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[PATCH 3/57][Arm][GAS] Add support for MVE instructions: vabs and vneg
gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (do_neon_abs_neg): Make it accept MVE variant. (insns): Change vabs and vneg entries to accept MVE variants. * testsuite/gas/arm/mve-vabsneg-bad-1.d: New test. * testsuite/gas/arm/mve-vabsneg-bad-1.l: New test. * testsuite/gas/arm/mve-vabsneg-bad-1.s: New test. * testsuite/gas/arm/mve-vabsneg-bad-2.d: New test. * testsuite/gas/arm/mve-vabsneg-bad-2.l: New test. * testsuite/gas/arm/mve-vabsneg-bad-2.s: New test.
This commit is contained in:
Andre Vieira
@ -1,3 +1,14 @@
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (do_neon_abs_neg): Make it accept MVE variant.
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(insns): Change vabs and vneg entries to accept MVE variants.
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* testsuite/gas/arm/mve-vabsneg-bad-1.d: New test.
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* testsuite/gas/arm/mve-vabsneg-bad-1.l: New test.
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* testsuite/gas/arm/mve-vabsneg-bad-1.s: New test.
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* testsuite/gas/arm/mve-vabsneg-bad-2.d: New test.
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* testsuite/gas/arm/mve-vabsneg-bad-2.l: New test.
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* testsuite/gas/arm/mve-vabsneg-bad-2.s: New test.
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (enum it_instruction_type): Rename to...
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@ -15950,12 +15950,13 @@ do_neon_abs_neg (void)
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if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
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return;
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if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
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return;
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rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
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et = neon_check_type (2, rs, N_EQK, N_S_32 | N_F_16_32 | N_KEY);
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if (check_simd_pred_availability (et.type == NT_float,
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NEON_CHECK_ARCH | NEON_CHECK_CC))
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return;
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inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
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inst.instruction |= HI1 (inst.operands[0].reg) << 22;
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inst.instruction |= LOW4 (inst.operands[1].reg);
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@ -21909,9 +21910,6 @@ static const struct asm_opcode insns[] =
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nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
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nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
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NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg),
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NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg),
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NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
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NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
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NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
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@ -22643,6 +22641,9 @@ static const struct asm_opcode insns[] =
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mnCEF(vadd, _vadd, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_addsub_if_i),
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mnCEF(vsub, _vsub, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_addsub_if_i),
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MNCEF(vabs, 1b10300, 2, (RNSDQMQ, RNSDQMQ), neon_abs_neg),
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MNCEF(vneg, 1b10380, 2, (RNSDQMQ, RNSDQMQ), neon_abs_neg),
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#undef ARM_VARIANT
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#define ARM_VARIANT & fpu_neon_ext_v1
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mnUF(vabd, _vabd, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su),
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6
gas/testsuite/gas/arm/mve-vabsneg-bad-1.d
Normal file
6
gas/testsuite/gas/arm/mve-vabsneg-bad-1.d
Normal file
@ -0,0 +1,6 @@
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#name: bad MVE VABS and VNEG instructions
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#as: -march=armv8.1-m.main+mve
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#error_output: mve-vabsneg-bad-1.l
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.*: +file format .*arm.*
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33
gas/testsuite/gas/arm/mve-vabsneg-bad-1.l
Normal file
33
gas/testsuite/gas/arm/mve-vabsneg-bad-1.l
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@ -0,0 +1,33 @@
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[^:]*: Assembler messages:
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[^:]*:13: Error: bad type in SIMD instruction -- `vabs.p8 q0,q1'
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[^:]*:14: Error: bad type in SIMD instruction -- `vabs.p16 q0,q1'
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[^:]*:15: Error: bad type in SIMD instruction -- `vabs.u8 q0,q1'
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[^:]*:16: Error: bad type in SIMD instruction -- `vabs.u16 q0,q1'
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[^:]*:17: Error: bad type in SIMD instruction -- `vabs.u32 q0,q1'
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[^:]*:18: Error: selected FPU does not support instruction -- `vabs.f16 q0,q1'
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[^:]*:19: Error: selected FPU does not support instruction -- `vabs.f32 q0,q1'
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[^:]*:20: Error: bad type in SIMD instruction -- `vabs.s64 q0,q1'
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[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:22: Error: bad type in SIMD instruction -- `vneg.p8 q0,q1'
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[^:]*:23: Error: bad type in SIMD instruction -- `vneg.p16 q0,q1'
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[^:]*:24: Error: bad type in SIMD instruction -- `vneg.u8 q0,q1'
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[^:]*:25: Error: bad type in SIMD instruction -- `vneg.u16 q0,q1'
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[^:]*:26: Error: bad type in SIMD instruction -- `vneg.u32 q0,q1'
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[^:]*:27: Error: selected FPU does not support instruction -- `vneg.f16 q0,q1'
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[^:]*:28: Error: selected FPU does not support instruction -- `vneg.f32 q0,q1'
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[^:]*:29: Error: bad type in SIMD instruction -- `vneg.s64 q0,q1'
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[^:]*:30: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:30: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:30: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:30: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:30: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:30: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:32: Error: syntax error -- `vnegeq.s32 q0,q1'
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[^:]*:33: Error: syntax error -- `vnegeq.s32 q0,q1'
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[^:]*:35: Error: instruction missing MVE vector predication code -- `vneg.s32 q0,q1'
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[^:]*:36: Error: vector predicated instruction should be in VPT/VPST block -- `vnegt.s32 q0,q1'
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37
gas/testsuite/gas/arm/mve-vabsneg-bad-1.s
Normal file
37
gas/testsuite/gas/arm/mve-vabsneg-bad-1.s
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@ -0,0 +1,37 @@
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.macro cond op
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.irp cond, eq, ne, gt, ge, lt, le
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it \cond
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\op\().s32 q0, q1
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.endr
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.endm
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.syntax unified
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.text
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.thumb
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vabs.p8 q0, q1
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vabs.p16 q0, q1
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vabs.u8 q0, q1
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vabs.u16 q0, q1
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vabs.u32 q0, q1
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vabs.f16 q0, q1
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vabs.f32 q0, q1
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vabs.s64 q0, q1
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cond vabs
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vneg.p8 q0, q1
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vneg.p16 q0, q1
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vneg.u8 q0, q1
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vneg.u16 q0, q1
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vneg.u32 q0, q1
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vneg.f16 q0, q1
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vneg.f32 q0, q1
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vneg.s64 q0, q1
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cond vneg
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it eq
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vnegeq.s32 q0, q1
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vnegeq.s32 q0, q1
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vpst
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vneg.s32 q0, q1
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vnegt.s32 q0, q1
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6
gas/testsuite/gas/arm/mve-vabsneg-bad-2.d
Normal file
6
gas/testsuite/gas/arm/mve-vabsneg-bad-2.d
Normal file
@ -0,0 +1,6 @@
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#name: bad MVE FP VABS and VNEG instructions
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#as: -march=armv8.1-m.main+mve.fp
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#error_output: mve-vabsneg-bad-2.l
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.*: +file format .*arm.*
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29
gas/testsuite/gas/arm/mve-vabsneg-bad-2.l
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29
gas/testsuite/gas/arm/mve-vabsneg-bad-2.l
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@ -0,0 +1,29 @@
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[^:]*: Assembler messages:
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[^:]*:13: Error: bad type in SIMD instruction -- `vabs.p8 q0,q1'
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[^:]*:14: Error: bad type in SIMD instruction -- `vabs.p16 q0,q1'
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[^:]*:15: Error: bad type in SIMD instruction -- `vabs.u8 q0,q1'
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[^:]*:16: Error: bad type in SIMD instruction -- `vabs.u16 q0,q1'
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[^:]*:17: Error: bad type in SIMD instruction -- `vabs.u32 q0,q1'
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[^:]*:18: Error: bad type in SIMD instruction -- `vabs.s64 q0,q1'
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[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:20: Error: bad type in SIMD instruction -- `vneg.p8 q0,q1'
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[^:]*:21: Error: bad type in SIMD instruction -- `vneg.p16 q0,q1'
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[^:]*:22: Error: bad type in SIMD instruction -- `vneg.u8 q0,q1'
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[^:]*:23: Error: bad type in SIMD instruction -- `vneg.u16 q0,q1'
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[^:]*:24: Error: bad type in SIMD instruction -- `vneg.u32 q0,q1'
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[^:]*:25: Error: bad type in SIMD instruction -- `vneg.s64 q0,q1'
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:28: Error: syntax error -- `vnegeq.f32 q0,q1'
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[^:]*:29: Error: syntax error -- `vnegeq.f32 q0,q1'
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[^:]*:31: Error: instruction missing MVE vector predication code -- `vneg.f32 q0,q1'
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[^:]*:32: Error: vector predicated instruction should be in VPT/VPST block -- `vnegt.f32 q0,q1'
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32
gas/testsuite/gas/arm/mve-vabsneg-bad-2.s
Normal file
32
gas/testsuite/gas/arm/mve-vabsneg-bad-2.s
Normal file
@ -0,0 +1,32 @@
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.macro cond op
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.irp cond, eq, ne, gt, ge, lt, le
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it \cond
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\op\().s32 q0, q1
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.endr
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.endm
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.syntax unified
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.text
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.thumb
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vabs.p8 q0, q1
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vabs.p16 q0, q1
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vabs.u8 q0, q1
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vabs.u16 q0, q1
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vabs.u32 q0, q1
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vabs.s64 q0, q1
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cond vabs
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vneg.p8 q0, q1
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vneg.p16 q0, q1
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vneg.u8 q0, q1
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vneg.u16 q0, q1
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vneg.u32 q0, q1
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vneg.s64 q0, q1
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cond vneg
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it eq
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vnegeq.f32 q0, q1
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vnegeq.f32 q0, q1
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vpst
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vneg.f32 q0, q1
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vnegt.f32 q0, q1
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