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https://github.com/espressif/binutils-gdb.git
synced 2025-06-22 11:00:01 +08:00
x86: derive opcode encoding space attribute from base opcode
Just like is already done for VEX/XOP/EVEX encoded insns, record the encoding space information in the respective opcode modifier field. Do this again without changing the source table, but rather by deriving the values from their existing source representation.
This commit is contained in:
Jan Beulich
@ -1,3 +1,26 @@
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2021-03-29 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (optimize_encoding): Replace VEX-encoding
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checks by opcodespace ones.
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(insert_lfence_before): Likewise.
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(maybe_fused_with_jcc_p): Likewise.
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(add_branch_padding_frag_p): Likewise.
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(output_disp): Likewise.
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(load_insn_p): Re-arrange checks to key applicable ones off of
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an opcodespace check.
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(md_assemble): Adjust opcode checks.
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(check_byte_reg): Likewise.
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(process_operands): Likewise.
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(i386_index_check): Likewise.
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(process_suffix): Likewise. New local variable is_movx. Adjust
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movsx/movzx and crc32 handling.
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(output_insn): Adjust opcode checks. Drop no longer reachable
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case labels. Output legacy encoding prefixes in addition to the
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base_opcode byte(s). Rework counting of prefixes for extended
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opcode maps.
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* config/tc-i386-intel.c (i386_intel_simplify_register): Adjust
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opcode checks.
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2021-03-29 Alan Modra <amodra@gmail.com>
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* atof-generic.c (FALSE, TRUE): Don't define.
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@ -318,9 +318,11 @@ i386_intel_simplify_register (expressionS *e)
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if (intel_state.in_scale
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|| (t->opcode_modifier.opcodeprefix == PREFIX_0XF3
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&& t->base_opcode == 0x0f1b /* bndmk */)
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&& t->opcode_modifier.opcodespace == SPACE_0F
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&& t->base_opcode == 0x1b /* bndmk */)
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|| (t->opcode_modifier.opcodeprefix == PREFIX_NONE
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&& (t->base_opcode & ~1) == 0x0f1a /* bnd{ld,st}x */)
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&& t->opcode_modifier.opcodespace == SPACE_0F
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&& (t->base_opcode & ~1) == 0x1a /* bnd{ld,st}x */)
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|| i386_regtab[reg_num].reg_type.bitfield.baseindex)
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intel_state.index = i386_regtab + reg_num;
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else
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@ -4040,7 +4040,7 @@ optimize_encoding (void)
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unsigned int j;
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if (optimize_for_space
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&& !is_any_vex_encoding (&i.tm)
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&& i.tm.opcode_modifier.opcodespace == SPACE_BASE
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&& i.reg_operands == 1
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&& i.imm_operands == 1
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&& !i.types[1].bitfield.byte
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@ -4072,7 +4072,7 @@ optimize_encoding (void)
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}
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}
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else if (flag_code == CODE_64BIT
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&& !is_any_vex_encoding (&i.tm)
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&& i.tm.opcode_modifier.opcodespace == SPACE_BASE
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&& ((i.types[1].bitfield.qword
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&& i.reg_operands == 1
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&& i.imm_operands == 1
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@ -4138,7 +4138,7 @@ optimize_encoding (void)
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}
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else if (optimize > 1
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&& !optimize_for_space
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&& !is_any_vex_encoding (&i.tm)
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&& i.tm.opcode_modifier.opcodespace == SPACE_BASE
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&& i.reg_operands == 2
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&& i.op[0].regs == i.op[1].regs
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&& ((i.tm.base_opcode & ~(Opcode_D | 1)) == 0x8
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@ -4343,9 +4343,15 @@ load_insn_p (void)
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if (i.tm.opcode_modifier.anysize)
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return 0;
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/* pop, popf, popa. */
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if (strcmp (i.tm.name, "pop") == 0
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|| i.tm.base_opcode == 0x9d
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/* pop. */
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if (strcmp (i.tm.name, "pop") == 0)
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return 1;
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}
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if (i.tm.opcode_modifier.opcodespace == SPACE_BASE)
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{
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/* popf, popa. */
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if (i.tm.base_opcode == 0x9d
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|| i.tm.base_opcode == 0x61)
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return 1;
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@ -4375,7 +4381,7 @@ load_insn_p (void)
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&& i.tm.extension_opcode == 2)
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return 1;
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}
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else
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else if (i.tm.opcode_modifier.opcodespace == SPACE_BASE)
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{
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/* test, not, neg, mul, imul, div, idiv. */
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if ((i.tm.base_opcode == 0xf6 || i.tm.base_opcode == 0xf7)
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@ -4390,40 +4396,14 @@ load_insn_p (void)
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if (i.tm.base_opcode >= 0x80 && i.tm.base_opcode <= 0x83)
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return 1;
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/* bt, bts, btr, btc. */
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if (i.tm.base_opcode == 0xfba
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&& (i.tm.extension_opcode >= 4 && i.tm.extension_opcode <= 7))
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return 1;
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/* rol, ror, rcl, rcr, shl/sal, shr, sar. */
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if ((base_opcode == 0xc1
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|| (i.tm.base_opcode >= 0xd0 && i.tm.base_opcode <= 0xd3))
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&& i.tm.extension_opcode != 6)
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return 1;
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/* cmpxchg8b, cmpxchg16b, xrstors, vmptrld. */
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if (i.tm.base_opcode == 0xfc7
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&& i.tm.opcode_modifier.opcodeprefix == PREFIX_NONE
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&& (i.tm.extension_opcode == 1 || i.tm.extension_opcode == 3
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|| i.tm.extension_opcode == 6))
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return 1;
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/* fxrstor, ldmxcsr, xrstor. */
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if (i.tm.base_opcode == 0xfae
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&& (i.tm.extension_opcode == 1
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|| i.tm.extension_opcode == 2
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|| i.tm.extension_opcode == 5))
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return 1;
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/* lgdt, lidt, lmsw. */
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if (i.tm.base_opcode == 0xf01
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&& (i.tm.extension_opcode == 2
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|| i.tm.extension_opcode == 3
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|| i.tm.extension_opcode == 6))
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return 1;
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/* Check for x87 instructions. */
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if (i.tm.base_opcode >= 0xd8 && i.tm.base_opcode <= 0xdf)
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if (base_opcode >= 0xd8 && base_opcode <= 0xdf)
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{
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/* Skip fst, fstp, fstenv, fstcw. */
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if (i.tm.base_opcode == 0xd9
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@ -4462,6 +4442,34 @@ load_insn_p (void)
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return 1;
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}
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}
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else if (i.tm.opcode_modifier.opcodespace == SPACE_0F)
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{
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/* bt, bts, btr, btc. */
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if (i.tm.base_opcode == 0xba
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&& (i.tm.extension_opcode >= 4 && i.tm.extension_opcode <= 7))
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return 1;
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/* cmpxchg8b, cmpxchg16b, xrstors, vmptrld. */
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if (i.tm.base_opcode == 0xc7
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&& i.tm.opcode_modifier.opcodeprefix == PREFIX_NONE
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&& (i.tm.extension_opcode == 1 || i.tm.extension_opcode == 3
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|| i.tm.extension_opcode == 6))
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return 1;
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/* fxrstor, ldmxcsr, xrstor. */
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if (i.tm.base_opcode == 0xae
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&& (i.tm.extension_opcode == 1
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|| i.tm.extension_opcode == 2
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|| i.tm.extension_opcode == 5))
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return 1;
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/* lgdt, lidt, lmsw. */
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if (i.tm.base_opcode == 0x01
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&& (i.tm.extension_opcode == 2
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|| i.tm.extension_opcode == 3
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|| i.tm.extension_opcode == 6))
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return 1;
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}
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dest = i.operands - 1;
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@ -4471,8 +4479,8 @@ load_insn_p (void)
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&& i.types[dest].bitfield.imm8)
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dest--;
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/* add, or, adc, sbb, and, sub, xor, cmp, test, xchg, xadd */
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if (!any_vex_p
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/* add, or, adc, sbb, and, sub, xor, cmp, test, xchg. */
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if (i.tm.opcode_modifier.opcodespace == SPACE_BASE
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&& (base_opcode == 0x1
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|| base_opcode == 0x9
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|| base_opcode == 0x11
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@ -4481,8 +4489,12 @@ load_insn_p (void)
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|| base_opcode == 0x29
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|| base_opcode == 0x31
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|| base_opcode == 0x39
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|| (i.tm.base_opcode >= 0x84 && i.tm.base_opcode <= 0x87)
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|| base_opcode == 0xfc1))
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|| (base_opcode | 2) == 0x87))
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return 1;
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/* xadd. */
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if (i.tm.opcode_modifier.opcodespace == SPACE_0F
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&& base_opcode == 0xc1)
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return 1;
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/* Check for load instruction. */
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@ -4527,7 +4539,7 @@ insert_lfence_before (void)
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{
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char *p;
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if (is_any_vex_encoding (&i.tm))
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if (i.tm.opcode_modifier.opcodespace != SPACE_BASE)
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return;
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if (i.tm.base_opcode == 0xff
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@ -4908,7 +4920,8 @@ md_assemble (char *line)
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/* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
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instructions may define INT_OPCODE as well, so avoid this corner
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case for those instructions that use MODRM. */
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if (i.tm.base_opcode == INT_OPCODE
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if (i.tm.opcode_modifier.opcodespace == SPACE_BASE
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&& i.tm.base_opcode == INT_OPCODE
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&& !i.tm.opcode_modifier.modrm
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&& i.op[0].imms->X_add_number == 3)
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{
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@ -6289,7 +6302,8 @@ match_template (char mnem_suffix)
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j = i.imm_operands + (t->operands > i.imm_operands + 1);
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if (((i.suffix == QWORD_MNEM_SUFFIX
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&& flag_code != CODE_64BIT
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&& !(t->base_opcode == 0xfc7
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&& !(t->opcode_modifier.opcodespace == SPACE_0F
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&& t->base_opcode == 0xc7
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&& t->opcode_modifier.opcodeprefix == PREFIX_NONE
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&& t->extension_opcode == 1) /* cmpxchg8b */)
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|| (i.suffix == LONG_MNEM_SUFFIX
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@ -6740,7 +6754,7 @@ check_string (void)
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static int
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process_suffix (void)
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{
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bfd_boolean is_crc32 = FALSE;
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bfd_boolean is_crc32 = FALSE, is_movx = FALSE;
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/* If matched instruction specifies an explicit instruction mnemonic
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suffix, use it. */
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@ -6755,17 +6769,23 @@ process_suffix (void)
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&& !i.tm.opcode_modifier.addrprefixopreg)
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{
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unsigned int numop = i.operands;
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/* MOVSX/MOVZX */
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is_movx = (i.tm.opcode_modifier.opcodespace == SPACE_0F
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&& (i.tm.base_opcode | 8) == 0xbe)
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|| (i.tm.opcode_modifier.opcodespace == SPACE_BASE
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&& i.tm.base_opcode == 0x63
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&& i.tm.cpu_flags.bitfield.cpu64);
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/* CRC32 */
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is_crc32 = (i.tm.base_opcode == 0xf38f0
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is_crc32 = (i.tm.base_opcode == 0xf0
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&& i.tm.opcode_modifier.opcodespace == SPACE_0F38
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&& i.tm.opcode_modifier.opcodeprefix == PREFIX_0XF2);
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/* movsx/movzx want only their source operand considered here, for the
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ambiguity checking below. The suffix will be replaced afterwards
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to represent the destination (register). */
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if (((i.tm.base_opcode | 8) == 0xfbe && i.tm.opcode_modifier.w)
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|| (i.tm.base_opcode == 0x63
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&& i.tm.opcode_modifier.opcodespace == SPACE_BASE
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&& i.tm.cpu_flags.bitfield.cpu64))
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if (is_movx && (i.tm.opcode_modifier.w || i.tm.base_opcode == 0x63))
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--i.operands;
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/* crc32 needs REX.W set regardless of suffix / source operand size. */
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@ -6803,8 +6823,7 @@ process_suffix (void)
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/* As an exception, movsx/movzx silently default to a byte source
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in AT&T mode. */
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if ((i.tm.base_opcode | 8) == 0xfbe && i.tm.opcode_modifier.w
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&& !i.suffix && !intel_syntax)
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if (is_movx && i.tm.opcode_modifier.w && !i.suffix && !intel_syntax)
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i.suffix = BYTE_MNEM_SUFFIX;
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}
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else if (i.suffix == BYTE_MNEM_SUFFIX)
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@ -6883,7 +6902,8 @@ process_suffix (void)
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&& (i.tm.opcode_modifier.jump == JUMP_ABSOLUTE
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|| i.tm.opcode_modifier.jump == JUMP_BYTE
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|| i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT
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|| (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
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|| (i.tm.opcode_modifier.opcodespace == SPACE_0F
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&& i.tm.base_opcode == 0x01 /* [ls][gi]dt */
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&& i.tm.extension_opcode <= 3)))
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{
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switch (flag_code)
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@ -7011,10 +7031,7 @@ process_suffix (void)
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if (i.tm.opcode_modifier.floatmf)
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i.suffix = SHORT_MNEM_SUFFIX;
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else if ((i.tm.base_opcode | 8) == 0xfbe
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|| (i.tm.base_opcode == 0x63
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&& i.tm.opcode_modifier.opcodespace == SPACE_BASE
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&& i.tm.cpu_flags.bitfield.cpu64))
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else if (is_movx)
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/* handled below */;
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else if (evex)
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i.tm.opcode_modifier.evex = evex;
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@ -7027,10 +7044,7 @@ process_suffix (void)
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}
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}
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if ((i.tm.base_opcode | 8) == 0xfbe
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|| (i.tm.base_opcode == 0x63
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&& i.tm.opcode_modifier.opcodespace == SPACE_BASE
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&& i.tm.cpu_flags.bitfield.cpu64))
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if (is_movx)
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{
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/* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
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In AT&T syntax, if there is no suffix (warned about above), the default
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@ -7252,7 +7266,8 @@ check_byte_reg (void)
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continue;
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/* crc32 only wants its source operand checked here. */
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if (i.tm.base_opcode == 0xf38f0
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if (i.tm.base_opcode == 0xf0
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&& i.tm.opcode_modifier.opcodespace == SPACE_0F38
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&& i.tm.opcode_modifier.opcodeprefix == PREFIX_0XF2
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&& op != 0)
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continue;
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@ -7678,21 +7693,23 @@ process_operands (void)
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if (flag_code != CODE_64BIT
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? i.tm.base_opcode == POP_SEG_SHORT
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&& i.op[0].regs->reg_num == 1
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: (i.tm.base_opcode | 1) == POP_SEG386_SHORT
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: (i.tm.base_opcode | 1) == (POP_SEG386_SHORT & 0xff)
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&& i.op[0].regs->reg_num < 4)
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{
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as_bad (_("you can't `%s %s%s'"),
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i.tm.name, register_prefix, i.op[0].regs->reg_name);
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return 0;
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}
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if ( i.op[0].regs->reg_num > 3 && i.opcode_length == 1 )
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if (i.op[0].regs->reg_num > 3
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&& i.tm.opcode_modifier.opcodespace == SPACE_BASE )
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{
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i.tm.base_opcode ^= POP_SEG_SHORT ^ POP_SEG386_SHORT;
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i.opcode_length = 2;
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i.tm.base_opcode ^= (POP_SEG_SHORT ^ POP_SEG386_SHORT) & 0xff;
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i.tm.opcode_modifier.opcodespace = SPACE_0F;
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}
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i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
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}
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else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
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else if (i.tm.opcode_modifier.opcodespace == SPACE_BASE
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&& (i.tm.base_opcode & ~3) == MOV_AX_DISP32)
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{
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default_seg = &ds;
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}
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@ -8949,8 +8966,8 @@ maybe_fused_with_jcc_p (enum mf_cmp_kind* mf_cmp_p)
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if (i.base_reg && i.base_reg->reg_num == RegIP)
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return 0;
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/* No VEX/EVEX encoding. */
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if (is_any_vex_encoding (&i.tm))
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/* No opcodes outside of base encoding space. */
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if (i.tm.opcode_modifier.opcodespace != SPACE_BASE)
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return 0;
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/* add, sub without add/sub m, imm. */
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@ -9073,7 +9090,8 @@ add_branch_padding_frag_p (enum align_branch_kind *branch_p,
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/* NB: Don't work with COND_JUMP86 without i386. */
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if (!align_branch_power
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|| now_seg == absolute_section
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|| !cpu_arch_flags.bitfield.cpui386)
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|| !cpu_arch_flags.bitfield.cpui386
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|| i.tm.opcode_modifier.opcodespace != SPACE_BASE)
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return 0;
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add_padding = 0;
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@ -9096,8 +9114,6 @@ add_branch_padding_frag_p (enum align_branch_kind *branch_p,
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add_padding = 1;
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}
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}
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else if (is_any_vex_encoding (&i.tm))
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return 0;
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else if ((i.tm.base_opcode | 1) == 0xc3)
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{
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/* Near ret. */
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@ -9181,8 +9197,10 @@ output_insn (void)
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x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X87;
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||||
if ((i.xstate & xstate_mmx)
|
||||
|| i.tm.base_opcode == 0xf77 /* emms */
|
||||
|| i.tm.base_opcode == 0xf0e /* femms */)
|
||||
|| (i.tm.opcode_modifier.opcodespace == SPACE_0F
|
||||
&& !is_any_vex_encoding (&i.tm)
|
||||
&& (i.tm.base_opcode == 0x77 /* emms */
|
||||
|| i.tm.base_opcode == 0x0e /* femms */)))
|
||||
x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MMX;
|
||||
|
||||
if (i.index_reg)
|
||||
@ -9200,10 +9218,10 @@ output_insn (void)
|
||||
i.xstate |= xstate_ymm;
|
||||
|
||||
if ((i.xstate & xstate_xmm)
|
||||
/* ldmxcsr / stmxcsr */
|
||||
|| (i.tm.base_opcode == 0xfae && i.tm.cpu_flags.bitfield.cpusse)
|
||||
/* vldmxcsr / vstmxcsr */
|
||||
|| (i.tm.base_opcode == 0xae && i.tm.cpu_flags.bitfield.cpuavx)
|
||||
/* ldmxcsr / stmxcsr / vldmxcsr / vstmxcsr */
|
||||
|| (i.tm.base_opcode == 0xae
|
||||
&& (i.tm.cpu_flags.bitfield.cpusse
|
||||
|| i.tm.cpu_flags.bitfield.cpuavx))
|
||||
|| i.tm.cpu_flags.bitfield.cpuwidekl
|
||||
|| i.tm.cpu_flags.bitfield.cpukl)
|
||||
x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XMM;
|
||||
@ -9226,7 +9244,8 @@ output_insn (void)
|
||||
if (x86_feature_2_used
|
||||
|| i.tm.cpu_flags.bitfield.cpucmov
|
||||
|| i.tm.cpu_flags.bitfield.cpusyscall
|
||||
|| (i.tm.base_opcode == 0xfc7
|
||||
|| (i.tm.opcode_modifier.opcodespace == SPACE_0F
|
||||
&& i.tm.base_opcode == 0xc7
|
||||
&& i.tm.opcode_modifier.opcodeprefix == PREFIX_NONE
|
||||
&& i.tm.extension_opcode == 1) /* cmpxchg8b */)
|
||||
x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_BASELINE;
|
||||
@ -9327,9 +9346,9 @@ output_insn (void)
|
||||
enum mf_cmp_kind mf_cmp;
|
||||
|
||||
if (avoid_fence
|
||||
&& (i.tm.base_opcode == 0xfaee8
|
||||
|| i.tm.base_opcode == 0xfaef0
|
||||
|| i.tm.base_opcode == 0xfaef8))
|
||||
&& (i.tm.base_opcode == 0xaee8
|
||||
|| i.tm.base_opcode == 0xaef0
|
||||
|| i.tm.base_opcode == 0xaef8))
|
||||
{
|
||||
/* Encode lfence, mfence, and sfence as
|
||||
f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
|
||||
@ -9411,7 +9430,6 @@ output_insn (void)
|
||||
case PREFIX_NONE:
|
||||
switch (i.opcode_length)
|
||||
{
|
||||
case 3:
|
||||
case 2:
|
||||
break;
|
||||
case 1:
|
||||
@ -9482,36 +9500,55 @@ output_insn (void)
|
||||
}
|
||||
|
||||
/* Now the opcode; be careful about word order here! */
|
||||
j = i.opcode_length;
|
||||
if (!i.vex.length)
|
||||
switch (i.tm.opcode_modifier.opcodespace)
|
||||
{
|
||||
case SPACE_BASE:
|
||||
break;
|
||||
case SPACE_0F:
|
||||
++j;
|
||||
break;
|
||||
case SPACE_0F38:
|
||||
case SPACE_0F3A:
|
||||
j += 2;
|
||||
break;
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
|
||||
if (now_seg == absolute_section)
|
||||
abs_section_offset += i.opcode_length;
|
||||
else if (i.opcode_length == 1)
|
||||
abs_section_offset += j;
|
||||
else if (j == 1)
|
||||
{
|
||||
FRAG_APPEND_1_CHAR (i.tm.base_opcode);
|
||||
}
|
||||
else
|
||||
{
|
||||
p = frag_more (j);
|
||||
if (!i.vex.length
|
||||
&& i.tm.opcode_modifier.opcodespace != SPACE_BASE)
|
||||
{
|
||||
*p++ = 0x0f;
|
||||
if (i.tm.opcode_modifier.opcodespace != SPACE_0F)
|
||||
*p++ = i.tm.opcode_modifier.opcodespace == SPACE_0F38
|
||||
? 0x38 : 0x3a;
|
||||
}
|
||||
|
||||
switch (i.opcode_length)
|
||||
{
|
||||
case 4:
|
||||
p = frag_more (4);
|
||||
*p++ = (i.tm.base_opcode >> 24) & 0xff;
|
||||
*p++ = (i.tm.base_opcode >> 16) & 0xff;
|
||||
break;
|
||||
case 3:
|
||||
p = frag_more (3);
|
||||
*p++ = (i.tm.base_opcode >> 16) & 0xff;
|
||||
break;
|
||||
case 2:
|
||||
p = frag_more (2);
|
||||
/* Put out high byte first: can't use md_number_to_chars! */
|
||||
*p++ = (i.tm.base_opcode >> 8) & 0xff;
|
||||
/* Fall through. */
|
||||
case 1:
|
||||
*p = i.tm.base_opcode & 0xff;
|
||||
break;
|
||||
default:
|
||||
abort ();
|
||||
break;
|
||||
}
|
||||
|
||||
/* Put out high byte first: can't use md_number_to_chars! */
|
||||
*p++ = (i.tm.base_opcode >> 8) & 0xff;
|
||||
*p = i.tm.base_opcode & 0xff;
|
||||
}
|
||||
|
||||
/* Now the modrm byte and sib byte (if present). */
|
||||
@ -9566,28 +9603,16 @@ output_insn (void)
|
||||
|
||||
/* Count prefixes for extended opcode maps. */
|
||||
if (!i.vex.length)
|
||||
switch (i.opcode_length)
|
||||
switch (i.tm.opcode_modifier.opcodespace)
|
||||
{
|
||||
case 3:
|
||||
if (((i.tm.base_opcode >> 16) & 0xff) == 0xf)
|
||||
{
|
||||
count++;
|
||||
switch ((i.tm.base_opcode >> 8) & 0xff)
|
||||
{
|
||||
case 0x38:
|
||||
case 0x3a:
|
||||
count++;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
case SPACE_BASE:
|
||||
break;
|
||||
case 2:
|
||||
if (((i.tm.base_opcode >> 8) & 0xff) == 0xf)
|
||||
count++;
|
||||
case SPACE_0F:
|
||||
count++;
|
||||
break;
|
||||
case 1:
|
||||
case SPACE_0F38:
|
||||
case SPACE_0F3A:
|
||||
count += 2;
|
||||
break;
|
||||
default:
|
||||
abort ();
|
||||
@ -9807,7 +9832,7 @@ output_disp (fragS *insn_start_frag, offsetT insn_start_off)
|
||||
&& i.rm.regmem == 5))
|
||||
&& (i.rm.mode == 2
|
||||
|| (i.rm.mode == 0 && i.rm.regmem == 5))
|
||||
&& !is_any_vex_encoding(&i.tm)
|
||||
&& i.tm.opcode_modifier.opcodespace == SPACE_BASE
|
||||
&& ((i.operands == 1
|
||||
&& i.tm.base_opcode == 0xff
|
||||
&& (i.rm.reg == 2 || i.rm.reg == 4))
|
||||
@ -11103,9 +11128,11 @@ i386_index_check (const char *operand_string)
|
||||
|
||||
/* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */
|
||||
if ((t->opcode_modifier.opcodeprefix == PREFIX_0XF3
|
||||
&& t->base_opcode == 0x0f1b)
|
||||
&& t->opcode_modifier.opcodespace == SPACE_0F
|
||||
&& t->base_opcode == 0x1b)
|
||||
|| (t->opcode_modifier.opcodeprefix == PREFIX_NONE
|
||||
&& (t->base_opcode & ~1) == 0x0f1a)
|
||||
&& t->opcode_modifier.opcodespace == SPACE_0F
|
||||
&& (t->base_opcode & ~1) == 0x1a)
|
||||
|| t->opcode_modifier.sib == SIBMEM)
|
||||
{
|
||||
/* They cannot use RIP-relative addressing. */
|
||||
@ -11117,7 +11144,8 @@ i386_index_check (const char *operand_string)
|
||||
|
||||
/* bndldx and bndstx ignore their scale factor. */
|
||||
if (t->opcode_modifier.opcodeprefix == PREFIX_NONE
|
||||
&& (t->base_opcode & ~1) == 0x0f1a
|
||||
&& t->opcode_modifier.opcodespace == SPACE_0F
|
||||
&& (t->base_opcode & ~1) == 0x1a
|
||||
&& i.log2_scale_factor)
|
||||
as_warn (_("register scaling is being ignored here"));
|
||||
}
|
||||
|
||||
@ -1,3 +1,13 @@
|
||||
2021-03-29 Jan Beulich <jbeulich@suse.com>
|
||||
|
||||
* i386-gen.c (process_i386_opcode_modifier): New parameter
|
||||
"space".
|
||||
(output_i386_opcode): New local variable "space". Adjust
|
||||
process_i386_opcode_modifier() invocation.
|
||||
(process_i386_opcodes): Adjust process_i386_opcode_modifier()
|
||||
invocation.
|
||||
* i386-tbl.h: Re-generate.
|
||||
|
||||
2021-03-29 Alan Modra <amodra@gmail.com>
|
||||
|
||||
* aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
|
||||
|
||||
@ -1176,8 +1176,8 @@ adjust_broadcast_modifier (char **opnd)
|
||||
}
|
||||
|
||||
static void
|
||||
process_i386_opcode_modifier (FILE *table, char *mod, unsigned int prefix,
|
||||
char **opnd, int lineno)
|
||||
process_i386_opcode_modifier (FILE *table, char *mod, unsigned int space,
|
||||
unsigned int prefix, char **opnd, int lineno)
|
||||
{
|
||||
char *str, *next, *last;
|
||||
bitfield modifiers [ARRAY_SIZE (opcode_modifiers)];
|
||||
@ -1220,6 +1220,19 @@ process_i386_opcode_modifier (FILE *table, char *mod, unsigned int prefix,
|
||||
}
|
||||
}
|
||||
|
||||
if (space)
|
||||
{
|
||||
if (!modifiers[OpcodeSpace].value)
|
||||
modifiers[OpcodeSpace].value = space;
|
||||
else if (modifiers[OpcodeSpace].value != space)
|
||||
fail (_("%s:%d: Conflicting opcode space specifications\n"),
|
||||
filename, lineno);
|
||||
else
|
||||
fprintf (stderr,
|
||||
_("%s:%d: Warning: redundant opcode space specification\n"),
|
||||
filename, lineno);
|
||||
}
|
||||
|
||||
if (prefix)
|
||||
{
|
||||
if (!modifiers[OpcodePrefix].value)
|
||||
@ -1355,7 +1368,7 @@ static void
|
||||
output_i386_opcode (FILE *table, const char *name, char *str,
|
||||
char *last, int lineno)
|
||||
{
|
||||
unsigned int i, length, prefix = 0;
|
||||
unsigned int i, length, prefix = 0, space = 0;
|
||||
char *base_opcode, *extension_opcode, *end;
|
||||
char *cpu_flags, *opcode_modifier, *operand_types [MAX_OPERANDS];
|
||||
unsigned long int opcode;
|
||||
@ -1427,10 +1440,27 @@ output_i386_opcode (FILE *table, const char *name, char *str,
|
||||
opcode &= (1UL << (8 * --length)) - 1;
|
||||
}
|
||||
|
||||
/* Transform opcode space encoded in the opcode into opcode modifier
|
||||
representation. */
|
||||
if (length > 1 && (opcode >> (8 * length - 8)) == 0xf)
|
||||
{
|
||||
switch ((opcode >> (8 * length - 16)) & 0xff)
|
||||
{
|
||||
default: space = SPACE_0F; break;
|
||||
case 0x38: space = SPACE_0F38; break;
|
||||
case 0x3A: space = SPACE_0F3A; break;
|
||||
}
|
||||
|
||||
if (space != SPACE_0F && --length == 1)
|
||||
fail (_("%s:%d: %s: unrecognized opcode encoding space\n"),
|
||||
filename, lineno, name);
|
||||
opcode &= (1UL << (8 * --length)) - 1;
|
||||
}
|
||||
|
||||
fprintf (table, " { \"%s\", 0x%0*lx%s, %s, %lu,\n",
|
||||
name, 2 * (int)length, opcode, end, extension_opcode, i);
|
||||
|
||||
process_i386_opcode_modifier (table, opcode_modifier, prefix,
|
||||
process_i386_opcode_modifier (table, opcode_modifier, space, prefix,
|
||||
operand_types, lineno);
|
||||
|
||||
process_i386_cpu_flag (table, cpu_flags, 0, ",", " ", lineno);
|
||||
@ -1822,7 +1852,7 @@ process_i386_opcodes (FILE *table)
|
||||
|
||||
fprintf (table, " { NULL, 0, 0, 0,\n");
|
||||
|
||||
process_i386_opcode_modifier (table, "0", 0, NULL, -1);
|
||||
process_i386_opcode_modifier (table, "0", 0, 0, NULL, -1);
|
||||
|
||||
process_i386_cpu_flag (table, "0", 0, ",", " ", -1);
|
||||
|
||||
|
||||
3192
opcodes/i386-tbl.h
3192
opcodes/i386-tbl.h
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user