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arm: Add unwind support for mixed register lists
* config/tc-arm.c (parse_reg_list): Add handling of mixed register types. (reg_names): Enumerate pseudoregister according to mapped physical register number. (s_arm_unwind_save_pseudo): Modify function signature. (s_arm_unwind_save_core): Likewise. (s_arm_unwind_save_mixed): New function. (s_arm_unwind_save): Generate register list mask to pass to nested functions. * testsuite/gas/arm/unwind-pacbti-m.s: Expand test for mixed register type lists. * testsuite/gas/arm/unwind-pacbti-m.d: Likewise. * testsuite/gas/arm/unwind-pacbti-m-readelf.d: Likewise.
This commit is contained in:
Victor Do Nascimento
committed by
Nick Clifton
Nick Clifton
parent
301fe55e9c
commit
3363d8560f
@ -1942,6 +1942,22 @@ parse_reg_list (char ** strp, enum reg_list_els etype)
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rt = REG_TYPE_PSEUDO;
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reg = arm_reg_parse (&str, rt);
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/* Skip over allowed registers of alternative types in mixed-type
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register lists. */
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if (reg == FAIL && rt == REG_TYPE_PSEUDO
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&& ((reg = arm_reg_parse (&str, REG_TYPE_RN)) != FAIL))
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{
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cur_reg = reg;
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continue;
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}
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else if (reg == FAIL && rt == REG_TYPE_RN
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&& ((reg = arm_reg_parse (&str, REG_TYPE_PSEUDO)) != FAIL))
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{
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cur_reg = reg;
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continue;
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}
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if (etype == REGLIST_CLRM)
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{
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if (reg == REG_SP || reg == REG_PC)
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@ -4281,22 +4297,11 @@ s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
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/* Parse a directive saving pseudo registers. */
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static void
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s_arm_unwind_save_pseudo (void)
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s_arm_unwind_save_pseudo (long range)
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{
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valueT op;
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long range;
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range = parse_reg_list (&input_line_pointer, REGLIST_PSEUDO);
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if (range == FAIL)
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{
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as_bad (_("expected pseudo register list"));
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ignore_rest_of_line ();
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return;
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}
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demand_empty_rest_of_line ();
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if (range & (1 << 9))
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if (range & (1 << 12))
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{
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/* Opcode for restoring RA_AUTH_CODE. */
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op = 0xb4;
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@ -4308,22 +4313,11 @@ s_arm_unwind_save_pseudo (void)
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/* Parse a directive saving core registers. */
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static void
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s_arm_unwind_save_core (void)
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s_arm_unwind_save_core (long range)
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{
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valueT op;
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long range;
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int n;
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range = parse_reg_list (&input_line_pointer, REGLIST_RN);
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if (range == FAIL)
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{
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as_bad (_("expected register list"));
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ignore_rest_of_line ();
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return;
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}
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demand_empty_rest_of_line ();
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/* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
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into .unwind_save {..., sp...}. We aren't bothered about the value of
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ip because it is clobbered by calls. */
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@ -4722,6 +4716,40 @@ s_arm_unwind_save_mmxwcg (void)
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ignore_rest_of_line ();
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}
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static void
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s_arm_unwind_save_mixed (long range, long mask_range)
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{
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const long roof = ((sizeof (long) * CHAR_BIT) - 1)
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- __builtin_clzl (mask_range);
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long subrange = 0;
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unsigned lim_lo = 0;
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unsigned lim_hi = 0;
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/* Iterate over pseudoregister to establish subrange bounds. */
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for (; lim_hi <= roof; lim_hi++)
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{
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if (mask_range & (1 << lim_hi))
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{
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/* Once we know where to split our range, construct subrange. */
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for (unsigned n = lim_lo; n < lim_hi; n++)
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{
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if (range & (1 << n))
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subrange |= (1 << n);
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}
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s_arm_unwind_save_core (subrange);
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s_arm_unwind_save_pseudo (1 << lim_hi);
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subrange = 0;
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lim_lo = lim_hi + 1;
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}
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}
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lim_lo = 0xffff << roof;
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subrange = range & lim_lo;
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s_arm_unwind_save_core (subrange);
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}
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/* Parse an unwind_save directive.
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If the argument is non-zero, this is a .vsave directive. */
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@ -4729,7 +4757,8 @@ s_arm_unwind_save_mmxwcg (void)
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static void
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s_arm_unwind_save (int arch_v6)
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{
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char *peek;
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char *peek, *mask_peek;
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long range, mask_range;
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struct reg_entry *reg;
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bool had_brace = false;
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@ -4737,7 +4766,7 @@ s_arm_unwind_save (int arch_v6)
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as_bad (MISSING_FNSTART);
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/* Figure out what sort of save we have. */
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peek = input_line_pointer;
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peek = mask_peek = input_line_pointer;
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if (*peek == '{')
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{
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@ -4767,13 +4796,35 @@ s_arm_unwind_save (int arch_v6)
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s_arm_unwind_save_fpa (reg->number);
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return;
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case REG_TYPE_RN:
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s_arm_unwind_save_core ();
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return;
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case REG_TYPE_PSEUDO:
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s_arm_unwind_save_pseudo ();
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return;
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case REG_TYPE_RN:
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mask_range = parse_reg_list (&mask_peek, REGLIST_PSEUDO);
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range = parse_reg_list (&input_line_pointer, REGLIST_RN);
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if (range == FAIL || mask_range == FAIL)
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{
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as_bad (_("expected register list"));
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ignore_rest_of_line ();
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return;
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}
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demand_empty_rest_of_line ();
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if (!mask_range)
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{
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s_arm_unwind_save_core (range);
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return;
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}
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else if (!range)
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{
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s_arm_unwind_save_pseudo (mask_range);
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return;
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}
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else
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{
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s_arm_unwind_save_mixed (range, mask_range);
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return;
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}
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case REG_TYPE_VFD:
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if (arch_v6)
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@ -23976,7 +24027,7 @@ static const struct reg_entry reg_names[] =
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for tc_arm_regname_to_dw2regnum to translate to DWARF reg number using
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134 + reg_number should the range 134 to 142 be used for more pseudo regs
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in the future. This also helps fit RA_AUTH_CODE into a bitmask. */
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REGDEF(ra_auth_code,9,PSEUDO),
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REGDEF(ra_auth_code,12,PSEUDO),
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};
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#undef REGDEF
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#undef REGNUM
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@ -6,11 +6,15 @@
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# VxWorks needs a special variant of this file.
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#skip: *-*-vxworks*
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Unwind section '.ARM.exidx' at offset 0x40 contains 1 entry:
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Unwind section '.ARM.exidx' at offset 0x60 contains 1 entry:
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0x0 <foo>: 0x80b4a8b0
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Compact model index: 0
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0x0 <foo>: @0x0
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Compact model index: 1
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0x84 0x00 pop {r14}
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0xb4 pop {ra_auth_code}
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0x84 0x00 pop {r14}
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0xb4 pop {ra_auth_code}
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0xa3 pop {r4, r5, r6, r7}
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0xb4 pop {ra_auth_code}
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0xa8 pop {r4, r14}
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0xb0 finish
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@ -8,16 +8,20 @@
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.*: file format.*
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RELOCATION RECORDS FOR \[.ARM.exidx\]:
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OFFSET TYPE VALUE
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OFFSET TYPE VALUE.
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00000000 R_ARM_PREL31 .text
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00000000 R_ARM_NONE __aeabi_unwind_cpp_pr0
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00000000 R_ARM_NONE __aeabi_unwind_cpp_pr1
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00000004 R_ARM_PREL31 .ARM.extab
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Contents of section .text:
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0000 (10b54df8 04cd5df8 04cb10bd|b510f84d cd04f85d cb04bd10) .*
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0000 (10b54df8 04cd5df8 04cb2de9 f050bde8|e8bd50f0 e92dcb04 f85dcd04 f84db510) .*
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0010 (f0502de9 0050bde8 005010bd|bd105000 e8bd5000 e92d50f0) .*
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Contents of section .ARM.extab:
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0000 (00840281 b40084b4 b0a8b4a3|a3b4a8b0 b48400b4 81028400) 00000000 .*
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Contents of section .ARM.exidx:
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0000 00000000 (b0a8b480|80b4a8b0) .*
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0000 00000000 00000000 .*
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Contents of section .ARM.attributes:
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0000 41(290000 00|000000 29)616561 62690001 (1f000000|0000001f) .*
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0010 05382e31 2d4d2e4d 41494e00 0615074d .*
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0020 09033202 34024a01 4c01 .*
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0020 09033202 34024a01 4c01 .*
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@ -16,5 +16,11 @@ foo:
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push {r12}
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.save {ra_auth_code}
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pop {r12}
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push {r4-r7, ip, lr}
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.save {r4-r7, ra_auth_code, lr}
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pop {r4-r7, ip, lr}
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push {ip, lr}
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.save {ra_auth_code, lr}
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pop {ip, lr}
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pop {r4, pc}
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.fnend
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