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RISC-V: Update the riscv_opts.[rvc|rve] in the riscv_set_arch.
We also need to update the riscv_opts.[rvc|rve] for elf attributes. Otherwise, the following case will fail, $ cat cadd.s .attribute arch, "rv64gc" c.add a0, a1 $ riscv64-unknown-elf-as cadd.s -o cadd.o cadd.s: Assembler messages: cadd.s:2: Error: illegal operands `c.add a0,a1 After applying this patch, $ riscv64-unknown-elf-as cadd.s -o cadd.o $ riscv64-unknown-elf-objdump -d cadd.o cadd.o: file format elf64-littleriscv Disassembly of section .text: 0000000000000000 <.text>: 0: 952e add a0,a0,a1 ... gas/ * config/tc-riscv.c (riscv_set_arch): Call riscv_set_rvc and riscv_set_rve both for -march and elf attributes. (riscv_after_parse_args): Likewise.
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@ -1,3 +1,9 @@
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2021-06-11 Nelson Chu <nelson.chu@sifive.com>
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* config/tc-riscv.c (riscv_set_arch): Call riscv_set_rvc
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and riscv_set_rve both for -march and elf attributes.
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(riscv_after_parse_args): Likewise.
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2021-06-10 Jan Beulich <jbeulich@suse.com>
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* config/tc-arm.c (do_bfloat_vfma): Rename index to idx.
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@ -417,6 +417,14 @@ riscv_set_arch (const char *s)
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riscv_release_subset_list (&riscv_subsets);
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riscv_parse_subset (&rps, s);
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/* To support .option rvc and rve. */
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riscv_set_rvc (false);
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if (riscv_subset_supports ("c"))
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riscv_set_rvc (true);
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riscv_set_rve (false);
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if (riscv_subset_supports ("e"))
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riscv_set_rve (true);
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}
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/* Indicate -mabi option is explictly set. */
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@ -2945,16 +2953,6 @@ riscv_after_parse_args (void)
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riscv_set_arch (default_arch_with_ext);
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/* Add the RVC extension, regardless of -march, to support .option rvc. */
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riscv_set_rvc (false);
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if (riscv_subset_supports ("c"))
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riscv_set_rvc (true);
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/* Enable RVE if specified by the -march option. */
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riscv_set_rve (false);
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if (riscv_subset_supports ("e"))
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riscv_set_rve (true);
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/* If the CIE to be produced has not been overridden on the command line,
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then produce version 3 by default. This allows us to use the full
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range of registers in a .cfi_return_column directive. */
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