RISC-V: Add string length check for operands in AS

The current AS accepts invalid operands due to miss of operands length check.
For example, "e6" is an invalid operand in (vsetvli a0, a1, e6, mf8, tu, ma),
but it's still accepted by assembler.  In detail, the condition check "strncmp
(array[i], *s, len) == 0" in arg_lookup function passes with "strncmp ("e64",
"e6", 2)" in the case above.  So the generated encoding is same as that of
(vsetvli a0, a1, e64, mf8, tu, ma).

This patch fixes issue above by prompting an error in such case and also adds
a new testcase.

gas/ChangeLog:

        * config/tc-riscv.c (arg_lookup): Add string length check for operands.
        * testsuite/gas/riscv/vector-insns-fail-vsew.d: New testcase for an illegal vsew.
        * testsuite/gas/riscv/vector-insns-fail-vsew.l: Likewise.
        * testsuite/gas/riscv/vector-insns-fail-vsew.s: Likewise.

gas/config/tc-riscv.c

@@ -1206,7 +1206,8 @@ arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop)
     return false;
 
   for (i = 0; i < size; i++)
-    if (array[i] != NULL && strncmp (array[i], *s, len) == 0)
+    if (array[i] != NULL && strncmp (array[i], *s, len) == 0
+	&& array[i][len] == '\0')
       {
 	*regnop = i;
 	*s += len;

gas/testsuite/gas/riscv/vector-insns-fail-vsew.d

@@ -0,0 +1,3 @@
+#as: -march=rv32iv
+#source: vector-insns-fail-vsew.s
+#error_output: vector-insns-fail-vsew.l

gas/testsuite/gas/riscv/vector-insns-fail-vsew.l

@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: instruction vsetvli requires absolute expression
+.*: Error: illegal operands `vsetvli a0,a1,e6,mf8,tu,ma'

gas/testsuite/gas/riscv/vector-insns-fail-vsew.s

@@ -0,0 +1 @@
+	vsetvli  a0, a1, e6, mf8, tu, ma		# unrecognized vsew