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[PATCH 21/57][Arm][GAS] Add support for MVE instructions: vmaxv, vmaxav, vminv and vminav
gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (M_MNEM_vmaxv, M_MNEM_vmaxav, M_MNEM_vminv, M_MNEM_vminav): New instruction encodings. (do_mve_vmaxv): New encoding function. (insns): Add entries for new MVE mnemonics. * testsuite/gas/arm/mve-vmaxv-vminv-bad.d: New test. * testsuite/gas/arm/mve-vmaxv-vminv-bad.l: New test. * testsuite/gas/arm/mve-vmaxv-vminv-bad.s: New test.
This commit is contained in:
Andre Vieira
@ -1,3 +1,13 @@
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (M_MNEM_vmaxv, M_MNEM_vmaxav, M_MNEM_vminv,
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M_MNEM_vminav): New instruction encodings.
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(do_mve_vmaxv): New encoding function.
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(insns): Add entries for new MVE mnemonics.
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* testsuite/gas/arm/mve-vmaxv-vminv-bad.d: New test.
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* testsuite/gas/arm/mve-vmaxv-vminv-bad.l: New test.
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* testsuite/gas/arm/mve-vmaxv-vminv-bad.s: New test.
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (do_mve_vmaxnmv): New encoding function.
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* config/tc-arm.c (do_mve_vmaxnmv): New encoding function.
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@ -14163,6 +14163,10 @@ do_t_loloop (void)
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#define M_MNEM_vdwdup 0xee011f60
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#define M_MNEM_vdwdup 0xee011f60
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#define M_MNEM_vidup 0xee010f6e
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#define M_MNEM_vidup 0xee010f6e
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#define M_MNEM_viwdup 0xee010f60
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#define M_MNEM_viwdup 0xee010f60
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#define M_MNEM_vmaxv 0xeee20f00
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#define M_MNEM_vmaxav 0xeee00f00
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#define M_MNEM_vminv 0xeee20f80
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#define M_MNEM_vminav 0xeee00f80
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/* Neon instruction encoder helpers. */
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/* Neon instruction encoder helpers. */
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@ -17268,6 +17272,31 @@ do_mve_vmaxnmv (void)
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mve_encode_rq (et.size == 16, 64);
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mve_encode_rq (et.size == 16, 64);
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}
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}
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static void
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do_mve_vmaxv (void)
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{
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enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL);
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struct neon_type_el et;
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if (inst.instruction == M_MNEM_vmaxv || inst.instruction == M_MNEM_vminv)
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et = neon_check_type (2, rs, N_EQK, N_SU_MVE | N_KEY);
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else
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et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
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if (inst.cond > COND_ALWAYS)
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inst.pred_insn_type = INSIDE_VPT_INSN;
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else
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inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
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if (inst.operands[0].reg == REG_SP)
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as_tsktsk (MVE_BAD_SP);
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else if (inst.operands[0].reg == REG_PC)
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as_tsktsk (MVE_BAD_PC);
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mve_encode_rq (et.type == NT_unsigned, et.size);
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}
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static void
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static void
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do_neon_qrdmlah (void)
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do_neon_qrdmlah (void)
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{
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{
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@ -24434,6 +24463,10 @@ static const struct asm_opcode insns[] =
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mCEF(viwdup, _viwdup, 4, (RMQ, RRe, RR, EXPi), mve_viddup),
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mCEF(viwdup, _viwdup, 4, (RMQ, RRe, RR, EXPi), mve_viddup),
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mToC("vmaxa", ee330e81, 2, (RMQ, RMQ), mve_vmaxa_vmina),
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mToC("vmaxa", ee330e81, 2, (RMQ, RMQ), mve_vmaxa_vmina),
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mToC("vmina", ee331e81, 2, (RMQ, RMQ), mve_vmaxa_vmina),
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mToC("vmina", ee331e81, 2, (RMQ, RMQ), mve_vmaxa_vmina),
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mCEF(vmaxv, _vmaxv, 2, (RR, RMQ), mve_vmaxv),
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mCEF(vmaxav, _vmaxav, 2, (RR, RMQ), mve_vmaxv),
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mCEF(vminv, _vminv, 2, (RR, RMQ), mve_vmaxv),
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mCEF(vminav, _vminav, 2, (RR, RMQ), mve_vmaxv),
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#undef THUMB_VARIANT
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#undef THUMB_VARIANT
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#define THUMB_VARIANT & mve_fp_ext
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#define THUMB_VARIANT & mve_fp_ext
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5
gas/testsuite/gas/arm/mve-vmaxv-vminv-bad.d
Normal file
5
gas/testsuite/gas/arm/mve-vmaxv-vminv-bad.d
Normal file
@ -0,0 +1,5 @@
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#name: bad MVE VMAXV, VMAXAV, VMIMV and VMINAV instructions
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#as: -march=armv8.1-m.main+mve
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#error_output: mve-vmaxv-vminv-bad.l
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.*: +file format .*arm.*
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57
gas/testsuite/gas/arm/mve-vmaxv-vminv-bad.l
Normal file
57
gas/testsuite/gas/arm/mve-vmaxv-vminv-bad.l
Normal file
@ -0,0 +1,57 @@
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[^:]*: Assembler messages:
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[^:]*:10: Error: bad type in SIMD instruction -- `vmaxv.u64 r0,q1'
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[^:]*:11: Error: bad type in SIMD instruction -- `vmaxv.f16 r0,q1'
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[^:]*:12: Error: bad type in SIMD instruction -- `vminv.s64 r0,q1'
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[^:]*:13: Error: bad type in SIMD instruction -- `vminv.f32 r0,q1'
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[^:]*:14: Error: bad type in SIMD instruction -- `vmaxav.u16 r0,q1'
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[^:]*:15: Error: bad type in SIMD instruction -- `vmaxav.f32 r0,q1'
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[^:]*:16: Error: bad type in SIMD instruction -- `vminav.u32 r0,q1'
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[^:]*:17: Error: bad type in SIMD instruction -- `vminav.f16 r0,q1'
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[^:]*:18: Warning: instruction is UNPREDICTABLE with SP operand
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[^:]*:19: Warning: instruction is UNPREDICTABLE with PC operand
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[^:]*:20: Warning: instruction is UNPREDICTABLE with PC operand
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[^:]*:21: Warning: instruction is UNPREDICTABLE with SP operand
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[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Error: syntax error -- `vmaxveq.s32 r0,q1'
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[^:]*:28: Error: syntax error -- `vmaxveq.s32 r0,q1'
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[^:]*:30: Error: syntax error -- `vmaxveq.s32 r0,q1'
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[^:]*:31: Error: vector predicated instruction should be in VPT/VPST block -- `vmaxvt.s32 r0,q1'
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[^:]*:33: Error: instruction missing MVE vector predication code -- `vmaxv.s32 r0,q1'
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[^:]*:35: Error: syntax error -- `vmaxaveq.s32 r0,q1'
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[^:]*:36: Error: syntax error -- `vmaxaveq.s32 r0,q1'
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[^:]*:38: Error: syntax error -- `vmaxaveq.s32 r0,q1'
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[^:]*:39: Error: vector predicated instruction should be in VPT/VPST block -- `vmaxavt.s32 r0,q1'
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[^:]*:41: Error: instruction missing MVE vector predication code -- `vmaxav.s32 r0,q1'
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[^:]*:43: Error: syntax error -- `vminveq.s32 r0,q1'
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[^:]*:44: Error: syntax error -- `vminveq.s32 r0,q1'
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[^:]*:46: Error: syntax error -- `vminveq.s32 r0,q1'
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[^:]*:47: Error: vector predicated instruction should be in VPT/VPST block -- `vminvt.s32 r0,q1'
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[^:]*:49: Error: instruction missing MVE vector predication code -- `vminv.s32 r0,q1'
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[^:]*:51: Error: syntax error -- `vminaveq.s32 r0,q1'
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[^:]*:52: Error: syntax error -- `vminaveq.s32 r0,q1'
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[^:]*:54: Error: syntax error -- `vminaveq.s32 r0,q1'
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[^:]*:55: Error: vector predicated instruction should be in VPT/VPST block -- `vminavt.s32 r0,q1'
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[^:]*:57: Error: instruction missing MVE vector predication code -- `vminav.s32 r0,q1'
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57
gas/testsuite/gas/arm/mve-vmaxv-vminv-bad.s
Normal file
57
gas/testsuite/gas/arm/mve-vmaxv-vminv-bad.s
Normal file
@ -0,0 +1,57 @@
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.macro cond, op
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.irp cond, eq, ne, gt, ge, lt, le
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it \cond
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\op\().s16 r0, q1
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.endr
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.endm
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.syntax unified
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.thumb
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vmaxv.u64 r0, q1
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vmaxv.f16 r0, q1
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vminv.s64 r0, q1
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vminv.f32 r0, q1
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vmaxav.u16 r0, q1
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vmaxav.f32 r0, q1
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vminav.u32 r0, q1
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vminav.f16 r0, q1
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vmaxv.s32 sp, q1
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vmaxav.s32 pc, q1
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vminv.s32 pc, q1
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vminav.s32 sp, q1
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cond vmaxv
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cond vmaxav
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cond vminv
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cond vminav
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it eq
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vmaxveq.s32 r0, q1
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vmaxveq.s32 r0, q1
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vpst
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vmaxveq.s32 r0, q1
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vmaxvt.s32 r0, q1
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vpst
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vmaxv.s32 r0, q1
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it eq
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vmaxaveq.s32 r0, q1
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vmaxaveq.s32 r0, q1
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vpst
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vmaxaveq.s32 r0, q1
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vmaxavt.s32 r0, q1
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vpst
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vmaxav.s32 r0, q1
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it eq
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vminveq.s32 r0, q1
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vminveq.s32 r0, q1
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vpst
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vminveq.s32 r0, q1
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vminvt.s32 r0, q1
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vpst
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vminv.s32 r0, q1
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it eq
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vminaveq.s32 r0, q1
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vminaveq.s32 r0, q1
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vpst
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vminaveq.s32 r0, q1
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vminavt.s32 r0, q1
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vpst
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vminav.s32 r0, q1
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