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sim: riscv: invert sim_state storage

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This commit is contained in:
Mike Frysinger
2021-05-13 05:44:02 -04:00
parent 2ad10cb222
commit 10c23a2c6f
4 changed files with 22 additions and 12 deletions
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9
sim/riscv/ChangeLog
View File

@ -1,3 +1,12 @@
2021-05-17 Mike Frysinger <vapier@gentoo.org>
* interp.c (sim_open): Call sim_state_alloc_extra.
* sim-main.c (execute_a): Change sd to riscv_sim_state.
* sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Define.
(struct sim_state): Delete.
(struct riscv_sim_state): New struct.
(RISCV_SIM_STATE): Define.
2021-05-16 Mike Frysinger <vapier@gentoo.org>
* interp.c, machs.c, sim-main.c: Replace config.h include with defs.h.

3
sim/riscv/interp.c
View File

@ -59,7 +59,8 @@ sim_open (SIM_OPEN_KIND kind, host_callback *callback,
{
char c;
int i;
SIM_DESC sd = sim_state_alloc (kind, callback);
SIM_DESC sd = sim_state_alloc_extra (kind, callback,
sizeof (struct riscv_sim_state));
/* The cpu data is kept in a separately allocated chunk of memory. */
if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK)

13
sim/riscv/sim-main.c
View File

@ -794,6 +794,7 @@ static sim_cia
execute_a (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
{
SIM_DESC sd = CPU_STATE (cpu);
struct riscv_sim_state *state = RISCV_SIM_STATE (sd);
int rd = (iw >> OP_SH_RD) & OP_MASK_RD;
int rs1 = (iw >> OP_SH_RS1) & OP_MASK_RS1;
int rs2 = (iw >> OP_SH_RS2) & OP_MASK_RS2;
@ -813,7 +814,7 @@ execute_a (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
sim_core_read_unaligned_4 (cpu, cpu->pc, read_map, cpu->regs[rs1]));
/* Walk the reservation list to find an existing match. */
amo_curr = sd->amo_reserved_list;
amo_curr = state->amo_reserved_list;
while (amo_curr)
{
if (amo_curr->addr == cpu->regs[rs1])
@ -824,15 +825,15 @@ execute_a (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
/* No reservation exists, so add one. */
amo_curr = xmalloc (sizeof (*amo_curr));
amo_curr->addr = cpu->regs[rs1];
amo_curr->next = sd->amo_reserved_list;
sd->amo_reserved_list = amo_curr;
amo_curr->next = state->amo_reserved_list;
state->amo_reserved_list = amo_curr;
goto done;
case MATCH_SC_W:
TRACE_INSN (cpu, "%s %s, %s, (%s);", op->name, rd_name, rs2_name,
rs1_name);
/* Walk the reservation list to find a match. */
amo_curr = amo_prev = sd->amo_reserved_list;
amo_curr = amo_prev = state->amo_reserved_list;
while (amo_curr)
{
if (amo_curr->addr == cpu->regs[rs1])
@ -841,8 +842,8 @@ execute_a (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
sim_core_write_unaligned_4 (cpu, cpu->pc, write_map,
cpu->regs[rs1], cpu->regs[rs2]);
store_rd (cpu, rd, 0);
if (amo_curr == sd->amo_reserved_list)
sd->amo_reserved_list = amo_curr->next;
if (amo_curr == state->amo_reserved_list)
state->amo_reserved_list = amo_curr->next;
else
amo_prev->next = amo_curr->next;
free (amo_curr);

9
sim/riscv/sim-main.h
View File

@ -21,6 +21,8 @@
#ifndef SIM_MAIN_H
#define SIM_MAIN_H
#define SIM_HAVE_COMMON_SIM_STATE
#include "sim-basics.h"
#include "machs.h"
#include "sim-base.h"
@ -66,13 +68,10 @@ struct atomic_mem_reserved_list {
address_word addr;
};
struct sim_state {
sim_cpu *cpu[MAX_NR_PROCESSORS];
struct riscv_sim_state {
struct atomic_mem_reserved_list *amo_reserved_list;
/* ... simulator specific members ... */
sim_state_base base;
};
#define RISCV_SIM_STATE(sd) ((struct riscv_sim_state *) STATE_ARCH_DATA (sd))
extern void step_once (SIM_CPU *);
extern void initialize_cpu (SIM_DESC, SIM_CPU *, int);