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Update Zynq, MPSoc Cortex-A53 and MPSoc Cortex-R5 demo projects to build with the 18.1 version of the Xilinx SDK - building BUT NOT YET TESTED.

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This commit is contained in:
Richard Barry
2018-05-02 04:04:54 +00:00
parent a3148ba638
commit 26d8c76996
827 changed files with 236693 additions and 152370 deletions
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1
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/FreeRTOSConfig.h
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@ -117,6 +117,7 @@ to exclude the API function. */
#define INCLUDE_eTaskGetState 1
#define INCLUDE_xTaskAbortDelay 1
#define INCLUDE_xTaskGetHandle 1
#define INCLUDE_xSemaphoreGetMutexHolder 1
/* This demo makes use of one or more example stats formatting functions. These
format the raw data provided by the uxTaskGetSystemState() function in to human

72
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/FreeRTOS_asm_vectors.S
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@ -53,85 +53,21 @@
.org 0
.text
.globl _boot
.globl _vector_table
.globl _freertos_vector_table
.globl FIQInterrupt
.globl IRQInterrupt
.globl SErrorInterrupt
.globl SynchronousInterrupt
.org 0
.section .vectors, "a"
_vector_table:
.set VBAR, _vector_table
.org VBAR
b _boot
.org (VBAR + 0x80)
b .
.org (VBAR + 0x100)
b .
.org (VBAR + 0x180)
b .
.org (VBAR + 0x200)
b .
.org (VBAR + 0x280)
b .
.org (VBAR + 0x300)
b .
.org (VBAR + 0x380)
b .
.org (VBAR + 0x400)
b .
.org (VBAR + 0x480)
b .
.org (VBAR + 0x500)
b .
.org (VBAR + 0x580)
b .
.org (VBAR + 0x600)
b .
.org (VBAR + 0x680)
b .
.org (VBAR + 0x700)
b .
.org (VBAR + 0x780)
b .
/******************************************************************************
* Vector table to use when FreeRTOS is running.
*****************************************************************************/
.set FREERTOS_VBAR, (VBAR+0x1000)
.text
.section .freertos_vectors
.align 8
.set FREERTOS_VBAR, .
.org(FREERTOS_VBAR)
_freertos_vector_table:
b FreeRTOS_SWI_Handler

1
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/lscript.ld
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@ -40,6 +40,7 @@ SECTIONS
{
.text : {
KEEP (*(.vectors))
KEEP (*(.freertos_vectors))
*(.boot)
*(.text)
*(.text.*)

4
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/.cproject
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@ -1,8 +1,8 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
<cconfiguration id="org.eclipse.cdt.core.default.config.1652171495">
<storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.1652171495" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
<cconfiguration id="org.eclipse.cdt.core.default.config.1606552079">
<storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.1606552079" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
<externalSettings/>
<extensions/>
</storageModule>

2
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/.project
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@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>RTOSDemo_A53_bsp</name>
<comment>Created by SDK v2016.4</comment>
<comment>Created by SDK v2018.1</comment>
<projects>
</projects>
<buildSpec>

8
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/Makefile
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@ -16,16 +16,20 @@ include: $(addsuffix /make.include,$(SUBDIRS))
libs: $(addsuffix /make.libs,$(SUBDIRS))
clean: $(addsuffix /make.clean,$(SUBDIRS))
$(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a
cp -f $< $@
%/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,)
@echo "Running Make include in $(subst /make.include,,$@)"
$(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=aarch64-none-elf-gcc" "ARCHIVER=aarch64-none-elf-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g"
$(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=aarch64-none-elf-gcc" "ARCHIVER=aarch64-none-elf-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g -Wall -Wextra"
%/make.libs: include
@echo "Running Make libs in $(subst /make.libs,,$@)"
$(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=aarch64-none-elf-gcc" "ARCHIVER=aarch64-none-elf-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g"
$(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=aarch64-none-elf-gcc" "ARCHIVER=aarch64-none-elf-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g -Wall -Wextra"
%/make.clean:
$(MAKE) -C $(subst /make.clean,,$@) -s clean
clean:
rm -f ${PROCESSOR}/lib/libxil.a

779
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xparameters.h
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File diff suppressed because it is too large Load Diff

40
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/avbuf_v2_1/src/Makefile Normal file
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@ -0,0 +1,40 @@
COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
CC_FLAGS = $(COMPILER_FLAGS)
ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
OUTS = *.o
LIBSOURCES:=*.c
INCLUDEFILES:=*.h
OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
libs: banner avbuf_libs clean
%.o: %.c
${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
banner:
echo "Compiling avbuf"
avbuf_libs: ${OBJECTS}
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
.PHONY: include
include: avbuf_includes
avbuf_includes:
${CP} ${INCLUDEFILES} ${INCLUDEDIR}
clean:
rm -rf ${OBJECTS}

1092
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/avbuf_v2_1/src/xavbuf.c Normal file
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File diff suppressed because it is too large Load Diff

302
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/avbuf_v2_1/src/xavbuf.h Normal file
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@ -0,0 +1,302 @@
/*******************************************************************************
*
* Copyright (C) 2017 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
*******************************************************************************/
/******************************************************************************/
/**
*
* @file xavbuf.h
*
* This file implements all the functions related to the Video Pipeline of the
* DisplayPort Subsystem.
*
* Features supported by this driver
* - Live Video and Graphics input.
* - Non-Live Video Graphics input.
* - Output Formats Supported - RGB, YUV444, YUV4222.
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.0 aad 06/24/17 Initial release.
* 2.0 aad 10/07/17 Added Enums for Video and Audio sources.
* </pre>
*
*******************************************************************************/
#ifndef XAVBUF_H_
/* Prevent circular inclusions by using protection macros. */
#define XAVBUF_H_
/******************************* Include Files ********************************/
#include "xavbuf_hw.h"
#include "sleep.h"
/****************************** Type Definitions ******************************/
/**
* This typedef describes all the Video Formats supported by the driver
*/
typedef enum {
//Non-Live Video Formats
CbY0CrY1,
CrY0CbY1,
Y0CrY1Cb,
Y0CbY1Cr,
YV16,
YV24,
YV16Ci,
MONOCHROME,
YV16Ci2,
YUV444,
RGB888,
RGBA8880,
RGB888_10BPC,
YUV444_10BPC,
YV16Ci2_10BPC,
YV16Ci_10BPC,
YV16_10BPC,
YV24_10BPC,
MONOCHROME_10BPC,
YV16_420,
YV16Ci_420,
YV16Ci2_420,
YV16_420_10BPC,
YV16Ci_420_10BPC,
YV16Ci2_420_10BPC,
// Non-Live Graphics formats
RGBA8888,
ABGR8888,
RGB888_GFX,
BGR888,
RGBA5551,
RGBA4444,
RGB565,
BPP8,
BPP4,
BPP2,
BPP1,
YUV422,
YOnly,
//Live Input/Output Video/Graphics Formats
RGB_6BPC,
RGB_8BPC,
RGB_10BPC,
RGB_12BPC,
YCbCr444_6BPC,
YCbCr444_8BPC,
YCbCr444_10BPC,
YCbCr444_12BPC,
YCbCr422_8BPC,
YCbCr422_10BPC,
YCbCr422_12BPC,
YOnly_8BPC,
YOnly_10BPC,
YOnly_12BPC,
} XAVBuf_VideoFormat;
/**
* This data structure describes video planes.
*/
typedef enum {
Interleaved,
SemiPlanar,
Planar
} XAVBuf_VideoModes;
/**
* This typedef describes the video source list
*/
typedef enum {
XAVBUF_VIDSTREAM1_LIVE,
XAVBUF_VIDSTREAM1_NONLIVE,
XAVBUF_VIDSTREAM1_TPG,
XAVBUF_VIDSTREAM1_NONE,
} XAVBuf_VideoStream;
/**
* This typedef describes the graphics source list
*/
typedef enum {
XAVBUF_VIDSTREAM2_DISABLEGFX = 0x0,
XAVBUF_VIDSTREAM2_NONLIVE_GFX = 0x4,
XAVBUF_VIDSTREAM2_LIVE_GFX = 0x8,
XAVBUF_VIDSTREAM2_NONE = 0xC0,
} XAVBuf_GfxStream;
/**
* This typedef describes the audio stream 1 source list
*/
typedef enum {
XAVBUF_AUDSTREAM1_LIVE = 0x00,
XAVBUF_AUDSTREAM1_NONLIVE = 0x10,
XAVBUF_AUDSTREAM1_TPG = 0x20,
XAVBUF_AUDSTREAM1_NO_AUDIO = 0x30,
} XAVBuf_AudioStream1;
/**
* This typedef describes the audio stream 2 source list
*/
typedef enum {
XAVBUF_AUDSTREAM2_NO_AUDIO = 0X00,
XAVBUF_AUDSTREAM2_AUDIOGFX = 0X40,
} XAVBuf_AudioStream2;
/**
* This typedef describes the attributes associated with the video formats.
*/
typedef struct {
XAVBuf_VideoFormat VideoFormat;
u8 Value;
XAVBuf_VideoModes Mode;
u32 SF[3];
u8 SamplingEn;
u8 IsRGB;
u8 Swap;
u8 BPP;
} XAVBuf_VideoAttribute;
/**
* This typedef stores the attributes of an audio stream
*/
typedef struct {
u32 Volume;
u8 SwapLR;
} XAVBuf_AudioAttribute;
/**
* This typedef stores the data associated with the Audio Video input modes.
*/
typedef struct {
XAVBuf_VideoAttribute *NonLiveVideo, *NonLiveGraphics;
XAVBuf_VideoAttribute *LiveVideo, *LiveGraphics;
XAVBuf_AudioAttribute *Audio, *GraphicsAudio;
XAVBuf_VideoStream VideoSrc;
XAVBuf_GfxStream GraphicsSrc;
XAVBuf_AudioStream1 AudioSrc1;
XAVBuf_AudioStream2 AudioSrc2;
u8 AudioClk, VideoClk;
} XAVBuf_AVModes;
/**
* This structure stores the background color information.
*/
typedef struct {
u16 RCr;
u16 GY;
u16 BCb;
} XAVBuf_BlenderBgClr;
/**
* This typedef stores the AVBuf Configuration information.
*/
typedef struct {
u16 DeviceId;
u32 BaseAddr;
} XAVBuf_Config;
/**
* This typedef stores all the attributes associated to the Blender block of the
* DisplayPort Subsystem
*/
typedef struct {
u8 GlobalAlphaEn;
u8 Alpha;
XAVBuf_VideoAttribute *OutputVideo;
} XAVBuf_Blender;
/**
* The XAVBuf driver instance data. The user is required to allocate a variable
* of this type for every XAVBUF instance in the system. A pointer to this type
* is then passed to the driver API functions
*/
typedef struct {
XAVBuf_Config Config;
XAVBuf_AVModes AVMode;
XAVBuf_Blender Blender;
} XAVBuf;
/**************************** Function Prototypes *****************************/
/* xavbuf.c: Setup and initialization functions. */
void XAVBuf_CfgInitialize(XAVBuf *InstancePtr, u32 BaseAddr, u16 DeviceId);
/* xavbuf.c: Functions to setup the Input Video and Audio sources */
void XAVBuf_InputVideoSelect(XAVBuf *InstancePtr, XAVBuf_VideoStream VidStream,
XAVBuf_GfxStream GfxStream);
void XAVBuf_InputAudioSelect(XAVBuf *InstancePtr, XAVBuf_AudioStream1 AudStream,
XAVBuf_AudioStream2 AudioStream2);
/* xavbuf.c: Functions to setup the Video Format attributes */
int XAVBuf_SetInputNonLiveVideoFormat(XAVBuf *InstancePtr,
XAVBuf_VideoFormat Format);
int XAVBuf_SetInputNonLiveGraphicsFormat(XAVBuf *InstancePtr,
XAVBuf_VideoFormat Format);
int XAVBuf_SetInputLiveVideoFormat(XAVBuf *InstancePtr,
XAVBuf_VideoFormat Format);
int XAVBuf_SetInputLiveGraphicsFormat(XAVBuf *InstancePtr,
XAVBuf_VideoFormat Format);
int XAVBuf_SetOutputVideoFormat(XAVBuf *InstancePtr, XAVBuf_VideoFormat Format);
XAVBuf_VideoAttribute *XAVBuf_GetLiveVideoAttribute(XAVBuf_VideoFormat Format);
XAVBuf_VideoAttribute *XAVBuf_GetNLiveVideoAttribute(XAVBuf_VideoFormat Format);
XAVBuf_VideoAttribute *XAVBuf_GetNLGraphicsAttribute(XAVBuf_VideoFormat Format);
/* xavbuf.c: Functions to setup the clock sources for video and audio */
void XAVBuf_SetAudioVideoClkSrc(XAVBuf *InstancePtr, u8 VideoClk, u8 AudioClk);
/* xavbuf.c: Functions that setup Video and Graphics pipeline depending on the
* sources and format selected.
*/
void XAVBuf_ConfigureVideoPipeline(XAVBuf *InstancePtr);
void XAVBuf_ConfigureGraphicsPipeline(XAVBuf *InstancePtr);
/* Functions to setup Blender Properties */
void XAVBuf_BlendSetBgColor(XAVBuf *InstancePtr, XAVBuf_BlenderBgClr *Color);
void XAVBuf_SetBlenderAlpha(XAVBuf *InstancePtr, u8 Alpha, u8 Enable);
void XAVBuf_SoftReset(XAVBuf *InstancePtr);
void XABuf_LineResetDisable(XAVBuf *InstancePtr, u8 Disable);
void XAVBuf_ConfigureOutputVideo(XAVBuf *InstancePtr);
/* Audio Configuration functions */
void XAVBuf_AudioSoftReset(XAVBuf *InstancePtr);
void XAVBuf_AudioMixerVolumeControl(XAVBuf *InstancePtr, u8 Channel0Volume,
u8 Channel1Volume);
/* DPDMA Interface functions */
void XAVBuf_EnableGraphicsBuffers(XAVBuf *InstancePtr, u8 Enable);
void XAVBuf_EnableVideoBuffers(XAVBuf *InstancePtr, u8 Enable);
void XAVBuf_EnableAudio0Buffers(XAVBuf *InstancePtr, u8 Enable);
void XAVBuf_EnableAudio1Buffers(XAVBuf *InstancePtr, u8 Enable);
#endif //XAVBUF_H_

561
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/avbuf_v2_1/src/xavbuf_clk.c Normal file
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@ -0,0 +1,561 @@
/******************************************************************************
*
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************/
/**
*
* @file xavbuf.c
*
* This header file contains PLL configuring functions. These Functions
* calculates and configures the PLL depending on desired frequency.
*
* @note None.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.0 mh 06/24/17 Initial release.
* 2.1 tu 12/29/17 LPD and FPD offsets adjusted
* </pre>
*
*******************************************************************************/
/******************************* Include Files ********************************/
#include "xavbuf_clk.h"
/**************************** Constant Definitions ****************************/
/*Input Frequency for the PLL with precision upto two decimals*/
#define XAVBUF_INPUT_REF_CLK 3333333333
/*Frequency of VCO before divider to meet jitter requirement*/
#define XAVBUF_PLL_OUT_FREQ 1450000000
/* Precision of Input Ref Frequency for PLL*/
#define XAVBUF_INPUT_FREQ_PRECISION 100
/* 16 bit fractional shift to get Integer */
#define XAVBUF_PRECISION 16
#define XAVBUF_SHIFT_DECIMAL (1 << XAVBUF_PRECISION)
#define XAVBUF_DECIMAL (XAVBUF_SHIFT_DECIMAL - 1)
#define XDPSSU_MAX_VIDEO_FREQ 300000000
#define XAVBUF_AUDIO_SAMPLES 512
#define XAVBUF_AUDIO_SAMPLE_RATE_44_1 44100
#define XAVBUF_AUDIO_SAMPLE_RATE_48_0 48000
#define XAVBUF_EXTERNAL_DIVIDER 2
/* Register offsets for address manipulation */
#define XAVBUF_REG_OFFSET 4
#define XAVBUF_FPD_CTRL_OFFSET 12
#define XAVBUF_LPD_CTRL_OFFSET 16
#define MOD_3(a) ((a) % (3))
/*************************** Constant Variable Definitions ********************/
/**
* This typedef enumerates capacitor resistor and lock values to be programmed.
*/
typedef struct{
u16 cp;
u16 res;
u16 lfhf;
u16 lock_dly;
u16 lock_cnt;
}PllConfig;
/* PLL fractional divide programming table*/
static const PllConfig PllFracDivideTable[] = {
{3, 5, 3, 63, 1000},
{3, 5, 3, 63, 1000},
{3, 9, 3, 63, 1000},
{3, 9, 3, 63, 1000},
{3, 9, 3, 63, 1000},
{3, 9, 3, 63, 1000},
{3, 14, 3, 63, 1000},
{3, 14, 3, 63, 1000},
{3, 14, 3, 63, 1000},
{3, 14, 3, 63, 1000},
{3, 14, 3, 63, 1000},
{3, 14, 3, 63, 1000},
{3, 14, 3, 63, 1000},
{3, 14, 3, 63, 975},
{3, 14, 3, 63, 950},
{3, 14, 3, 63, 925},
{3, 1, 3, 63, 900},
{3, 1, 3, 63, 875},
{3, 1, 3, 63, 850},
{3, 1, 3, 63, 850},
{3, 1, 3, 63, 825},
{3, 1, 3, 63, 800},
{3, 1, 3, 63, 775},
{3, 6, 3, 63, 775},
{3, 6, 3, 63, 750},
{3, 6, 3, 63, 725},
{3, 6, 3, 63, 700},
{3, 6, 3, 63, 700},
{3, 6, 3, 63, 675},
{3, 6, 3, 63, 675},
{3, 6, 3, 63, 650},
{3, 6, 3, 63, 650},
{3, 6, 3, 63, 625},
{3, 6, 3, 63, 625},
{3, 6, 3, 63, 625},
{3, 6, 3, 63, 600},
{3, 6, 3, 63, 600},
{3, 6, 3, 63, 600},
{3, 6, 3, 63, 600},
{3, 6, 3, 63, 600},
{3, 10, 3, 63, 600},
{3, 10, 3, 63, 600},
{3, 10, 3, 63, 600},
{3, 10, 3, 63, 600},
{3, 10, 3, 63, 600},
{3, 10, 3, 63, 600},
{3, 10, 3, 63, 600},
{3, 10, 3, 63, 600},
{3, 10, 3, 63, 600},
{3, 10, 3, 63, 600},
{3, 10, 3, 63, 600},
{3, 10, 3, 63, 600},
{3, 10, 3, 63, 600},
{3, 10, 3, 63, 600},
{3, 10, 3, 63, 600},
{3, 10, 3, 63, 600},
{4, 6, 3, 63, 600},
{4, 6, 3, 63, 600},
{4, 6, 3, 63, 600},
{4, 6, 3, 63, 600},
{4, 6, 3, 63, 600},
{4, 6, 3, 63, 600},
{3, 12, 3, 63, 600},
{3, 12, 3, 63, 600},
{3, 12, 3, 63, 600},
{3, 12, 3, 63, 600},
{3, 12, 3, 63, 600},
{3, 12, 3, 63, 600},
{3, 12, 3, 63, 600},
{3, 12, 3, 63, 600},
{3, 12, 3, 63, 600},
{3, 12, 3, 63, 600},
{3, 12, 3, 63, 600},
{3, 12, 3, 63, 600},
{3, 12, 3, 63, 600},
{3, 12, 3, 63, 600},
{3, 12, 3, 63, 600},
{3, 12, 3, 63, 600},
{3, 12, 3, 63, 600},
{3, 12, 3, 63, 600},
{3, 12, 3, 63, 600},
{3, 12, 3, 63, 600},
{3, 12, 3, 63, 600},
{3, 12, 3, 63, 600},
{3, 12, 3, 63, 600},
{3, 12, 3, 63, 600},
{3, 12, 3, 63, 600},
{3, 12, 3, 63, 600},
{3, 12, 3, 63, 600},
{3, 12, 3, 63, 600},
{3, 12, 3, 63, 600},
{3, 12, 3, 63, 600},
{3, 12, 3, 63, 600},
{3, 12, 3, 63, 600},
{3, 12, 3, 63, 600},
{3, 12, 3, 63, 600},
{3, 12, 3, 63, 600},
{3, 12, 3, 63, 600},
{3, 12, 3, 63, 600},
{3, 12, 3, 63, 600}
};
/******************************************************************************/
/**
* This function initializes the parameters required to configure PLL.
*
* @param PllInstancePtr is pointer to the XAVBuf_Pll instance.
* @param Pll is the PLL chosen to be configured.
* @param Pll is the PLL chosen to be configured.
* @param CrossDomain is the bool which is used to mention if the PLL
* outputs in other domain.
* @param ExtDividerCnt is number of external divider out of VCO.
*
* @return XST_SUCCESS if PLL is configured without an error.
* XST_FAILURE otherwise.
*
* @note In order to avoid floating point usage we have a 16bit
* fractional fixed point arithmetic implementation
*
*******************************************************************************/
static void XAVBuf_PllInitialize(XAVBuf_Pll *PllInstancePtr,
u8 Pll, u8 CrossDomain , u8 ExtDividerCnt)
{
/* Instantiate input frequency. */
PllInstancePtr->InputRefClk = XAVBUF_Pss_Ref_Clk;
PllInstancePtr->RefClkFreqhz = XAVBUF_INPUT_REF_CLK;
/* Turn on internal Divider*/
PllInstancePtr->Divider = 1;
PllInstancePtr->Pll = Pll;
PllInstancePtr->ExtDividerCnt = ExtDividerCnt;
//Check if CrossDomain is requested
if(CrossDomain)
PllInstancePtr->DomainSwitchDiv = 6;
else
PllInstancePtr->DomainSwitchDiv = 1;
//Check where PLL falls
if (Pll>2){
PllInstancePtr->Fpd = 0;
PllInstancePtr->BaseAddress = XAVBUF_CLK_LPD_BASEADDR;
PllInstancePtr->Offset = XAVBUF_LPD_CTRL_OFFSET;
}
else{
PllInstancePtr->Fpd = 1;
PllInstancePtr->BaseAddress = XAVBUF_CLK_FPD_BASEADDR;
PllInstancePtr->Offset = XAVBUF_FPD_CTRL_OFFSET;
}
}
/******************************************************************************/
/**
* This function calculates the parameters which are required to configure PLL
* depending upon the requested frequency.
*
* @param PllInstancePtr is pointer to the XAVBuf_Pll instance
* @param FreqHz is the requested frequency to DP in Hz
*
* @return XST_SUCCESS if parameters are calculated
* XST_FAILURE otherwise.
*
* @note In order to avoid floating point usage we have a 16bit
* fractional fixed point arithmetic implementation
*
*******************************************************************************/
static int XAVBuf_PllCalcParameterValues(XAVBuf_Pll *PllInstancePtr,
u64 FreqHz)
{
u64 ExtDivider, Vco, VcoIntFrac;
/* Instantiate input frequency. */
PllInstancePtr->InputRefClk = XAVBUF_Pss_Ref_Clk;
PllInstancePtr->RefClkFreqhz = XAVBUF_INPUT_REF_CLK ;
/* Turn on internal Divider*/
PllInstancePtr->Divider = 1;
PllInstancePtr->DomainSwitchDiv = 1;
/* Estimate the total divider. */
ExtDivider = (XAVBUF_PLL_OUT_FREQ / FreqHz) /
PllInstancePtr->DomainSwitchDiv;
if(ExtDivider > 63 && PllInstancePtr->ExtDividerCnt == 2){
PllInstancePtr->ExtDivider0 = 63;
PllInstancePtr->ExtDivider1 = ExtDivider / 63;
}
else if(ExtDivider < 63){
PllInstancePtr->ExtDivider0 = ExtDivider;
PllInstancePtr->ExtDivider1 = 1;
}
else
return XST_FAILURE;
Vco = FreqHz *(PllInstancePtr->ExtDivider1 *
PllInstancePtr->ExtDivider0 * 2) *
PllInstancePtr->DomainSwitchDiv;
/* Calculate integer and fractional part. */
VcoIntFrac = (Vco * XAVBUF_INPUT_FREQ_PRECISION *
XAVBUF_SHIFT_DECIMAL) /
PllInstancePtr->RefClkFreqhz ;
PllInstancePtr->Fractional = VcoIntFrac & XAVBUF_DECIMAL;
PllInstancePtr->FracIntegerFBDIV = VcoIntFrac >> XAVBUF_PRECISION;
return XST_SUCCESS;
}
/******************************************************************************/
/**
* This function will Read modify and write into corresponding registers.
*
* @param BaseAddress is the base address to which the value has to be
* written.
* @param RegOffset is the relative offset from Base address.
* @param Mask is used to select the number of bits to be modified.
* @param Shift is the number bits to be shifted from LSB.
* @param Data is the Data to be written.
*
* @return None.
*
* @note None.
*
*******************************************************************************/
static void XAVBuf_ReadModifyWriteReg(u32 BaseAddress, u32 RegOffset, u32 Mask,
u32 Shift, u32 Data)
{
u32 RegValue;
RegValue = XAVBuf_ReadReg(BaseAddress, RegOffset);
RegValue = (RegValue & ~Mask) | (Data << Shift);
XAVBuf_WriteReg(BaseAddress, RegOffset, RegValue);
}
/******************************************************************************/
/**
* This function configures PLL.
*
* @param PllInstancePtr is pointer to the XAVBuf_Pll instance.
*
* @return XST_SUCCESS if PLL is configured without an error.
* XST_FAILURE otherwise.
*
* @note None.
*
*******************************************************************************/
static int XAVBuf_ConfigurePll(XAVBuf_Pll *PllInstancePtr)
{
u64 BaseAddress = PllInstancePtr->BaseAddress;
u64 timer = 0;
u32 RegPll = 0;
u8 Pll = PllInstancePtr->Pll;
RegPll |= XAVBUF_ENABLE_BIT << XAVBUF_PLL_CTRL_BYPASS_SHIFT;
RegPll |= PllInstancePtr->FracIntegerFBDIV <<
XAVBUF_PLL_CTRL_FBDIV_SHIFT;
RegPll |= PllInstancePtr->Divider << XAVBUF_PLL_CTRL_DIV2_SHIFT;
RegPll |= PllInstancePtr->InputRefClk << XAVBUF_PLL_CTRL_PRE_SRC_SHIFT;
XAVBuf_WriteReg(BaseAddress, XAVBUF_PLL_CTRL + (MOD_3(Pll) *
PllInstancePtr->Offset), RegPll);
RegPll = 0;
/* Set the values for lock dly, lock counter, capacitor and resistor. */
RegPll |=
PllFracDivideTable[PllInstancePtr->FracIntegerFBDIV -25].cp
<< XAVBUF_PLL_CFG_CP_SHIFT;
RegPll |=
PllFracDivideTable[PllInstancePtr->FracIntegerFBDIV -25].res
<< XAVBUF_PLL_CFG_RES_SHIFT;
RegPll |=
PllFracDivideTable[PllInstancePtr->FracIntegerFBDIV -25].lfhf
<< XAVBUF_PLL_CFG_LFHF_SHIFT;
RegPll |=
PllFracDivideTable[PllInstancePtr->FracIntegerFBDIV -25].lock_dly
<< XAVBUF_PLL_CFG_LOCK_DLY_SHIFT;
RegPll |=
PllFracDivideTable[PllInstancePtr->FracIntegerFBDIV -25].lock_cnt
<< XAVBUF_PLL_CFG_LOCK_CNT_SHIFT;
XAVBuf_WriteReg(BaseAddress, XAVBUF_PLL_CFG + (MOD_3(Pll) *
PllInstancePtr->Offset), RegPll);
/* Enable and set Fractional Data. */
XAVBuf_WriteReg(BaseAddress, XAVBUF_PLL_FRAC_CFG + (MOD_3(Pll) *
PllInstancePtr->Offset), (1 << XAVBUF_PLL_FRAC_CFG_ENABLED_SHIFT) |
(PllInstancePtr->Fractional <<
XAVBUF_PLL_FRAC_CFG_DATA_SHIFT));
/* Assert reset to the PLL. */
XAVBuf_ReadModifyWriteReg(BaseAddress, XAVBUF_PLL_CTRL + (MOD_3(Pll) *
PllInstancePtr->Offset),
XAVBUF_PLL_CTRL_RESET_MASK, XAVBUF_PLL_CTRL_RESET_SHIFT,
XAVBUF_ENABLE_BIT);
/* Deassert reset to the PLL. */
XAVBuf_ReadModifyWriteReg(BaseAddress, XAVBUF_PLL_CTRL + (MOD_3(Pll) *
PllInstancePtr->Offset),
XAVBUF_PLL_CTRL_RESET_MASK, XAVBUF_PLL_CTRL_RESET_SHIFT,
XAVBUF_DISABLE_BIT);
while(!(XAVBuf_ReadReg(BaseAddress, XAVBUF_PLL_STATUS -
((1 - PllInstancePtr->Fpd) * XAVBUF_REG_OFFSET)) &
(1 << MOD_3(Pll))))
if(++timer > 1000)
return XST_FAILURE;
/* Deassert Bypass. */
XAVBuf_ReadModifyWriteReg(BaseAddress, XAVBUF_PLL_CTRL + (MOD_3(Pll) *
PllInstancePtr->Offset),
XAVBUF_PLL_CTRL_BYPASS_MASK, XAVBUF_PLL_CTRL_BYPASS_SHIFT,
XAVBUF_DISABLE_BIT);
if(PllInstancePtr->DomainSwitchDiv != 1)
XAVBuf_ReadModifyWriteReg(BaseAddress, (XAVBUF_DOMAIN_SWITCH_CTRL
+ (MOD_3(Pll) * XAVBUF_REG_OFFSET) - ((1 - PllInstancePtr->Fpd)
* XAVBUF_REG_OFFSET)),
XAVBUF_DOMAIN_SWITCH_DIVISOR0_MASK,
XAVBUF_DOMAIN_SWITCH_DIVISOR0_SHIFT,
PllInstancePtr->DomainSwitchDiv);
usleep(1);
return XST_SUCCESS;
}
/******************************************************************************/
/**
* This function configures Configures external divider.
*
* @param PllInstancePtr is pointer to the XAVBuf_Pll instance.
*
* @return None.
*
* @note None.
*
*******************************************************************************/
static void XAVBuf_ConfigureExtDivider(XAVBuf_Pll *PllInstancePtr,
u64 BaseAddress, u32 Offset)
{
XAVBuf_ReadModifyWriteReg(BaseAddress, Offset,
XAVBUF_VIDEO_REF_CTRL_CLKACT_MASK,
XAVBUF_VIDEO_REF_CTRL_CLKACT_SHIFT, XAVBUF_DISABLE_BIT);
XAVBuf_ReadModifyWriteReg(BaseAddress, Offset,
XAVBUF_VIDEO_REF_CTRL_DIVISOR1_MASK,
XAVBUF_VIDEO_REF_CTRL_DIVISOR1_SHIFT,
PllInstancePtr->ExtDivider1);
XAVBuf_ReadModifyWriteReg(BaseAddress, Offset,
XAVBUF_VIDEO_REF_CTRL_DIVISOR0_MASK,
XAVBUF_VIDEO_REF_CTRL_DIVISOR0_SHIFT,
PllInstancePtr->ExtDivider0);
XAVBuf_ReadModifyWriteReg(BaseAddress, Offset,
XAVBUF_VIDEO_REF_CTRL_CLKACT_MASK,
XAVBUF_VIDEO_REF_CTRL_CLKACT_SHIFT, XAVBUF_ENABLE_BIT);
XAVBuf_WriteReg(BaseAddress, Offset, 0x1011003);
}
/******************************************************************************/
/**
* This function calls API to calculate and configure PLL with desired frequency
* for Video.
*
* @param FreqHz is the desired frequency in Hz.
*
* @return XST_SUCCESS if PLL is configured without an error.
* XST_FAILURE otherwise.
*
* @note The Pll used is design specific.
*
*******************************************************************************/
int XAVBuf_SetPixelClock(u64 FreqHz)
{
u32 PllAssigned;
XAVBuf_Pll PllInstancePtr;
u8 Pll, CrossDomain, Flag;
/*Verify Input Arguments*/
Xil_AssertNonvoid(FreqHz < XDPSSU_MAX_VIDEO_FREQ);
PllAssigned = XAVBuf_ReadReg(XAVBUF_CLK_FPD_BASEADDR,
XAVBUF_VIDEO_REF_CTRL) & XAVBUF_VIDEO_REF_CTRL_SRCSEL_MASK;
switch (PllAssigned) {
case XAVBUF_VPLL_SRC_SEL:
Pll = VPLL;
CrossDomain = 0;
break;
case XAVBUF_DPLL_SRC_SEL:
Pll = DPLL;
CrossDomain = 0;
break;
case XAVBUF_RPLL_TO_FPD_SRC_SEL:
Pll = RPLL;
CrossDomain = 1;
break;
default:
return XST_FAILURE;
}
/*Calculate configure PLL and External Divider*/
XAVBuf_PllInitialize(&PllInstancePtr, Pll, CrossDomain,
XAVBUF_EXTERNAL_DIVIDER);
Flag = XAVBuf_PllCalcParameterValues(&PllInstancePtr, FreqHz);
if(Flag != 0)
return XST_FAILURE;
Flag = XAVBuf_ConfigurePll(&PllInstancePtr);
if(Flag != 0)
return XST_FAILURE;
XAVBuf_ConfigureExtDivider(&PllInstancePtr, XAVBUF_CLK_FPD_BASEADDR,
XAVBUF_VIDEO_REF_CTRL);
return XST_SUCCESS;
}
/******************************************************************************/
/**
* This function calls API to calculate and configure PLL with desired
* frequency for Audio.
*
* @param FreqHz is the desired frequency in Hz.
*
* @return XST_SUCCESS if PLL is configured without an error.
* XST_FAILURE otherwise.
*
* @note The Pll used is design specific.
*
*******************************************************************************/
int XAVBuf_SetAudioClock(u64 FreqHz)
{
u32 Flag, PllAssigned;
u8 Pll, CrossDomain;
XAVBuf_Pll XAVBuf_RPllInstancePtr;
/*Verify Input Arguments*/
Flag = (FreqHz == (XAVBUF_AUDIO_SAMPLE_RATE_44_1 *
XAVBUF_AUDIO_SAMPLES)) ||
(FreqHz == (XAVBUF_AUDIO_SAMPLE_RATE_48_0 *
XAVBUF_AUDIO_SAMPLES));
Xil_AssertNonvoid(Flag);
PllAssigned = XAVBuf_ReadReg(XAVBUF_CLK_FPD_BASEADDR,
XAVBUF_AUDIO_REF_CTRL) &
XAVBUF_AUDIO_REF_CTRL_SRCSEL_MASK;
switch (PllAssigned) {
case XAVBUF_VPLL_SRC_SEL:
Pll = VPLL;
CrossDomain = 0;
break;
case XAVBUF_DPLL_SRC_SEL:
Pll = DPLL;
CrossDomain = 0;
break;
case XAVBUF_RPLL_TO_FPD_SRC_SEL:
Pll = RPLL;
CrossDomain = 1;
break;
default:
return XST_FAILURE;
}
/*Calculate configure PLL and External Divider*/
XAVBuf_PllInitialize(&XAVBuf_RPllInstancePtr, Pll, CrossDomain,
XAVBUF_EXTERNAL_DIVIDER);
Flag = XAVBuf_PllCalcParameterValues(&XAVBuf_RPllInstancePtr, FreqHz);
if(Flag != 0)
return XST_FAILURE;
Flag = XAVBuf_ConfigurePll(&XAVBuf_RPllInstancePtr);
if(Flag != 0)
return XST_FAILURE;
XAVBuf_ConfigureExtDivider(&XAVBuf_RPllInstancePtr,
XAVBUF_CLK_FPD_BASEADDR, XAVBUF_AUDIO_REF_CTRL);
return XST_SUCCESS;
}

97
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/avbuf_v2_1/src/xavbuf_clk.h Normal file
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@ -0,0 +1,97 @@
/******************************************************************************
*
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************/
/**
*
* @file xavbuf_clk.h
*
* This header file contains the identifiers and low-level driver functions (or
* macros) that can be used to configure PLL to generate required frequency.
*
* @note None.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.0 mh 06/24/17 Initial release.
* 2.1 tu 12/29/17 LPD and FPD offsets adjusted
* </pre>
*
*******************************************************************************/
#ifndef XAVBUF_CLK_H_
#define XAVBUF_CLK_H_
/******************************* Include Files ********************************/
#include "xavbuf_hw.h"
#include "xstatus.h"
#include "sleep.h"
/****************************** Type Definitions ******************************/
/**
* This enum enumerates various PLL
*/
enum PLL{
APLL = 0,
DPLL = 1,
VPLL = 2,
IOPLL = 3,
RPLL = 4
};
/**
* This typedef enumerates various variables used to configure Pll
*/
typedef struct {
u64 BaseAddress;
u64 Fractional;
u64 RefClkFreqhz;
u32 Divider;
u8 Offset;
u8 ClkDividBy2;
u8 ExtDivider0;
u8 ExtDivider1;
u8 ExtDividerCnt;
u8 DomainSwitchDiv;
u8 FracIntegerFBDIV;
u8 IntegerFBDIV;
u8 InputRefClk;
u8 Fpd;
u8 Pll;
}XAVBuf_Pll;
/**************************** Function Prototypes *****************************/
int XAVBuf_SetPixelClock(u64 FreqHz);
int XAVBuf_SetAudioClock(u64 FreqHz);
#endif /* XAVBUF_CLK_H_ */

10
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_3/src/xemacps_g.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/avbuf_v2_1/src/xavbuf_g.c
View File

@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
@ -38,17 +38,17 @@
*******************************************************************/
#include "xparameters.h"
#include "xemacps.h"
#include "xavbuf.h"
/*
* The configuration table for devices
*/
XEmacPs_Config XEmacPs_ConfigTable[] =
XAVBuf_Config XAVBuf_ConfigTable[XPAR_XAVBUF_NUM_INSTANCES] =
{
{
XPAR_PSU_ETHERNET_3_DEVICE_ID,
XPAR_PSU_ETHERNET_3_BASEADDR
XPAR_PSU_DP_DEVICE_ID,
XPAR_PSU_DP_BASEADDR
}
};

1675
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227
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/avbuf_v2_1/src/xavbuf_videoformats.c Normal file
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@ -0,0 +1,227 @@
/*******************************************************************************
*
* Copyright (C) 2017 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
*******************************************************************************/
/******************************************************************************/
/**
*
* @file xavbuf_videoformats.c
* @addtogroup xavbuf_v2_1
* @{
*
* Contains attributes of the video formats mapped to the hardware
*
* @note None.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.0 aad 03/10/17 Initial release.
* 2.0 aad 02/22/18 Fixed scaling factors and bits per pixel
* </pre>
*
*******************************************************************************/
/******************************* Include Files ********************************/
#include "xavbuf.h"
/**************************** Variable Definitions ****************************/
#ifdef __cplusplus
extern "C"
#endif
const XAVBuf_VideoAttribute XAVBuf_SupportedFormats[XAVBUF_NUM_SUPPORTED] =
{
/* Non - Live Video Formats */
{ CbY0CrY1, 0, Interleaved,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
TRUE, FALSE, FALSE, 16},
{ CrY0CbY1, 1, Interleaved,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
TRUE, FALSE, FALSE, 16},
{ Y0CrY1Cb, 2, Interleaved,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
TRUE, FALSE, FALSE, 16},
{ Y0CbY1Cr, 3, Interleaved,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
TRUE, FALSE, FALSE, 16},
{ YV16, 4, Planar,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
TRUE, FALSE, FALSE, 16},
{ YV24, 5, Planar,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
FALSE, FALSE, FALSE, 24},
{ YV16Ci, 6, SemiPlanar,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
TRUE, FALSE, FALSE, 16},
{ MONOCHROME, 7, Interleaved,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
TRUE, FALSE, FALSE, 8},
{ YV16Ci2, 8, SemiPlanar,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
TRUE, FALSE, TRUE, 16},
{ YUV444, 9, Interleaved,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
FALSE, FALSE, FALSE, 24},
{ RGB888, 10, Interleaved,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
FALSE, TRUE, FALSE, 24},
{ RGBA8880, 11, Interleaved,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
FALSE, TRUE, FALSE, 32},
{ RGB888_10BPC, 12, Interleaved,
{XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF},
FALSE, TRUE, FALSE, 30},
{ YUV444_10BPC, 13, Interleaved,
{XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF},
FALSE, FALSE, FALSE, 30},
{ YV16Ci2_10BPC, 14, SemiPlanar,
{XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF},
TRUE, FALSE, TRUE, 20},
{ YV16Ci_10BPC, 15, SemiPlanar,
{XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF},
TRUE, FALSE, FALSE, 20},
{ YV16_10BPC, 16, Planar,
{XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF},
TRUE, FALSE, FALSE, 20},
{ YV24_10BPC, 17, Planar,
{XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF},
FALSE, FALSE, FALSE, 30},
{ MONOCHROME_10BPC, 18, Interleaved,
{XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF},
TRUE, FALSE, FALSE, 10},
{ YV16_420, 19, Planar,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
TRUE, FALSE, FALSE, 16},
{ YV16Ci_420, 20, SemiPlanar,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
TRUE, FALSE, FALSE, 16},
{ YV16Ci2_420, 21, SemiPlanar,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
TRUE, FALSE, TRUE, 16},
{ YV16_420_10BPC, 22, Planar,
{XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF},
TRUE, FALSE, FALSE, 20},
{ YV16Ci_420_10BPC, 23, SemiPlanar,
{XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF},
TRUE, FALSE, FALSE, 20},
{ YV16Ci2_420_10BPC, 24, SemiPlanar,
{XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF},
TRUE, FALSE, TRUE, 20},
/* Non-Live Graphics formats */
{ RGBA8888, 0, Interleaved,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
FALSE, TRUE, FALSE, 32},
{ ABGR8888, 1, Interleaved,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
FALSE, TRUE, FALSE, 32},
{ RGB888_GFX, 2, Interleaved,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
FALSE, TRUE, FALSE, 24},
{ BGR888, 3, Interleaved,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
FALSE, TRUE, FALSE, 24},
{ RGBA5551, 4, Interleaved,
{XAVBUF_BUF_5BIT_SF, XAVBUF_BUF_5BIT_SF, XAVBUF_BUF_5BIT_SF},
FALSE, TRUE, FALSE, 16},
{ RGBA4444, 5, Interleaved,
{XAVBUF_BUF_4BIT_SF, XAVBUF_BUF_4BIT_SF, XAVBUF_BUF_4BIT_SF},
FALSE, TRUE, FALSE, 16},
{ RGB565, 6, Interleaved,
{XAVBUF_BUF_5BIT_SF, XAVBUF_BUF_6BIT_SF, XAVBUF_BUF_5BIT_SF},
FALSE, TRUE, FALSE, 16},
{ BPP8, 7, Interleaved,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
FALSE, TRUE, FALSE, 8},
{ BPP4, 8, Interleaved,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
FALSE, TRUE, FALSE, 4},
{ BPP2, 9, Interleaved,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
FALSE, TRUE, FALSE, 2},
{ BPP1, 10, Interleaved,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
FALSE, TRUE, FALSE, 1},
{ YUV422, 11, Interleaved,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
FALSE, FALSE, FALSE, 24},
/* Video Formats for Live Video/Graphics input and output sources */
{ RGB_6BPC, 0, Interleaved,
{XAVBUF_BUF_6BIT_SF, XAVBUF_BUF_6BIT_SF, XAVBUF_BUF_6BIT_SF},
FALSE, TRUE, FALSE, 18},
{ RGB_8BPC, 0, Interleaved,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
FALSE, TRUE, FALSE, 24},
{ RGB_10BPC, 0, Interleaved,
{XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF},
FALSE, TRUE, FALSE, 30},
{ RGB_12BPC, 0, Interleaved,
{XAVBUF_BUF_12BIT_SF, XAVBUF_BUF_12BIT_SF, XAVBUF_BUF_12BIT_SF},
FALSE, TRUE, FALSE, 36},
{ YCbCr444_6BPC, 1, Interleaved,
{XAVBUF_BUF_6BIT_SF, XAVBUF_BUF_6BIT_SF, XAVBUF_BUF_6BIT_SF},
FALSE, FALSE, FALSE, 18},
{ YCbCr444_8BPC, 1, Interleaved,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
FALSE, FALSE, FALSE, 24},
{ YCbCr444_10BPC, 1, Interleaved,
{XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF},
FALSE, FALSE, FALSE, 30},
{ YCbCr444_12BPC, 1, Interleaved,
{XAVBUF_BUF_12BIT_SF, XAVBUF_BUF_12BIT_SF, XAVBUF_BUF_12BIT_SF},
FALSE, FALSE, FALSE, 36},
{ YCbCr422_8BPC, 2, Interleaved,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
TRUE, FALSE, FALSE, 24},
{ YCbCr422_10BPC, 2, Interleaved,
{XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF},
TRUE, FALSE, FALSE, 30},
{ YCbCr422_12BPC, 2, Interleaved,
{XAVBUF_BUF_12BIT_SF, XAVBUF_BUF_12BIT_SF, XAVBUF_BUF_12BIT_SF},
TRUE, FALSE, FALSE, 36},
{ YOnly_8BPC, 3, Interleaved,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
TRUE, FALSE, FALSE, 24},
{ YOnly_10BPC, 3, Interleaved,
{XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF},
TRUE, FALSE, FALSE, 30},
{ YOnly_12BPC, 3, Interleaved,
{XAVBUF_BUF_12BIT_SF, XAVBUF_BUF_12BIT_SF, XAVBUF_BUF_12BIT_SF},
TRUE, FALSE, FALSE, 36},
};
/** @} */

27
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_5/src/Makefile
View File

@ -1,27 +0,0 @@
COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
INCLUDEFILES=*.h
LIBSOURCES=*.c
OUTS = *.o
libs:
echo "Compiling axipmon"
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
make clean
include:
${CP} ${INCLUDEFILES} ${INCLUDEDIR}
clean:
rm -rf ${OUTS}

40
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_6/src/Makefile Normal file
View File

@ -0,0 +1,40 @@
COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
CC_FLAGS = $(COMPILER_FLAGS)
ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
OUTS = *.o
LIBSOURCES:=*.c
INCLUDEFILES:=*.h
OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
libs: banner xaxipmon_libs clean
%.o: %.c
${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
banner:
echo "Compiling axipmon"
xaxipmon_libs: ${OBJECTS}
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
.PHONY: include
include: xaxipmon_includes
xaxipmon_includes:
${CP} ${INCLUDEFILES} ${INCLUDEDIR}
clean:
rm -rf ${OBJECTS}

2
FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_6/src/xaxipmon.c
View File

@ -33,7 +33,7 @@
/**
*
* @file xaxipmon.c
* @addtogroup axipmon_v6_3
* @addtogroup axipmon_v6_6
* @{
*
* This file contains the driver API functions that can be used to access

10
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_5/src/xaxipmon.h → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_6/src/xaxipmon.h
View File

@ -33,7 +33,7 @@
/**
*
* @file xaxipmon.h
* @addtogroup axipmon_v6_3
* @addtogroup axipmon_v6_6
* @{
* @details
*
@ -253,6 +253,14 @@
* 6.3 kvn 07/02/15 Modified code according to MISRA-C:2012 guidelines.
* 6.4 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
* Changed the prototype of XAxiPmon_CfgInitialize API.
* 6.5 ms 01/23/17 Modified xil_printf statement in main function for all
* examples to ensure that "Successfully ran" and "Failed"
* strings are available in all examples. This is a fix
* for CR-965028.
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
* 6.6 ms 04/18/17 Modified tcl file to add suffix U for all macro
* definitions of axipmon in xparameters.h
* </pre>
*
*****************************************************************************/

4
FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_g.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_6/src/xaxipmon_g.c
View File

@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
@ -44,7 +44,7 @@
* The configuration table for devices
*/
XAxiPmon_Config XAxiPmon_ConfigTable[] =
XAxiPmon_Config XAxiPmon_ConfigTable[XPAR_XAXIPMON_NUM_INSTANCES] =
{
{
XPAR_PSU_APM_0_DEVICE_ID,

2
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_5/src/xaxipmon_hw.h → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_6/src/xaxipmon_hw.h
View File

@ -33,7 +33,7 @@
/**
*
* @file xaxipmon_hw.h
* @addtogroup axipmon_v6_3
* @addtogroup axipmon_v6_6
* @{
*
* This header file contains identifiers and basic driver functions (or

2
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_5/src/xaxipmon_selftest.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_6/src/xaxipmon_selftest.c
View File

@ -33,7 +33,7 @@
/**
*
* @file xaxipmon_selftest.c
* @addtogroup axipmon_v6_3
* @addtogroup axipmon_v6_6
* @{
*
* This file contains a diagnostic self test function for the XAxiPmon driver.

2
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_5/src/xaxipmon_sinit.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_6/src/xaxipmon_sinit.c
View File

@ -33,7 +33,7 @@
/**
*
* @file xaxipmon_sinit.c
* @addtogroup axipmon_v6_3
* @addtogroup axipmon_v6_6
* @{
*
* This file contains the implementation of the XAxiPmon driver's static

2
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_2/src/xcanps.c
View File

@ -33,7 +33,7 @@
/**
*
* @file xcanps.c
* @addtogroup canps_v3_0
* @addtogroup canps_v3_2
* @{
*
* Functions in this file are the minimum required functions for the XCanPs

4
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_2/src/xcanps.h
View File

@ -33,7 +33,7 @@
/**
*
* @file xcanps.h
* @addtogroup canps_v3_0
* @addtogroup canps_v3_2
* @{
* @details
*
@ -204,6 +204,8 @@
* Data mismatch while sending data less than 8 bytes.
* 3.1 nsk 12/21/15 Updated XCanPs_IntrHandler in xcanps_intr.c to handle
* error interrupts correctly. CR#925615
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
* </pre>
*
******************************************************************************/

4
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_2/src/xcanps_g.c
View File

@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
@ -44,7 +44,7 @@
* The configuration table for devices
*/
XCanPs_Config XCanPs_ConfigTable[] =
XCanPs_Config XCanPs_ConfigTable[XPAR_XCANPS_NUM_INSTANCES] =
{
{
XPAR_PSU_CAN_1_DEVICE_ID,

2
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_2/src/xcanps_hw.c
View File

@ -33,7 +33,7 @@
/**
*
* @file xcanps_hw.c
* @addtogroup canps_v3_0
* @addtogroup canps_v3_2
* @{
*
* This file contains the implementation of the canps interface reset sequence

2
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_2/src/xcanps_hw.h
View File

@ -33,7 +33,7 @@
/**
*
* @file xcanps_hw.h
* @addtogroup canps_v3_0
* @addtogroup canps_v3_2
* @{
*
* This header file contains the identifiers and basic driver functions (or

2
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_2/src/xcanps_intr.c
View File

@ -33,7 +33,7 @@
/**
*
* @file xcanps_intr.c
* @addtogroup canps_v3_0
* @addtogroup canps_v3_2
* @{
*
* This file contains functions related to CAN interrupt handling.

2
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_2/src/xcanps_selftest.c
View File

@ -33,7 +33,7 @@
/**
*
* @file xcanps_selftest.c
* @addtogroup canps_v3_0
* @addtogroup canps_v3_2
* @{
*
* This file contains a diagnostic self-test function for the XCanPs driver.

2
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_2/src/xcanps_sinit.c
View File

@ -33,7 +33,7 @@
/**
*
* @file xcanps_sinit.c
* @addtogroup canps_v3_0
* @addtogroup canps_v3_2
* @{
*
* This file contains the implementation of the XCanPs driver's static

0
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/coresightps_dcc_v1_3/src/Makefile → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/coresightps_dcc_v1_4/src/Makefile
View File

6
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/coresightps_dcc_v1_3/src/xcoresightpsdcc.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.c
View File

@ -33,7 +33,7 @@
/**
*
* @file xcoresightpsdcc.c
* @addtogroup coresightps_dcc_v1_1
* @addtogroup coresightps_dcc_v1_4
* @{
*
* Functions in this file are the minimum required functions for the
@ -132,7 +132,7 @@ void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data)
******************************************************************************/
u8 XCoresightPs_DccRecvByte(u32 BaseAddress)
{
u8 Data;
u8 Data = 0U;
(void) BaseAddress;
while (!(XCoresightPs_DccGetStatus() & XCORESIGHTPS_DCC_STATUS_RX))
@ -169,7 +169,7 @@ u8 XCoresightPs_DccRecvByte(u32 BaseAddress)
******************************************************************************/
static INLINE u32 XCoresightPs_DccGetStatus(void)
{
u32 Status;
u32 Status = 0U;
#ifdef __aarch64__
asm volatile ("mrs %0, mdccsr_el0" : "=r" (Status));

2
FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_3/src/xcoresightpsdcc.h → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.h
View File

@ -33,7 +33,7 @@
/**
*
* @file xcoresightpsdcc.h
* @addtogroup coresightps_dcc_v1_1
* @addtogroup coresightps_dcc_v1_4
* @{
* @details
*

5
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/cpu_cortexa53_v1_2/src/Makefile → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/cpu_cortexa53_v1_5/src/Makefile
View File

@ -10,7 +10,7 @@ INCLUDEDIR=../../../include
INCLUDES=-I${INCLUDEDIR}
OUTS = *.o
OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
LIBSOURCES=*.c
INCLUDEFILES=*.h
@ -20,3 +20,6 @@ libs:
.PHONY: include
include:
${CP} $(INCLUDEFILES) $(INCLUDEDIR)
clean:
rm -rf ${OBJECTS}

7
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/cpu_cortexa53_v1_2/src/xcpu_cortexa53.h → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/cpu_cortexa53_v1_5/src/xcpu_cortexa53.h
View File

@ -33,11 +33,16 @@
/**
*
* @file xcpu_cortexa53.h
* @addtogroup cpu_cortexa53_v1_0
* @addtogroup cpu_cortexa53_v1_5
* @{
* @details
*
* dummy file
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------------
* 1.4 ms 04/18/17 Modified tcl file to add suffix U for XPAR_CPU_ID
* parameter of cpu_cortexa53 in xparameters.h
******************************************************************************/
/** @} */

0
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_1/src/Makefile → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_2/src/Makefile
View File

78
FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_2/src/xcsudma.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2014-2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -34,7 +34,7 @@
/**
*
* @file xcsudma.c
* @addtogroup csudma_v1_0
* @addtogroup csudma_v1_2
* @{
*
* This file contains the implementation of the interface functions for CSU_DMA
@ -188,6 +188,80 @@ void XCsuDma_Transfer(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
}
}
/*****************************************************************************/
/**
*
* This function sets the starting address and amount(size) of the data to be
* transfered from/to the memory through the AXI interface.
* This function is useful for pmu processor when it wishes to do
* a 64-bit DMA transfer.
*
* @param InstancePtr is a pointer to XCsuDma instance to be worked on.
* @param Channel represents the type of channel either it is Source or
* Destination.
* Source channel - XCSUDMA_SRC_CHANNEL
* Destination Channel - XCSUDMA_DST_CHANNEL
* @param AddrLow is a 32 bit variable which holds the starting lower address of
* data which needs to write into the memory(DST) (or read from
* the memory(SRC)).
* @param AddrHigh is a 32 bit variable which holds the higher address of data
* which needs to write into the memory(DST) (or read from
* the memroy(SRC)).
* @param Size is a 32 bit variable which represents the number of 4 byte
* words needs to be transfered from starting address.
* @param EnDataLast is to trigger an end of message. It will enable or
* disable data_inp_last signal to stream interface when current
* command is completed. It is applicable only to source channel
* and neglected for destination channel.
* - 1 - Asserts data_inp_last signal.
* - 0 - data_inp_last will not be asserted.
*
* @return None.
*
* @note Data_inp_last signal is asserted simultaneously with the
* data_inp_valid signal associated with the final 32-bit word
* transfer
* This API won't do flush/invalidation for the DMA buffer.
* It is recommened to call this API only through PMU processor.
*
******************************************************************************/
void XCsuDma_64BitTransfer(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
u32 AddrLow, u32 AddrHigh, u32 Size, u8 EnDataLast)
{
/* Verify arguments */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
(Channel == (XCSUDMA_DST_CHANNEL)));
Xil_AssertVoid(Size <= (u32)(XCSUDMA_SIZE_MAX));
Xil_AssertVoid(InstancePtr->IsReady == (u32)(XIL_COMPONENT_IS_READY));
XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
((u32)(XCSUDMA_ADDR_OFFSET) +
((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
(AddrLow & XCSUDMA_ADDR_MASK));
XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
((u32)(XCSUDMA_ADDR_MSB_OFFSET) +
((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
(AddrHigh & XCSUDMA_MSB_ADDR_MASK));
if (EnDataLast == (u8)(XCSUDMA_LAST_WORD_MASK)) {
XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
((u32)(XCSUDMA_SIZE_OFFSET) +
((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
((Size << (u32)(XCSUDMA_SIZE_SHIFT)) |
(u32)(XCSUDMA_LAST_WORD_MASK)));
}
else {
XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
((u32)(XCSUDMA_SIZE_OFFSET) +
((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
(Size << (u32)(XCSUDMA_SIZE_SHIFT)));
}
}
/*****************************************************************************/
/*****************************************************************************/
/**
*

13
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_1/src/xcsudma.h → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_2/src/xcsudma.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2014-2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -82,7 +82,7 @@
* to build and link only those parts of the driver that are necessary.
*
* @file xcsudma.h
* @addtogroup csudma_v1_0
* @addtogroup csudma_v1_2
* @{
* @details
*
@ -99,6 +99,13 @@
* 1.0 vnsld 22/10/14 First release
* 1.1 adk 10/05/16 Fixed CR#951040 race condition in the recv path when
* source and destination points to the same buffer.
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
* ms 04/10/17 Modified filename tag in xcsudma_selftest_example.c to
* include the file in doxygen examples.
* 1.2 adk 11/22/17 Added peripheral test app support for CSUDMA driver.
* adk 09/03/18 Added new API XCsuDma_64BitTransfer() useful for 64-bit
* dma transfers through PMU processor(CR#996201).
* </pre>
*
******************************************************************************/
@ -373,6 +380,8 @@ s32 XCsuDma_CfgInitialize(XCsuDma *InstancePtr, XCsuDma_Config *CfgPtr,
u32 EffectiveAddr);
void XCsuDma_Transfer(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
UINTPTR Addr, u32 Size, u8 EnDataLast);
void XCsuDma_64BitTransfer(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
u32 AddrLow, u32 AddrHigh, u32 Size, u8 EnDataLast);
void XCsuDma_LoopBackTransfer(XCsuDma *InstancePtr, u64 SrcAddr, u64 DstAddr,
u32 Size);
u64 XCsuDma_GetAddr(XCsuDma *InstancePtr, XCsuDma_Channel Channel);

4
FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_g.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_2/src/xcsudma_g.c
View File

@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
@ -44,7 +44,7 @@
* The configuration table for devices
*/
XCsuDma_Config XCsuDma_ConfigTable[] =
XCsuDma_Config XCsuDma_ConfigTable[XPAR_XCSUDMA_NUM_INSTANCES] =
{
{
XPAR_PSU_CSUDMA_DEVICE_ID,

2
FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_hw.h → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_2/src/xcsudma_hw.h
View File

@ -33,7 +33,7 @@
/**
*
* @file xcsudma_hw.h
* @addtogroup csudma_v1_0
* @addtogroup csudma_v1_2
* @{
*
* This header file contains identifiers and register-level driver functions (or

2
FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_intr.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_2/src/xcsudma_intr.c
View File

@ -34,7 +34,7 @@
/**
*
* @file xcsudma_intr.c
* @addtogroup csudma_v1_0
* @addtogroup csudma_v1_2
* @{
*
* This file contains interrupt related functions of Xilinx CSU_DMA core.

2
FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_selftest.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_2/src/xcsudma_selftest.c
View File

@ -34,7 +34,7 @@
/**
*
* @file xcsudma_selftest.c
* @addtogroup csudma_v1_0
* @addtogroup csudma_v1_2
* @{
*
* This file contains a diagnostic self-test function for the CSU_DMA driver.

2
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_1/src/xcsudma_sinit.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_2/src/xcsudma_sinit.c
View File

@ -34,7 +34,7 @@
/**
*
* @file xcsudma_sinit.c
* @addtogroup csudma_v1_0
* @addtogroup csudma_v1_2
* @{
*
* This file contains static initialization methods for Xilinx CSU_DMA core.

7
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ddrcpsu_v1_1/src/xddrcpsu.h
View File

@ -18,15 +18,14 @@
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
*******************************************************************************/
@ -34,7 +33,7 @@
/**
*
* @file xddcrpsu.h
* @addtogroup ddrcpsu_v1_0
* @addtogroup ddrcpsu_v1_1
* @{
* @details
*

40
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/dpdma_v1_0/src/Makefile Normal file
View File

@ -0,0 +1,40 @@
COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
CC_FLAGS = $(COMPILER_FLAGS)
ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
OUTS = *.o
LIBSOURCES:=*.c
INCLUDEFILES:=*.h
OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
libs: banner dpdma_libs clean
%.o: %.c
${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
banner:
echo "Compiling dpdma"
dpdma_libs: ${OBJECTS}
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
.PHONY: include
include: dpdma_includes
dpdma_includes:
${CP} ${INCLUDEFILES} ${INCLUDEDIR}
clean:
rm -rf ${OBJECTS}

966
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/dpdma_v1_0/src/xdpdma.c Normal file
View File

@ -0,0 +1,966 @@
/******************************************************************************
*
* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
*******************************************************************************/
/*****************************************************************************/
/**
*
* @file xdpdma.c
*
* This file contains the implementation of the interface functions of the
* XDpDma driver. Refer to xdpdma.h for detailed information.
*
* @note None.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ---- ----- -------- ----------------------------------------------------
* 1.0 aad 04/12/16 Initial release.
*
*****************************************************************************/
/***************************** Include Files **********************************/
#include "xdpdma.h"
#include "xavbuf.h"
/************************** Constant Definitions ******************************/
#define XDPDMA_CH_OFFSET 0x100
#define XDPDMA_WAIT_TIMEOUT 10000
#define XDPDMA_AUDIO_ALIGNMENT 128
#define XDPDMA_VIDEO_CHANNEL0 0
#define XDPDMA_VIDEO_CHANNEL1 1
#define XDPDMA_VIDEO_CHANNEL2 2
#define XDPDMA_GRAPHICS_CHANNEL 3
#define XDPDMA_AUDIO_CHANNEL0 4
#define XDPDMA_AUDIO_CHANNEL1 5
#define XDPDMA_DESC_PREAMBLE 0xA5
#define XDPDMA_DESC_IGNR_DONE 0x400
#define XDPDMA_DESC_UPDATE 0x200
#define XDPDMA_DESC_COMP_INTR 0x100
#define XDPDMA_DESC_LAST_FRAME 0x200000
#define XDPDMA_DESC_DONE_SHIFT 31
#define XDPDMA_QOS_MIN 4
#define XDPDMA_QOS_MAX 11
/*************************************************************************/
/**
*
* This function returns the number of outstanding transactions on a given
* channel.
*
* @param InstancePtr is a pointer to the driver instance.
* @param ChannelNum is the channel number on which the operation is
* being carried out.
*
* @return Number of pending transactions.
*
* @note None.
*
* **************************************************************************/
static int XDpDma_GetPendingTransaction(XDpDma *InstancePtr, u32 ChannelNum)
{
u32 RegVal;
RegVal = XDpDma_ReadReg(InstancePtr->Config.BaseAddr,
XDPDMA_CH0_STATUS + 0x100 * ChannelNum);
return (RegVal & XDPDMA_CH_STATUS_OTRAN_CNT_MASK);
}
/*************************************************************************/
/**
*
* This function waits until the outstanding transactions are completed.
*
* @param InstancePtr is a pointer to the driver instance.
* @param ChannelNum is the channel number on which the operation is
* being carried out.
*
* @return XST_SUCCESS when all the pending transactions are complete
* before timeout.
* XST_FAILURE if timeout occurs before pending transactions are
* completed.
*
* @note None.
*
* **************************************************************************/
static int XDpDma_WaitPendingTransaction(XDpDma *InstancePtr, u8 ChannelNum)
{
/* Verify arguments. */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(ChannelNum <= XDPDMA_AUDIO_CHANNEL1);
u32 Timeout = 0;
u32 Count;
do {
Count = XDpDma_GetPendingTransaction(InstancePtr, ChannelNum);
Timeout++;
} while((Timeout != XDPDMA_WAIT_TIMEOUT) && Count);
if(Timeout == XDPDMA_WAIT_TIMEOUT) {
return XST_FAILURE;
}
return XST_SUCCESS;
}
/*************************************************************************/
/**
*
* This function controls the hardware channels of the DPDMA.
*
*
* @param InstancePtr is a pointer to the driver instance.
* @param ChannelNum is the physical channel number of the DPDMA.
* @param ChannelState is an enum of type XDpDma_ChannelState.
*
* @return XST_SUCCESS when the mentioned channel is enabled successfully.
* XST_FAILURE when the mentioned channel fails to be enabled.
*
* @note None.
*
* **************************************************************************/
static int XDpDma_ConfigChannelState(XDpDma *InstancePtr, u8 ChannelNum,
XDpDma_ChannelState Enable)
{
u32 Mask = 0;
u32 RegVal = 0;
u32 Status = 0;
/* Verify arguments. */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(ChannelNum <= XDPDMA_AUDIO_CHANNEL1);
Mask = XDPDMA_CH_CNTL_EN_MASK | XDPDMA_CH_CNTL_PAUSE_MASK;
switch(Enable) {
case XDPDMA_ENABLE:
RegVal = XDPDMA_CH_CNTL_EN_MASK;
break;
case XDPDMA_DISABLE:
XDpDma_ConfigChannelState(InstancePtr, ChannelNum,
XDPDMA_PAUSE);
Status = XDpDma_WaitPendingTransaction(InstancePtr,
ChannelNum);
if(Status == XST_FAILURE) {
return XST_FAILURE;
}
RegVal = XDPDMA_DISABLE;
Mask = XDPDMA_CH_CNTL_EN_MASK;
break;
case XDPDMA_IDLE:
Status = XDpDma_ConfigChannelState(InstancePtr,
ChannelNum,
XDPDMA_DISABLE);
if(Status == XST_FAILURE) {
return XST_FAILURE;
}
RegVal = 0;
break;
case XDPDMA_PAUSE:
RegVal = XDPDMA_PAUSE;
break;
}
XDpDma_ReadModifyWrite(InstancePtr->Config.BaseAddr,
XDPDMA_CH0_CNTL + XDPDMA_CH_OFFSET * ChannelNum,
RegVal, Mask);
return XST_SUCCESS;
}
/*************************************************************************/
/**
*
* This function updates the descriptor that is not currently active on a
* Video/Graphics channel.
*
* @param InstancePtr is a pointer to the driver instance.
* @param Channel is a pointer to the channel on which the operation is
* to be carried out.
*
* @return Descriptor for next operation.
*
* @note None.
*
* **************************************************************************/
static XDpDma_Descriptor *XDpDma_UpdateVideoDescriptor(XDpDma_Channel *Channel)
{
if(Channel->Current == NULL) {
Channel->Current = &Channel->Descriptor0;
}
else if(Channel->Current == &Channel->Descriptor0) {
Channel->Current = &Channel->Descriptor1;
}
else if(Channel->Current == &Channel->Descriptor1) {
Channel->Current = &Channel->Descriptor0;
}
return Channel->Current;
}
/*************************************************************************/
/**
* This function programs the address of the descriptor about to be active
*
* @param InstancePtr is a pointer to the DPDMA instance.
* @param Channel is an enum of the channel for which the descriptor
* address is to be set.
*
* @return Descriptor for next operation.
*
* @note None.
*
* **************************************************************************/
static void XDpDma_SetDescriptorAddress(XDpDma *InstancePtr, u8 ChannelNum)
{
u32 AddrOffset;
u32 AddrEOffset;
Xil_AssertVoid(ChannelNum <= XDPDMA_AUDIO_CHANNEL1);
AddrOffset = XDPDMA_CH0_DSCR_STRT_ADDR +
(XDPDMA_CH_OFFSET * ChannelNum);
AddrEOffset = XDPDMA_CH0_DSCR_STRT_ADDRE +
(XDPDMA_CH_OFFSET * ChannelNum);
XDpDma_Descriptor *Descriptor = NULL;
switch(ChannelNum) {
case XDPDMA_VIDEO_CHANNEL0:
Descriptor = InstancePtr->Video.Channel[ChannelNum].Current;
break;
case XDPDMA_VIDEO_CHANNEL1:
Descriptor = InstancePtr->Video.Channel[ChannelNum].Current;
break;
case XDPDMA_VIDEO_CHANNEL2:
Descriptor = InstancePtr->Video.Channel[ChannelNum].Current;
break;
case XDPDMA_GRAPHICS_CHANNEL:
Descriptor = InstancePtr->Gfx.Channel.Current;
break;
case XDPDMA_AUDIO_CHANNEL0:
Descriptor = InstancePtr->Audio[0].Current;
break;
case XDPDMA_AUDIO_CHANNEL1:
Descriptor = InstancePtr->Audio[1].Current;
break;
}
XDpDma_WriteReg(InstancePtr->Config.BaseAddr, AddrEOffset,
(INTPTR) Descriptor >> 32);
XDpDma_WriteReg(InstancePtr->Config.BaseAddr, AddrOffset,
(INTPTR) Descriptor);
}
/*************************************************************************/
/**
*
* This functions sets the Audio Descriptor for Data Transfer.
*
* @param CurrDesc is a pointer to the descriptor to be initialized
* @param DataSize is the payload size of the buffer to be transferred
* @param BuffAddr is the payload address
*
* @return None.
*
* @note None.
*
* **************************************************************************/
static void XDpDma_SetupAudioDescriptor(XDpDma_Descriptor *CurrDesc,
u64 DataSize, u64 BuffAddr,
XDpDma_Descriptor *NextDesc)
{
Xil_AssertVoid(CurrDesc != NULL);
Xil_AssertVoid(DataSize != 0);
Xil_AssertVoid(BuffAddr != 0);
if(NextDesc == NULL) {
CurrDesc->Control = XDPDMA_DESC_PREAMBLE |
XDPDMA_DESC_UPDATE | XDPDMA_DESC_IGNR_DONE |
XDPDMA_DESC_COMP_INTR;
}
else {
CurrDesc->Control = XDPDMA_DESC_PREAMBLE |
XDPDMA_DESC_UPDATE | XDPDMA_DESC_IGNR_DONE;
}
CurrDesc->DSCR_ID = 0;
CurrDesc->XFER_SIZE = DataSize;
CurrDesc->LINE_SIZE_STRIDE = 0;
CurrDesc->LSB_Timestamp = 0;
CurrDesc->MSB_Timestamp = 0;
CurrDesc->ADDR_EXT = ((BuffAddr >> XDPDMA_DESCRIPTOR_SRC_ADDR_WIDTH) <<
XDPDMA_DESCRIPTOR_ADDR_EXT_SRC_ADDR_EXT_SHIFT) |
((INTPTR) NextDesc >>
XDPDMA_DESCRIPTOR_NEXT_DESR_WIDTH);
CurrDesc->NEXT_DESR = (INTPTR) NextDesc;
CurrDesc->SRC_ADDR = BuffAddr;
}
/*************************************************************************/
/**
*
* This functions retrieves the configuration for this DPDMA driver and
* fills in the InstancePtr->Config structure.
*
* @param InstancePtr is a pointer to the driver instance.
* @param ConfigPtr is a pointer to the configuration structure that will
* be used to copy the settings from.
*
* @return None.
*
* @note None.
*
* **************************************************************************/
void XDpDma_CfgInitialize(XDpDma *InstancePtr, XDpDma_Config *CfgPtr)
{
InstancePtr->Config.DeviceId = CfgPtr->DeviceId;
InstancePtr->Config.BaseAddr = CfgPtr->BaseAddr;
InstancePtr->Video.Channel[XDPDMA_VIDEO_CHANNEL0].Current = NULL;
InstancePtr->Video.Channel[XDPDMA_VIDEO_CHANNEL1].Current = NULL;
InstancePtr->Video.Channel[XDPDMA_VIDEO_CHANNEL2].Current = NULL;
InstancePtr->Video.TriggerStatus = XDPDMA_TRIGGER_DONE;
InstancePtr->Video.VideoInfo = NULL;
InstancePtr->Video.FrameBuffer[XDPDMA_VIDEO_CHANNEL0] = NULL;
InstancePtr->Video.FrameBuffer[XDPDMA_VIDEO_CHANNEL1] = NULL;
InstancePtr->Video.FrameBuffer[XDPDMA_VIDEO_CHANNEL2] = NULL;
InstancePtr->Gfx.Channel.Current = NULL;
InstancePtr->Gfx.TriggerStatus = XDPDMA_TRIGGER_DONE;
InstancePtr->Gfx.VideoInfo = NULL;
InstancePtr->Gfx.FrameBuffer = NULL;
}
/*************************************************************************/
/**
*
* This functions controls the states in which a channel should go into.
*
* @param InstancePtr is a pointer to the driver instance.
* @param ChannelType is an enum of XDpDma_ChannelType.
* @param ChannelState is an enum of type XDpDma_ChannelState.
*
* @return XST_SUCCESS when the mentioned channel is enabled successfully.
* XST_FAILURE when the mentioned channel fails to be enabled.
*
* @note None.
*
* **************************************************************************/
int XDpDma_SetChannelState(XDpDma *InstancePtr, XDpDma_ChannelType Channel,
XDpDma_ChannelState ChannelState)
{
u32 Index = 0;
u32 NumPlanes = 0;
u32 Status = 0;
/* Verify arguments. */
Xil_AssertNonvoid(InstancePtr != NULL);
switch(Channel) {
case VideoChan:
if(InstancePtr->Video.VideoInfo == NULL) {
return XST_FAILURE;
}
else {
NumPlanes = InstancePtr->Video.VideoInfo->Mode;
for(Index = 0; Index <= NumPlanes; Index++) {
Status = XDpDma_ConfigChannelState(InstancePtr,
Index,
ChannelState);
if(Status == XST_FAILURE) {
return XST_FAILURE;
}
}
}
break;
case GraphicsChan:
if(InstancePtr->Gfx.VideoInfo == NULL) {
return XST_FAILURE;
}
else {
return XDpDma_ConfigChannelState(InstancePtr,
XDPDMA_GRAPHICS_CHANNEL,
ChannelState);
}
break;
case AudioChan0:
return XDpDma_ConfigChannelState(InstancePtr,
XDPDMA_AUDIO_CHANNEL0,
ChannelState);
break;
case AudioChan1:
return XDpDma_ConfigChannelState(InstancePtr,
XDPDMA_AUDIO_CHANNEL1,
ChannelState);
break;
default:
return XST_FAILURE;
break;
}
return XST_SUCCESS;
}
/*************************************************************************/
/**
*
* This function allocates DPDMA Video Channels depending on the number of
* planes in the video
*
* @param InstancePtr is a pointer to the driver instance.
* @params Format is the video format to be used for the DPDMA transfer
*
* @return XST_SUCCESS, When the format is valid Video Format.
* XST_FAILURE, When the format is not valid Video Format
*
* @note None.
*
* **************************************************************************/
int XDpDma_SetVideoFormat(XDpDma *InstancePtr, XAVBuf_VideoFormat Format)
{
/* Verify arguments. */
Xil_AssertNonvoid(InstancePtr != NULL);
InstancePtr->Video.VideoInfo = XAVBuf_GetNLiveVideoAttribute(Format);
if(InstancePtr->Video.VideoInfo == NULL) {
return XST_FAILURE;
}
return XST_SUCCESS;
}
/*************************************************************************/
/**
*
* This function allocates DPDMA Graphics Channels.
*
* @param InstancePtr is a pointer to the driver instance.
* @params Format is the video format to be used for the DPDMA transfer
*
* @return XST_SUCCESS, When the format is a valid Graphics Format.
* XST_FAILURE, When the format is not valid Graphics Format.
*
* @note None.
*
* **************************************************************************/
int XDpDma_SetGraphicsFormat(XDpDma *InstancePtr, XAVBuf_VideoFormat Format)
{
/* Verify arguments. */
Xil_AssertNonvoid(InstancePtr != NULL);
InstancePtr->Gfx.VideoInfo = XAVBuf_GetNLGraphicsAttribute(Format);
if(InstancePtr->Gfx.VideoInfo == NULL) {
return XST_FAILURE;
}
return XST_SUCCESS;
}
/*************************************************************************/
/**
*
* This function starts the operation on the a given channel
*
* @param InstancePtr is a pointer to the driver instance.
* @param QOS is the Quality of Service value to be selected.
*
* @return None.
*
* @note .
*
* **************************************************************************/
void XDpDma_SetQOS(XDpDma *InstancePtr, u8 QOS)
{
u8 Index;
u32 RegVal = 0;
Xil_AssertVoid(QOS >= XDPDMA_QOS_MIN && QOS <= XDPDMA_QOS_MAX);
RegVal = ((QOS << XDPDMA_CH_CNTL_QOS_DATA_RD_SHIFT) |
(QOS << XDPDMA_CH_CNTL_QOS_DSCR_RD_SHIFT) |
(QOS << XDPDMA_CH_CNTL_QOS_DSCR_WR_SHIFT));
u32 Mask = XDPDMA_CH_CNTL_QOS_DATA_RD_MASK |
XDPDMA_CH_CNTL_QOS_DSCR_RD_MASK |
XDPDMA_CH_CNTL_QOS_DSCR_WR_MASK;
for(Index = 0; Index <= XDPDMA_AUDIO_CHANNEL1; Index++) {
XDpDma_ReadModifyWrite(InstancePtr->Config.BaseAddr,
XDPDMA_CH0_CNTL + (XDPDMA_CH_OFFSET * Index),
RegVal, Mask);
}
}
/*************************************************************************/
/**
*
* This function Triggers DPDMA to start the transaction.
*
* @param InstancePtr is a pointer to the XDpDma instance.
* @param Channel is the XDpDma_ChannelType on which the transaction
* is to be triggered.
*
* @return XST_SUCCESS The channel has successfully been Triggered.
* XST_FAILURE When the triggering Video and Graphics channel
* without setting the Video Formats.
*
* @note None.
*
* **************************************************************************/
int XDpDma_Trigger(XDpDma *InstancePtr, XDpDma_ChannelType Channel)
{
u32 Trigger = 0;
u8 Index = 0;
u8 NumPlanes = 0;
switch(Channel) {
case VideoChan:
if(InstancePtr->Video.VideoInfo == NULL) {
return XST_FAILURE;
}
else {
NumPlanes = InstancePtr->Video.VideoInfo->Mode;
for(Index = 0; Index <= NumPlanes; Index++) {
Trigger |= XDPDMA_GBL_TRG_CH0_MASK << Index;
InstancePtr->Video.TriggerStatus =
XDPDMA_TRIGGER_DONE;
}
}
break;
case GraphicsChan:
if(InstancePtr->Gfx.VideoInfo == NULL) {
return XST_FAILURE;
}
Trigger = XDPDMA_GBL_TRG_CH3_MASK;
InstancePtr->Gfx.TriggerStatus = XDPDMA_TRIGGER_DONE;
break;
case AudioChan0:
Trigger = XDPDMA_GBL_TRG_CH4_MASK;
InstancePtr->Audio[0].TriggerStatus = XDPDMA_TRIGGER_DONE;
break;
case AudioChan1:
Trigger = XDPDMA_GBL_TRG_CH5_MASK;
InstancePtr->Audio[1].TriggerStatus = XDPDMA_TRIGGER_DONE;
break;
}
XDpDma_WriteReg(InstancePtr->Config.BaseAddr, XDPDMA_GBL, Trigger);
return XST_SUCCESS;
}
/*************************************************************************/
/**
*
* This function Retriggers DPDMA to fetch data from new descriptor.
*
* @param InstancePtr is a pointer to the XDpDma instance.
* @param Channel is the XDpDma_ChannelType on which the transaction
* is to be retriggered.
*
* @return XST_SUCCESS The channel has successfully been Triggered.
* XST_FAILURE When the triggering Video and Graphics channel
* without setting the Video Formats.
*
* @note None.
*
* **************************************************************************/
int XDpDma_ReTrigger(XDpDma *InstancePtr, XDpDma_ChannelType Channel)
{
u32 Trigger = 0;
u8 NumPlanes;
u8 Index;
switch(Channel) {
case VideoChan:
if(InstancePtr->Video.VideoInfo == NULL) {
return XST_FAILURE;
}
else {
NumPlanes = InstancePtr->Video.VideoInfo->Mode;
for(Index = 0; Index <= NumPlanes; Index++) {
Trigger |= XDPDMA_GBL_RTRG_CH0_MASK << Index;
InstancePtr->Video.TriggerStatus =
XDPDMA_RETRIGGER_DONE;
}
}
break;
case GraphicsChan:
if(InstancePtr->Gfx.VideoInfo == NULL) {
return XST_FAILURE;
}
Trigger = XDPDMA_GBL_RTRG_CH3_MASK;
InstancePtr->Gfx.TriggerStatus = XDPDMA_RETRIGGER_DONE;
break;
case AudioChan0:
Trigger = XDPDMA_GBL_RTRG_CH4_MASK;
InstancePtr->Audio[0].TriggerStatus = XDPDMA_RETRIGGER_DONE;
break;
case AudioChan1:
Trigger = XDPDMA_GBL_RTRG_CH5_MASK;
InstancePtr->Audio[1].TriggerStatus = XDPDMA_RETRIGGER_DONE;
break;
}
XDpDma_WriteReg(InstancePtr->Config.BaseAddr, XDPDMA_GBL, Trigger);
return XST_SUCCESS;
}
/*************************************************************************/
/**
*
* This function intializes Video Descriptor for Video and Graphics channel
*
* @param Channel is a pointer to the current Descriptor of Video or
* Graphics Channel.
* @param FrameBuffer is a pointer to the Frame Buffer structure
*
* @return None.
*
* @note None.
*
* **************************************************************************/
void XDpDma_InitVideoDescriptor(XDpDma_Descriptor *CurrDesc,
XDpDma_FrameBuffer *FrameBuffer)
{
Xil_AssertVoid(CurrDesc != NULL);
Xil_AssertVoid(FrameBuffer != NULL);
Xil_AssertVoid((FrameBuffer->Stride) % XDPDMA_DESCRIPTOR_ALIGN == 0);
CurrDesc->Control = XDPDMA_DESC_PREAMBLE | XDPDMA_DESC_IGNR_DONE |
XDPDMA_DESC_LAST_FRAME;
CurrDesc->DSCR_ID = 0;
CurrDesc->XFER_SIZE = FrameBuffer->Size;
CurrDesc->LINE_SIZE_STRIDE = ((FrameBuffer->Stride >> 4) <<
XDPDMA_DESCRIPTOR_LINE_SIZE_STRIDE_SHIFT) |
(FrameBuffer->LineSize);
CurrDesc->ADDR_EXT = (((FrameBuffer->Address >>
XDPDMA_DESCRIPTOR_SRC_ADDR_WIDTH) <<
XDPDMA_DESCRIPTOR_ADDR_EXT_SRC_ADDR_EXT_SHIFT) |
((INTPTR) CurrDesc >>
XDPDMA_DESCRIPTOR_NEXT_DESR_WIDTH));
CurrDesc->NEXT_DESR = (INTPTR) CurrDesc;
CurrDesc->SRC_ADDR = FrameBuffer->Address;
}
/*************************************************************************/
/**
*
* This function intializes Descriptors for transactions on Audio Channel
*
* @param Channel is a pointer to the XDpDma_AudioChannel instance
*
* @param AudioBuffer is a pointer to the Audio Buffer structure
*
* @return None.
*
* @note None.
*
* **************************************************************************/
void XDpDma_InitAudioDescriptor(XDpDma_AudioChannel *Channel,
XDpDma_AudioBuffer *AudioBuffer)
{
u32 Size;
u64 Address;
Xil_AssertVoid(Channel != NULL);
Xil_AssertVoid(AudioBuffer != NULL);
Xil_AssertVoid((AudioBuffer->Size) % XDPDMA_AUDIO_ALIGNMENT == 0);
Xil_AssertVoid((AudioBuffer->Address) % XDPDMA_AUDIO_ALIGNMENT == 0);
Size = AudioBuffer->Size / 4;
Address = AudioBuffer->Address;
if(Channel->Current == &Channel->Descriptor4) {
XDpDma_SetupAudioDescriptor(&Channel->Descriptor4, Size,
Address,
&Channel->Descriptor5);
XDpDma_SetupAudioDescriptor(&Channel->Descriptor5, Size,
Address + Size,
&Channel->Descriptor6);
XDpDma_SetupAudioDescriptor(&Channel->Descriptor6, Size,
Address + (Size * 2),
&Channel->Descriptor7);
XDpDma_SetupAudioDescriptor(&Channel->Descriptor7, Size,
Address + (Size * 3), NULL);
}
else if(Channel->Current == &Channel->Descriptor0) {
XDpDma_SetupAudioDescriptor(&Channel->Descriptor0, Size,
Address,
&Channel->Descriptor1);
XDpDma_SetupAudioDescriptor(&Channel->Descriptor1, Size,
Address + Size,
&Channel->Descriptor2);
XDpDma_SetupAudioDescriptor(&Channel->Descriptor2, Size,
Address + (Size * 2),
&Channel->Descriptor3);
XDpDma_SetupAudioDescriptor(&Channel->Descriptor3, Size,
Address + (Size * 3), NULL);
}
}
/*************************************************************************/
/**
*
* This function sets the next Frame Buffers to be displayed on the Video
* Channel.
*
* @param InstancePtr is pointer to the instance of DPDMA.
* @param Plane0 is a pointer to the Frame Buffer structure.
* @param Plane1 is a pointer to the Frame Buffer structure.
* @param Plane2 is a pointer to the Frame Buffer structure.
*
* @return None.
*
* @note For interleaved mode use Plane0.
* For semi-planar mode use Plane0 and Plane1.
* For planar mode use Plane0, Plane1 and Plane2
*
* **************************************************************************/
void XDpDma_DisplayVideoFrameBuffer(XDpDma *InstancePtr,
XDpDma_FrameBuffer *Plane0,
XDpDma_FrameBuffer *Plane1,
XDpDma_FrameBuffer *Plane2)
{
u8 NumPlanes;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->Video.VideoInfo != NULL);
NumPlanes = InstancePtr->Video.VideoInfo->Mode;
switch(NumPlanes) {
case XDPDMA_VIDEO_CHANNEL2:
Xil_AssertVoid(Plane2 != NULL);
InstancePtr->Video.FrameBuffer[XDPDMA_VIDEO_CHANNEL2] =
Plane2;
case XDPDMA_VIDEO_CHANNEL1:
Xil_AssertVoid(Plane1 != NULL);
InstancePtr->Video.FrameBuffer[XDPDMA_VIDEO_CHANNEL1] =
Plane1;
case XDPDMA_VIDEO_CHANNEL0:
Xil_AssertVoid(Plane0 != NULL);
InstancePtr->Video.FrameBuffer[XDPDMA_VIDEO_CHANNEL0] =
Plane0;
break;
}
if(InstancePtr->Video.Channel[XDPDMA_VIDEO_CHANNEL0].Current == NULL) {
InstancePtr->Video.TriggerStatus = XDPDMA_TRIGGER_EN;
}
else {
InstancePtr->Video.TriggerStatus = XDPDMA_RETRIGGER_EN;
}
}
/*************************************************************************/
/**
*
* This function sets the next Frame Buffers to be displayed on the Graphics
* Channel.
*
* @param InstancePtr is pointer to the instance of DPDMA.
* @param Plane is a pointer to the Frame Buffer structure.
*
* @return None.
*
* @note None.
*
**************************************************************************/
void XDpDma_DisplayGfxFrameBuffer(XDpDma *InstancePtr,
XDpDma_FrameBuffer *Plane)
{
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(Plane != NULL);
InstancePtr->Gfx.FrameBuffer = Plane;
if(InstancePtr->Gfx.Channel.Current == NULL) {
InstancePtr->Gfx.TriggerStatus = XDPDMA_TRIGGER_EN;
}
else {
InstancePtr->Gfx.TriggerStatus = XDPDMA_RETRIGGER_EN;
}
}
/*************************************************************************/
/**
*
* This function sets the next Audio Buffer to be played on Audio Channel 0
*
* @param InstancePtr is pointer to the instance of DPDMA.
* @param Buffer is a pointer to the attributes of the Audio information
* to be played.
* @param ChannelNum selects between Audio Channel 0 and Audio Channel 1
*
* @return XST_SUCCESS when the play audio request is successful.
* XST_FAILURE when the play audio request fails, user has to
* retry to play the audio.
*
* @note The user has to schedule new audio buffer before half the audio
* information is consumed by DPDMA to have a seamless playback.
*
**************************************************************************/
int XDpDma_PlayAudio(XDpDma *InstancePtr, XDpDma_AudioBuffer *Buffer,
u8 ChannelNum)
{
XDpDma_AudioChannel *Channel;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(Buffer != NULL);
Xil_AssertNonvoid(Buffer->Size >= 512);
Xil_AssertNonvoid(Buffer->Size % 128 == 0);
Xil_AssertNonvoid(Buffer->Address % 128 == 0);
Channel = &InstancePtr->Audio[ChannelNum];
Channel->Buffer = Buffer;
if(Channel->Current == NULL) {
Channel->TriggerStatus = XDPDMA_TRIGGER_EN;
Channel->Current = &Channel->Descriptor0;
Channel->Used = 0;
}
else if(Channel->Current == &Channel->Descriptor0) {
/* Check if descriptor chain can be updated */
if(Channel->Descriptor1.MSB_Timestamp >>
XDPDMA_DESC_DONE_SHIFT) {
Channel->Current = NULL;
return XST_FAILURE;
}
else if(Channel->Descriptor7.MSB_Timestamp >>
XDPDMA_DESC_DONE_SHIFT || !(Channel->Used)) {
Channel->Descriptor3.Control = XDPDMA_DESC_PREAMBLE |
XDPDMA_DESC_UPDATE | XDPDMA_DESC_IGNR_DONE;
Channel->Descriptor3.NEXT_DESR =
(INTPTR) &Channel->Descriptor4;
Channel->Descriptor3.ADDR_EXT &=
~XDPDMA_DESCRIPTOR_ADDR_EXT_DSC_NXT_MASK;
Channel->Descriptor3.ADDR_EXT |=
(INTPTR) &Channel->Descriptor4 >> 32;
Channel->Current = &Channel->Descriptor4;
Channel->Used = 1;
XDpDma_InitAudioDescriptor(Channel, Buffer);
}
else {
return XST_FAILURE;
}
}
else if(Channel->Current == &Channel->Descriptor4) {
/* Check if descriptor chain can be updated */
if(Channel->Descriptor5.MSB_Timestamp >>
XDPDMA_DESC_DONE_SHIFT) {
Channel->Current = NULL;
return XST_FAILURE;
}
else if(Channel->Descriptor3.MSB_Timestamp >>
XDPDMA_DESC_DONE_SHIFT) {
Channel->Descriptor7.Control = XDPDMA_DESC_PREAMBLE |
XDPDMA_DESC_UPDATE | XDPDMA_DESC_IGNR_DONE;
Channel->Descriptor7.NEXT_DESR =
(INTPTR) &Channel->Descriptor0;
Channel->Descriptor7.ADDR_EXT &=
~XDPDMA_DESCRIPTOR_ADDR_EXT_DSC_NXT_MASK;
Channel->Descriptor7.ADDR_EXT |=
(INTPTR) &Channel->Descriptor0 >> 32;
Channel->Current = &Channel->Descriptor0;
XDpDma_InitAudioDescriptor(Channel, Buffer);
}
else {
return XST_FAILURE;
}
}
return XST_SUCCESS;
}
/*************************************************************************/
/**
*
* This function sets the channel with the latest framebuffer and the
* available descriptor for transfer on the next Vsync.
*
* @param InstancePtr is pointer to the instance of DPDMA.
* @param Channel indicates which channels are being setup for transfer.
*
* @return None.
*
* @note None.
*
**************************************************************************/
void XDpDma_SetupChannel(XDpDma *InstancePtr, XDpDma_ChannelType Channel)
{
XDpDma_Channel *Chan;
XDpDma_AudioChannel *AudChan;
XDpDma_FrameBuffer *FB;
XDpDma_AudioBuffer *AudioBuffer;
u8 Index, NumPlanes;
Xil_AssertVoid(InstancePtr != NULL);
switch(Channel) {
case VideoChan:
Xil_AssertVoid(InstancePtr->Video.VideoInfo != NULL);
Xil_AssertVoid(InstancePtr->Video.FrameBuffer != NULL);
NumPlanes = InstancePtr->Video.VideoInfo->Mode;
for(Index = 0; Index <= NumPlanes; Index++) {
Chan = &InstancePtr->Video.Channel[Index];
FB = InstancePtr->Video.FrameBuffer[Index];
XDpDma_UpdateVideoDescriptor(Chan);
XDpDma_InitVideoDescriptor(Chan->Current, FB);
XDpDma_SetDescriptorAddress(InstancePtr,
Index);
}
break;
case GraphicsChan:
Xil_AssertVoid(InstancePtr->Gfx.VideoInfo != NULL);
Xil_AssertVoid(InstancePtr->Gfx.FrameBuffer != NULL);
Chan = &InstancePtr->Gfx.Channel;
FB = InstancePtr->Gfx.FrameBuffer;
XDpDma_UpdateVideoDescriptor(Chan);
XDpDma_InitVideoDescriptor(Chan->Current, FB);
XDpDma_SetDescriptorAddress(InstancePtr,
XDPDMA_GRAPHICS_CHANNEL);
break;
case AudioChan0:
Xil_AssertVoid(InstancePtr->Audio[0].Buffer != NULL);
AudChan = &InstancePtr->Audio[0];
AudioBuffer = InstancePtr->Audio[0].Buffer;
XDpDma_InitAudioDescriptor(AudChan, AudioBuffer);
XDpDma_SetDescriptorAddress(InstancePtr,
XDPDMA_AUDIO_CHANNEL0);
break;
case AudioChan1:
Xil_AssertVoid(InstancePtr->Audio[1].Buffer != NULL);
AudChan = &InstancePtr->Audio[1];
AudioBuffer = InstancePtr->Audio[1].Buffer;
XDpDma_InitAudioDescriptor(AudChan, AudioBuffer);
XDpDma_SetDescriptorAddress(InstancePtr,
XDPDMA_AUDIO_CHANNEL1);
break;
}
}

283
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/dpdma_v1_0/src/xdpdma.h Normal file
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/******************************************************************************
*
* Copyright (C) 2017 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xdpdma.h
*
* This file defines the functions implemented by the DPDMA driver present
* in the Zynq Ultrascale MP.
*
* @note None.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ---- ----- -------- ----------------------------------------------------
* 1.0 aad 04/12/16 Initial release.
*
*****************************************************************************/
#ifndef XDPDMA_H_
/* Prevent circular inclusions by using protection macros. */
#define XDPDMA_H_
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files **********************************/
#include "xdpdma_hw.h"
#include "xvidc.h"
#include "xil_io.h"
#include "xil_assert.h"
#include "xstatus.h"
#include "xavbuf.h"
/************************** Constant Definitions ******************************/
/* Alignment for DPDMA Descriptor and Payload */
#define XDPDMA_DESCRIPTOR_ALIGN 256
/* DPDMA preamble field */
#define XDPDMA_DESCRIPTOR_PREAMBLE 0xA5
/**************************** Type Definitions ********************************/
/**
* This typedef describes the DPDMA descriptor structure and its internals
* which will be used when fetching data from a nonlive path
*/
typedef struct {
u32 Control; /**< [7:0] Descriptor Preamble
[8] Enable completion Interrupt
[9] Enable descriptor update
[10] Ignore Done
[11] AXI burst type
[15:12] AXACHE
[17:16] AXPROT
[18] Descriptor mode
[19] Last Descriptor
[20] Enable CRC
[21] Last descriptor frame
[31:22] Reserved */
u32 DSCR_ID; /**< [15:0] Descriptor ID
[31:16] Reserved */
u32 XFER_SIZE; /**< Size of transfer in bytes */
u32 LINE_SIZE_STRIDE; /**< [17:0] Horizontal Resolution
[31:18] Stride */
u32 LSB_Timestamp; /**< LSB of the Timestamp */
u32 MSB_Timestamp; /**< MSB of the Timestamp */
u32 ADDR_EXT; /**< [15:0] Next descriptor
extenstion
[31:16] SRC address extemsion */
u32 NEXT_DESR; /**< Address of next descriptor */
u32 SRC_ADDR; /**< Source Address */
u32 ADDR_EXT_23; /**< [15:0] Address extension for SRC
Address2
[31:16] Address extension for
SRC Address 3 */
u32 ADDR_EXT_45; /**< [15:0] Address extension for SRC
Address4
[31:16] Address extension for
SRC Address 5 */
u32 SRC_ADDR2; /**< Source address of 2nd page */
u32 SRC_ADDR3; /**< Source address of 3rd page */
u32 SRC_ADDR4; /**< Source address of 4th page */
u32 SRC_ADDR5; /**< Source address of 5th page */
u32 CRC; /**< Reserved */
} XDpDma_Descriptor __attribute__ ((aligned(XDPDMA_DESCRIPTOR_ALIGN)));
/**
* This typedef contains configuration information for the DPDMA.
*/
typedef struct {
u16 DeviceId; /**< Device ID */
u32 BaseAddr; /**< Base Address */
} XDpDma_Config;
/**
* The following data structure enumerates the types of
* DPDMA channels
*/
typedef enum {
VideoChan,
GraphicsChan,
AudioChan0,
AudioChan1,
} XDpDma_ChannelType;
/**
* This typedef lists the channel status.
*/
typedef enum {
XDPDMA_DISABLE,
XDPDMA_ENABLE,
XDPDMA_IDLE,
XDPDMA_PAUSE
} XDpDma_ChannelState;
/**
* This typedef is the information needed to transfer video info.
*/
typedef struct {
u64 Address;
u32 Size;
u32 Stride;
u32 LineSize;
} XDpDma_FrameBuffer;
/**
* This typedef is the information needed to transfer audio info.
*/
typedef struct {
u64 Address;
u64 Size;
} XDpDma_AudioBuffer;
/**
* This typedef defines the Video/Graphics Channel attributes.
*/
typedef struct {
XDpDma_Descriptor Descriptor0;
XDpDma_Descriptor Descriptor1;
XDpDma_Descriptor *Current;
} XDpDma_Channel;
/**
* This typedef defines the Video Channel attributes.
*/
typedef struct {
XDpDma_Channel Channel[3];
u8 TriggerStatus;
u8 AVBufEn;
XAVBuf_VideoAttribute *VideoInfo;
XDpDma_FrameBuffer *FrameBuffer[3];
} XDpDma_VideoChannel;
/**
* This typedef defines the Graphics Channel attributes.
*/
typedef struct {
XDpDma_Channel Channel;
u8 TriggerStatus;
u8 AVBufEn;
XAVBuf_VideoAttribute *VideoInfo;
XDpDma_FrameBuffer *FrameBuffer;
} XDpDma_GfxChannel;
/**
* This typedef defines the Audio Channel attributes.
*/
typedef struct {
XDpDma_Descriptor Descriptor0, Descriptor1, Descriptor2;
XDpDma_Descriptor Descriptor3, Descriptor4, Descriptor5;
XDpDma_Descriptor Descriptor6, Descriptor7;
XDpDma_Descriptor *Current;
u8 TriggerStatus;
XDpDma_AudioBuffer *Buffer;
u8 Used;
} XDpDma_AudioChannel;
/*************************************************************************/
/**
* This callback type represents the handler for a DPDMA VSync interrupt.
*
* @param InstancePtr is a pointer to the XDpDma instance.
*
* @note None.
*
**************************************************************************/
typedef void (*XDpDma_VSyncInterruptHandler)(void *InstancePtr);
/*************************************************************************/
/**
* This callback type represents the handler for a DPDMA Done interrupt.
*
* @param InstancePtr is a pointer to the XDpDma instance.
*
* @note None.
*
**************************************************************************/
typedef void (*XDpDma_DoneInterruptHandler)(void *InstancePtr);
/**
* The XDpDma driver instance data representing the DPDMA operation.
*/
typedef struct {
XDpDma_Config Config;
XDpDma_VideoChannel Video;
XDpDma_GfxChannel Gfx;
XDpDma_AudioChannel Audio[2];
XVidC_VideoTiming *Timing;
u8 QOS;
XDpDma_VSyncInterruptHandler VSyncHandler;
void * VSyncInterruptHandler;
XDpDma_DoneInterruptHandler DoneHandler;
void * DoneInterruptHandler;
} XDpDma;
void XDpDma_CfgInitialize(XDpDma *InstancePtr, XDpDma_Config *CfgPtr);
XDpDma_Config *XDpDma_LookupConfig(u16 DeviceId);
int XDpDma_SetChannelState(XDpDma *InstancePtr, XDpDma_ChannelType Channel,
XDpDma_ChannelState ChannelState);
void XDpDma_SetQOS(XDpDma *InstancePtr, u8 QOS);
void XDpDma_SetupChannel(XDpDma *InstancePtr, XDpDma_ChannelType Channel);
int XDpDma_SetVideoFormat(XDpDma *InstancePtr, XAVBuf_VideoFormat Format);
int XDpDma_SetGraphicsFormat(XDpDma *InstancePtr, XAVBuf_VideoFormat Format);
void XDpDma_SetVideoTiming(XDpDma *InstancePtr, XVidC_VideoTiming *Timing);
int XDpDma_Trigger(XDpDma *InstancePtr, XDpDma_ChannelType Channel);
int XDpDma_ReTrigger(XDpDma *InstancePtr, XDpDma_ChannelType Channel);
void XDpDma_InterruptEnable(XDpDma *InstancePtr, u32 Mask);
void XDpDma_InterruptHandler(XDpDma *InstancePtr);
void XDpDma_VSyncHandler(XDpDma *InstancePtr);
void XDpDma_DoneHandler(XDpDma *InstancePtr);
void XDpDma_InitVideoDescriptor(XDpDma_Descriptor *CurrDesc,
XDpDma_FrameBuffer *FrameBuffer);
void XDpDma_DisplayVideoFrameBuffer(XDpDma *InstancePtr,
XDpDma_FrameBuffer *Plane1,
XDpDma_FrameBuffer *Plane2,
XDpDma_FrameBuffer *Plane3);
void XDpDma_DisplayGfxFrameBuffer(XDpDma *InstancePtr,
XDpDma_FrameBuffer *Plane);
void XDpDma_InitAudioDescriptor(XDpDma_AudioChannel *Channel,
XDpDma_AudioBuffer *AudioBuffer);
int XDpDma_PlayAudio(XDpDma *InstancePtr, XDpDma_AudioBuffer *Buffer,
u8 ChannelNum);
#ifdef __cplusplus
}
#endif
#endif /* _XDPDMA_H_ */

55
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/dpdma_v1_0/src/xdpdma_g.c Normal file
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/*******************************************************************
*
* CAUTION: This file is automatically generated by HSI.
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
*copies of the Software, and to permit persons to whom the Software is
*furnished to do so, subject to the following conditions:
*
*The above copyright notice and this permission notice shall be included in
*all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
*(a) running on a Xilinx device, or
*(b) that interact with a Xilinx device through a bus or interconnect.
*
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*Except as contained in this notice, the name of the Xilinx shall not be used
*in advertising or otherwise to promote the sale, use or other dealings in
*this Software without prior written authorization from Xilinx.
*
*
* Description: Driver configuration
*
*******************************************************************/
#include "xparameters.h"
#include "xdpdma.h"
/*
* The configuration table for devices
*/
XDpDma_Config XDpDma_ConfigTable[XPAR_XDPDMA_NUM_INSTANCES] =
{
{
XPAR_PSU_DPDMA_DEVICE_ID,
XPAR_PSU_DPDMA_BASEADDR
}
};

1811
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/dpdma_v1_0/src/xdpdma_hw.h Normal file
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File diff suppressed because it is too large Load Diff

166
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/dpdma_v1_0/src/xdpdma_intr.c Normal file
View File

@ -0,0 +1,166 @@
/*******************************************************************************
*
* Copyright (C) 2017 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
*******************************************************************************/
/******************************************************************************/
/**
*
* @file xdppsu_intr.c
*
* This file contains functions related to XDpPsu interrupt handling.
*
* @note None.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.0 aad 01/17/17 Initial release.
* </pre>
*
*******************************************************************************/
/******************************* Include Files ********************************/
#include "xdpdma.h"
/*************************************************************************/
/**
*
* This function enables the interrupts that are required.
*
* @param InstancePtr is pointer to the instance of DPDMA
*
* @return None.
*
* @note None.
*
* **************************************************************************/
void XDpDma_InterruptEnable(XDpDma *InstancePtr, u32 Mask)
{
XDpDma_WriteReg(InstancePtr->Config.BaseAddr, XDPDMA_IEN, Mask);
}
/*************************************************************************/
/**
*
* This function handles the interrupts generated by DPDMA
*
* @param InstancePtr is pointer to the instance of the DPDMA
*
* @return None.
*
* @note None.
*
* **************************************************************************/
void XDpDma_InterruptHandler(XDpDma *InstancePtr)
{
u32 RegVal;
RegVal = XDpDma_ReadReg(InstancePtr->Config.BaseAddr,
XDPDMA_ISR);
if(RegVal & XDPDMA_ISR_VSYNC_INT_MASK) {
XDpDma_VSyncHandler(InstancePtr);
}
if(RegVal & XDPDMA_ISR_DSCR_DONE4_MASK) {
XDpDma_SetChannelState(InstancePtr, AudioChan0, XDPDMA_DISABLE);
InstancePtr->Audio[0].Current = NULL;
XDpDma_WriteReg(InstancePtr->Config.BaseAddr, XDPDMA_ISR,
XDPDMA_ISR_DSCR_DONE4_MASK);
}
if(RegVal & XDPDMA_ISR_DSCR_DONE5_MASK) {
XDpDma_SetChannelState(InstancePtr, AudioChan1, XDPDMA_DISABLE);
InstancePtr->Audio[1].Current = NULL;
XDpDma_WriteReg(InstancePtr->Config.BaseAddr, XDPDMA_ISR,
XDPDMA_ISR_DSCR_DONE5_MASK);
}
}
/*************************************************************************/
/**
*
* This function handles frame new frames on VSync
*
* @param InstancePtr is pointer to the instance of the driver.
*
* @return None.
*
* @note None.
*
* **************************************************************************/
void XDpDma_VSyncHandler(XDpDma *InstancePtr)
{
Xil_AssertVoid(InstancePtr != NULL);
/* Video Channel Trigger/Retrigger Handler */
if(InstancePtr->Video.TriggerStatus == XDPDMA_TRIGGER_EN) {
XDpDma_SetupChannel(InstancePtr, VideoChan);
XDpDma_SetChannelState(InstancePtr, VideoChan,
XDPDMA_ENABLE);
XDpDma_Trigger(InstancePtr, VideoChan);
}
else if(InstancePtr->Video.TriggerStatus == XDPDMA_RETRIGGER_EN) {
XDpDma_SetupChannel(InstancePtr, VideoChan);
XDpDma_ReTrigger(InstancePtr, VideoChan);
}
/* Graphics Channel Trigger/Retrigger Handler */
if(InstancePtr->Gfx.TriggerStatus == XDPDMA_TRIGGER_EN) {
XDpDma_SetupChannel(InstancePtr, GraphicsChan);
XDpDma_SetChannelState(InstancePtr, GraphicsChan,
XDPDMA_ENABLE);
XDpDma_Trigger(InstancePtr, GraphicsChan);
}
else if(InstancePtr->Gfx.TriggerStatus == XDPDMA_RETRIGGER_EN) {
XDpDma_SetupChannel(InstancePtr, GraphicsChan);
XDpDma_ReTrigger(InstancePtr, GraphicsChan);
}
/* Audio Channel 0 Trigger Handler */
if(InstancePtr->Audio[0].TriggerStatus == XDPDMA_TRIGGER_EN) {
XDpDma_SetupChannel(InstancePtr, AudioChan0);
XDpDma_SetChannelState(InstancePtr, AudioChan0,
XDPDMA_ENABLE);
XDpDma_Trigger(InstancePtr, AudioChan0);
}
/* Audio Channel 1 Trigger Handler */
if(InstancePtr->Audio[1].TriggerStatus == XDPDMA_TRIGGER_EN) {
XDpDma_SetupChannel(InstancePtr, AudioChan1);
XDpDma_SetChannelState(InstancePtr, AudioChan1,
XDPDMA_ENABLE);
XDpDma_Trigger(InstancePtr, AudioChan1);
}
/* Clear VSync Interrupt */
XDpDma_WriteReg(InstancePtr->Config.BaseAddr, XDPDMA_ISR,
XDPDMA_ISR_VSYNC_INT_MASK);
}

96
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/dpdma_v1_0/src/xdpdma_sinit.c Normal file
View File

@ -0,0 +1,96 @@
/*******************************************************************************
*
* Copyright (C) 2017 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
*******************************************************************************/
/******************************************************************************/
/**
*
* @file xdpdma_sinit.c
* @addtogroup dpdma_v1_0
* @{
*
* This file contains static initialization methods for the XDpDma driver.
*
* @note None.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.0 aad 01/20/15 Initial release.
* </pre>
*
*******************************************************************************/
/******************************* Include Files ********************************/
#include "xdpdma.h"
#include "xparameters.h"
/*************************** Variable Declarations ****************************/
/**
* A table of configuration structures containing the configuration information
* for each DisplayPort TX core in the system.
*/
extern XDpDma_Config XDpDma_ConfigTable[XPAR_XDPDMA_NUM_INSTANCES];
/**************************** Function Definitions ****************************/
/******************************************************************************/
/**
* This function looks for the device configuration based on the unique device
* ID. The table XDpDma_ConfigTable[] contains the configuration information for
* each device in the system.
*
* @param DeviceId is the unique device ID of the device being looked up.
*
* @return A pointer to the configuration table entry corresponding to the
* given device ID, or NULL if no match is found.
*
* @note None.
*
*******************************************************************************/
XDpDma_Config *XDpDma_LookupConfig(u16 DeviceId)
{
XDpDma_Config *CfgPtr;
u32 Index;
for (Index = 0; Index < XPAR_XDPDMA_NUM_INSTANCES; Index++) {
if (XDpDma_ConfigTable[Index].DeviceId == DeviceId) {
CfgPtr = &XDpDma_ConfigTable[Index];
break;
}
}
return CfgPtr;
}
/** @} */

0
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_3/src/Makefile → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/Makefile
View File

5
FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_2/src/xemacps.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps.c
View File

@ -33,7 +33,7 @@
/**
*
* @file xemacps.c
* @addtogroup emacps_v3_1
* @addtogroup emacps_v3_7
* @{
*
* The XEmacPs driver. Functions in this file are the minimum required functions
@ -52,6 +52,8 @@
* Disable extended mode. Perform all 64 bit changes under
* check for arch64.
* 3.1 hk 08/10/15 Update upper 32 bit tx and rx queue ptr registers
* 3.5 hk 08/14/17 Update cache coherency information of the interface in
* its config structure.
*
* </pre>
******************************************************************************/
@ -107,6 +109,7 @@ LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config * CfgPtr,
/* Set device base address and ID */
InstancePtr->Config.DeviceId = CfgPtr->DeviceId;
InstancePtr->Config.BaseAddress = EffectiveAddress;
InstancePtr->Config.IsCacheCoherent = CfgPtr->IsCacheCoherent;
/* Set callbacks to an initial stub routine */
InstancePtr->SendHandler = ((XEmacPs_Handler)((void*)XEmacPs_StubHandler));

19
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_3/src/xemacps.h → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps.h
View File

@ -33,7 +33,7 @@
/**
*
* @file xemacps.h
* @addtogroup emacps_v3_1
* @addtogroup emacps_v3_7
* @{
* @details
*
@ -316,6 +316,21 @@
* there is no error. CR# 869403
* 08/10/15 Update upper 32 bit tx and rx queue ptr registers.
* 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
* 3.4 ms 01/23/17 Modified xil_printf statement in main function for all
* examples to ensure that "Successfully ran" and "Failed"
* strings are available in all examples. This is a fix
* for CR-965028.
* ms 03/17/17 Modified text file in examples folder for doxygen
* generation.
* ms 04/05/17 Added tabspace for return statements in functions of
* xemacps_ieee1588_example.c for proper documentation
* while generating doxygen.
* 3.5 hk 08/14/17 Update cache coherency information of the interface in
* its config structure.
* 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
* changed to volatile.
* Add API XEmacPs_BdRingPtrReset() to reset pointers
*
* </pre>
*
****************************************************************************/
@ -513,6 +528,8 @@ typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
typedef struct {
u16 DeviceId; /**< Unique ID of device */
UINTPTR BaseAddress;/**< Physical base address of IPIF registers */
u8 IsCacheCoherent; /**< Applicable only to A53 in EL1 mode;
* describes whether Cache Coherent or not */
} XEmacPs_Config;

2
FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_2/src/xemacps_bd.h → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps_bd.h
View File

@ -33,7 +33,7 @@
/**
*
* @file xemacps_bd.h
* @addtogroup emacps_v3_1
* @addtogroup emacps_v3_7
* @{
*
* This header provides operations to manage buffer descriptors in support

31
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_3/src/xemacps_bdring.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps_bdring.c
View File

@ -33,7 +33,7 @@
/**
*
* @file xemacps_bdring.c
* @addtogroup emacps_v3_1
* @addtogroup emacps_v3_7
* @{
*
* This file implements buffer descriptor ring related functions.
@ -57,6 +57,8 @@
* from uncached area. Fix for CR #663885.
* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.6 rb 09/08/17 Add XEmacPs_BdRingPtrReset() API to reset BD ring
* pointers
*
* </pre>
******************************************************************************/
@ -505,7 +507,7 @@ LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
XEmacPs_Bd * BdSetPtr)
{
LONG Status;
(void *)BdSetPtr;
(void) BdSetPtr;
Xil_AssertNonvoid(RingPtr != NULL);
Xil_AssertNonvoid(BdSetPtr != NULL);
@ -1072,4 +1074,29 @@ static void XEmacPs_BdSetTxWrap(UINTPTR BdPtr)
*TempPtr = DataValueTx;
}
}
/*****************************************************************************/
/**
* Reset BD ring head and tail pointers.
*
* @param RingPtr is the instance to be worked on.
* @param VirtAddr is the virtual base address of the user memory region.
*
* @note
* Should be called after XEmacPs_Stop()
*
* @note
* C-style signature:
* void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc)
*
*****************************************************************************/
void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc)
{
RingPtr->FreeHead = virtaddrloc;
RingPtr->PreHead = virtaddrloc;
RingPtr->HwHead = virtaddrloc;
RingPtr->HwTail = virtaddrloc;
RingPtr->PostHead = virtaddrloc;
}
/** @} */

7
FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_bdring.h → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps_bdring.h
View File

@ -33,7 +33,7 @@
/**
*
* @file xemacps_bdring.h
* @addtogroup emacps_v3_1
* @addtogroup emacps_v3_7
* @{
*
* The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs
@ -47,6 +47,8 @@
* 1.00a wsy 01/10/10 First release
* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
* changed to volatile.
*
* </pre>
*
@ -81,7 +83,7 @@ typedef struct {
XEmacPs_Bd *BdaRestart;
/**< BDA to load when channel is started */
u32 HwCnt; /**< Number of BDs in work group */
volatile u32 HwCnt; /**< Number of BDs in work group */
u32 PreCnt; /**< Number of BDs in pre-work group */
u32 FreeCnt; /**< Number of allocatable BDs in the free group */
u32 PostCnt; /**< Number of BDs in post-work group */
@ -228,6 +230,7 @@ u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
XEmacPs_Bd ** BdSetPtr);
LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction);
void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc);
#ifdef __cplusplus
}

2
FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_control.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps_control.c
View File

@ -33,7 +33,7 @@
/**
*
* @file xemacps_control.c
* @addtogroup emacps_v3_1
* @addtogroup emacps_v3_7
* @{
*
* Functions in this file implement general purpose command and control related

7
FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_g.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps_g.c
View File

@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
@ -44,11 +44,12 @@
* The configuration table for devices
*/
XEmacPs_Config XEmacPs_ConfigTable[] =
XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES] =
{
{
XPAR_PSU_ETHERNET_3_DEVICE_ID,
XPAR_PSU_ETHERNET_3_BASEADDR
XPAR_PSU_ETHERNET_3_BASEADDR,
XPAR_PSU_ETHERNET_3_IS_CACHE_COHERENT
}
};

2
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_3/src/xemacps_hw.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps_hw.c
View File

@ -33,7 +33,7 @@
/**
*
* @file xemacps_hw.c
* @addtogroup emacps_v3_1
* @addtogroup emacps_v3_7
* @{
*
* This file contains the implementation of the ethernet interface reset sequence

2
FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_hw.h → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps_hw.h
View File

@ -33,7 +33,7 @@
/**
*
* @file xemacps_hw.h
* @addtogroup emacps_v3_1
* @addtogroup emacps_v3_7
* @{
*
* This header file contains identifiers and low-level driver functions (or

2
FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_2/src/xemacps_intr.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps_intr.c
View File

@ -33,7 +33,7 @@
/**
*
* @file xemacps_intr.c
* @addtogroup emacps_v3_1
* @addtogroup emacps_v3_7
* @{
*
* Functions in this file implement general purpose interrupt processing related

2
FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_sinit.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps_sinit.c
View File

@ -33,7 +33,7 @@
/**
*
* @file xemacps_sinit.c
* @addtogroup emacps_v3_1
* @addtogroup emacps_v3_7
* @{
*
* This file contains lookup method by device ID when success, it returns

0
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_1/src/Makefile → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_3/src/Makefile
View File

2
FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_3/src/xgpiops.c
View File

@ -33,7 +33,7 @@
/**
*
* @file xgpiops.c
* @addtogroup gpiops_v3_1
* @addtogroup gpiops_v3_3
* @{
*
* The XGpioPs driver. Functions in this file are the minimum required functions

13
FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops.h → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_3/src/xgpiops.h
View File

@ -1,3 +1,4 @@
/******************************************************************************
*
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
@ -33,7 +34,7 @@
/**
*
* @file xgpiops.h
* @addtogroup gpiops_v3_1
* @addtogroup gpiops_v3_3
* @{
* @details
*
@ -97,7 +98,15 @@
* passed to APIs. CR# 822636
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
*
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
* ms 04/05/17 Added tabspace for return statements in functions of
* gpiops examples for proper documentation while
* generating doxygen.
* 3.3 ms 04/17/17 Added notes about gpio input and output pin description
* for zcu102 and zc702 boards in polled and interrupt
* example, configured Interrupt pin to input pin for
* proper functioning of interrupt example.
* </pre>
*
******************************************************************************/

4
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_1/src/xgpiops_g.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_3/src/xgpiops_g.c
View File

@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
@ -44,7 +44,7 @@
* The configuration table for devices
*/
XGpioPs_Config XGpioPs_ConfigTable[] =
XGpioPs_Config XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES] =
{
{
XPAR_PSU_GPIO_0_DEVICE_ID,

2
FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_hw.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_3/src/xgpiops_hw.c
View File

@ -33,7 +33,7 @@
/**
*
* @file xgpiops_hw.c
* @addtogroup gpiops_v3_1
* @addtogroup gpiops_v3_3
* @{
*
* This file contains low level GPIO functions.

2
FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_hw.h → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_3/src/xgpiops_hw.h
View File

@ -33,7 +33,7 @@
/**
*
* @file xgpiops_hw.h
* @addtogroup gpiops_v3_1
* @addtogroup gpiops_v3_3
* @{
*
* This header file contains the identifiers and basic driver functions (or

4
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_1/src/xgpiops_intr.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_3/src/xgpiops_intr.c
View File

@ -33,7 +33,7 @@
/**
*
* @file xgpiops_intr.c
* @addtogroup gpiops_v3_1
* @addtogroup gpiops_v3_3
* @{
*
* This file contains functions related to GPIO interrupt handling.
@ -722,7 +722,7 @@ void XGpioPs_IntrHandler(XGpioPs *InstancePtr)
******************************************************************************/
void StubHandler(void *CallBackRef, u32 Bank, u32 Status)
{
(void*) CallBackRef;
(void) CallBackRef;
(void) Bank;
(void) Status;

2
FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_selftest.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_3/src/xgpiops_selftest.c
View File

@ -33,7 +33,7 @@
/**
*
* @file xgpiops_selftest.c
* @addtogroup gpiops_v3_1
* @addtogroup gpiops_v3_3
* @{
*
* This file contains a diagnostic self-test function for the XGpioPs driver.

2
FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_sinit.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_3/src/xgpiops_sinit.c
View File

@ -33,7 +33,7 @@
/**
*
* @file xgpiops_sinit.c
* @addtogroup gpiops_v3_1
* @addtogroup gpiops_v3_3
* @{
*
* This file contains the implementation of the XGpioPs driver's static

0
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/Makefile → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/Makefile
View File

2
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/xiicps.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps.c
View File

@ -33,7 +33,7 @@
/**
*
* @file xiicps.c
* @addtogroup iicps_v3_0
* @addtogroup iicps_v3_5
* @{
*
* Contains implementation of required functions for the XIicPs driver.

4
FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps.h → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps.h
View File

@ -33,7 +33,7 @@
/**
*
* @file xiicps.h
* @addtogroup iicps_v3_0
* @addtogroup iicps_v3_5
* @{
* @details
*
@ -184,6 +184,8 @@
* 02/18/15 Implemented larger data transfer using repeated start
* in Zynq UltraScale MP.
* 3.3 kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
*
* </pre>
*

4
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/xiicps_g.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps_g.c
View File

@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
@ -44,7 +44,7 @@
* The configuration table for devices
*/
XIicPs_Config XIicPs_ConfigTable[] =
XIicPs_Config XIicPs_ConfigTable[XPAR_XIICPS_NUM_INSTANCES] =
{
{
XPAR_PSU_I2C_0_DEVICE_ID,

2
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/xiicps_hw.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps_hw.c
View File

@ -33,7 +33,7 @@
/**
*
* @file xiicps_hw.c
* @addtogroup iicps_v3_0
* @addtogroup iicps_v3_5
* @{
*
* Contains implementation of required functions for providing the reset sequence

2
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/xiicps_hw.h → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps_hw.h
View File

@ -33,7 +33,7 @@
/**
*
* @file xiicps_hw.h
* @addtogroup iicps_v3_0
* @addtogroup iicps_v3_5
* @{
*
* This header file contains the hardware definition for an IIC device.

2
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/xiicps_intr.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps_intr.c
View File

@ -33,7 +33,7 @@
/**
*
* @file xiicps_intr.c
* @addtogroup iicps_v3_0
* @addtogroup iicps_v3_5
* @{
*
* Contains functions of the XIicPs driver for interrupt-driven transfers.

14
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/xiicps_master.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps_master.c
View File

@ -33,7 +33,7 @@
/**
*
* @file xiicps_master.c
* @addtogroup iicps_v3_0
* @addtogroup iicps_v3_5
* @{
*
* Handles master mode transfers.
@ -63,7 +63,8 @@
* 02/18/15 Implemented larger data transfer using repeated start
* in Zynq UltraScale MP.
* 3.3 kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
*
* 3.6 ask 09/03/18 In XIicPs_MasterRecvPolled, set transfer size register
* before slave address. Fix for CR996440.
* </pre>
*
******************************************************************************/
@ -424,7 +425,6 @@ s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr,
IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
/*
* Set up the transfer size register so the slave knows how much
@ -440,6 +440,9 @@ s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr,
ByteCountVar);
}
XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
/*
* Intrs keeps all the error-related interrupts.
*/
@ -632,6 +635,11 @@ void XIicPs_DisableSlaveMonitor(XIicPs *InstancePtr)
XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET)
& (~XIICPS_CR_SLVMON_MASK));
/*
* wait for slv monitor control bit to be clear
*/
while (XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET)
& XIICPS_CR_SLVMON_MASK);
/*
* Clear interrupt flag for slave monitor interrupt.
*/

2
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/xiicps_options.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps_options.c
View File

@ -33,7 +33,7 @@
/**
*
* @file xiicps_options.c
* @addtogroup iicps_v3_0
* @addtogroup iicps_v3_5
* @{
*
* Contains functions for the configuration of the XIccPs driver.

2
FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_selftest.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps_selftest.c
View File

@ -33,7 +33,7 @@
/**
*
* @file xiicps_selftest.c
* @addtogroup iicps_v3_0
* @addtogroup iicps_v3_5
* @{
*
* This component contains the implementation of selftest functions for the

2
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/xiicps_sinit.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps_sinit.c
View File

@ -33,7 +33,7 @@
/**
*
* @file xiicps_sinit.c
* @addtogroup iicps_v3_0
* @addtogroup iicps_v3_5
* @{
*
* The implementation of the XIicPs component's static initialization

2
FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_slave.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps_slave.c
View File

@ -32,7 +32,7 @@
/*****************************************************************************/
/**
* @file xiicps_slave.c
* @addtogroup iicps_v3_0
* @addtogroup iicps_v3_5
* @{
*
* Handles slave transfers

0
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_1/src/Makefile → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_3/src/Makefile
View File

41
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_1/src/xipipsu.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_3/src/xipipsu.c
View File

@ -33,7 +33,7 @@
/**
*
* @file xipipsu.c
* @addtogroup ipipsu_v1_0
* @addtogroup ipipsu_v2_3
* @{
*
* This file contains the implementation of the interface functions for XIpiPsu
@ -48,6 +48,7 @@
* 2.0 mjr 01/22/16 Fixed response buffer address
* calculation. CR# 932582.
* 2.1 kvn 05/05/16 Modified code for MISRA-C:2012 Compliance
* 2.2 kvn 02/17/17 Add support for updating ConfigTable at run time
* </pre>
*
*****************************************************************************/
@ -56,6 +57,9 @@
#include "xipipsu.h"
#include "xipipsu_hw.h"
/************************** Variable Definitions *****************************/
extern XIpiPsu_Config XIpiPsu_ConfigTable[XPAR_XIPIPSU_NUM_INSTANCES];
/****************************************************************************/
/**
* Initialize the Instance pointer based on a given Config Pointer
@ -350,4 +354,39 @@ XStatus XIpiPsu_WriteMessage(XIpiPsu *InstancePtr, u32 DestCpuMask, u32 *MsgPtr,
return Status;
}
/*****************************************************************************/
/**
*
* Set up the device configuration based on the unique device ID. A table
* contains the configuration info for each device in the system.
*
* @param DeviceId contains the ID of the device to set up the
* configuration for.
*
* @return A pointer to the device configuration for the specified
* device ID. See xipipsu.h for the definition of
* XIpiPsu_Config.
*
* @note This is for safety use case where in this function has to
* be called before CfgInitialize. So that driver will be
* initialized with the provided configuration. For non-safe
* use cases, this is not needed.
*
******************************************************************************/
void XIpiPsu_SetConfigTable(u32 DeviceId, XIpiPsu_Config *ConfigTblPtr)
{
u32 Index;
Xil_AssertVoid(ConfigTblPtr != NULL);
for (Index = 0U; Index < XPAR_XIPIPSU_NUM_INSTANCES; Index++) {
if (XIpiPsu_ConfigTable[Index].DeviceId == DeviceId) {
XIpiPsu_ConfigTable[Index].BaseAddress = ConfigTblPtr->BaseAddress;
XIpiPsu_ConfigTable[Index].BitMask = ConfigTblPtr->BitMask;
XIpiPsu_ConfigTable[Index].BufferIndex = ConfigTblPtr->BufferIndex;
XIpiPsu_ConfigTable[Index].IntId = ConfigTblPtr->IntId;
}
}
}
/** @} */

21
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_1/src/xipipsu.h → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_3/src/xipipsu.h
View File

@ -32,7 +32,7 @@
/*****************************************************************************/
/**
* @file xipipsu.h
* @addtogroup ipipsu_v1_0
* @addtogroup ipipsu_v2_3
* @{
* @details
*
@ -76,7 +76,23 @@
* @note XIpiPsu_Reset can be used at startup to clear the status and
* disable all sources
*
*/
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ---- --- -------- --------------------------------------------------
* 2.2 ms 01/23/17 Modified xil_printf statement in main function for all
* examples to ensure that "Successfully ran" and "Failed"
* strings are available in all examples. This is a fix
* for CR-965028.
* kvn 02/17/17 Add support for updating ConfigTable at run time
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
* 2.3 ms 04/11/17 Modified tcl file to add suffix U for all macro
* definitions of ipipsu in xparameters.h
* </pre>
*
*****************************************************************************/
/*****************************************************************************/
#ifndef XIPIPSU_H_
#define XIPIPSU_H_
@ -276,6 +292,7 @@ XStatus XIpiPsu_ReadMessage(XIpiPsu *InstancePtr, u32 SrcCpuMask, u32 *MsgPtr,
XStatus XIpiPsu_WriteMessage(XIpiPsu *InstancePtr, u32 DestCpuMask, u32 *MsgPtr,
u32 MsgLength, u8 BufferType);
void XIpiPsu_SetConfigTable(u32 DeviceId, XIpiPsu_Config *ConfigTblPtr);
#endif /* XIPIPSU_H_ */
/** @} */

20
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_1/src/xipipsu_g.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_3/src/xipipsu_g.c
View File

@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
@ -44,7 +44,7 @@
* The configuration table for devices
*/
XIpiPsu_Config XIpiPsu_ConfigTable[] =
XIpiPsu_Config XIpiPsu_ConfigTable[XPAR_XIPIPSU_NUM_INSTANCES] =
{
{
@ -83,22 +83,6 @@ XIpiPsu_Config XIpiPsu_ConfigTable[] =
{
XPAR_PSU_IPI_6_BIT_MASK,
XPAR_PSU_IPI_6_BUFFER_INDEX
},
{
XPAR_PSU_IPI_7_BIT_MASK,
XPAR_PSU_IPI_7_BUFFER_INDEX
},
{
XPAR_PSU_IPI_8_BIT_MASK,
XPAR_PSU_IPI_8_BUFFER_INDEX
},
{
XPAR_PSU_IPI_9_BIT_MASK,
XPAR_PSU_IPI_9_BUFFER_INDEX
},
{
XPAR_PSU_IPI_10_BIT_MASK,
XPAR_PSU_IPI_10_BUFFER_INDEX
}
}
}

6
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_1/src/xipipsu_hw.h → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_3/src/xipipsu_hw.h
View File

@ -32,7 +32,7 @@
/**
*
* @file xipipsu_hw.h
* @addtogroup ipipsu_v1_0
* @addtogroup ipipsu_v2_3
* @{
*
* This file contains macro definitions for low level HW related params
@ -62,8 +62,8 @@
#define XIPIPSU_BUFFER_OFFSET_TARGET (32U * 2U)
#define XIPIPSU_BUFFER_OFFSET_RESPONSE (32U)
/* Max Number of IPI slots on the device */
#define XIPIPSU_MAX_TARGETS 11
/* Number of IPI slots enabled on the device */
#define XIPIPSU_MAX_TARGETS XPAR_XIPIPSU_NUM_TARGETS
/* Register Offsets for each member of IPI Register Set */
#define XIPIPSU_TRIG_OFFSET 0x00U

2
FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu_sinit.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_3/src/xipipsu_sinit.c
View File

@ -32,7 +32,7 @@
/**
*
* @file xipipsu_sinit.c
* @addtogroup ipipsu_v1_0
* @addtogroup ipipsu_v2_3
* @{
*
* The implementation of the XIpiPsu component's static initialization

0
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_3/src/Makefile → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_7/src/Makefile
View File

62
FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_7/src/xqspipsu.c
View File

@ -33,7 +33,7 @@
/**
*
* @file xqspipsu.c
* @addtogroup qspipsu_v1_0
* @addtogroup qspipsu_v1_7
* @{
*
* This file implements the functions required to use the QSPIPSU hardware to
@ -60,6 +60,10 @@
* 1.3 nsk 09/16/16 Update PollData and PollTimeout support for dual
* parallel configurations, modified XQspiPsu_PollData()
* and XQspiPsu_Create_PollConfigData()
* 1,5 nsk 08/14/17 Added CCI support
* 1.7 tjs 01/16/18 Removed the check for DMA MSB to be written. (CR#992560)
* 1.7 tjs 01/17/18 Added a support to toggle WP pin of the flash.
* 1.7 tjs 03/14/18 Added support in EL1 NS mode (CR#974882)
*
* </pre>
*
@ -150,6 +154,7 @@ s32 XQspiPsu_CfgInitialize(XQspiPsu *InstancePtr, XQspiPsu_Config *ConfigPtr,
InstancePtr->StatusHandler = StubStatusHandler;
InstancePtr->Config.BusWidth = ConfigPtr->BusWidth;
InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
InstancePtr->Config.IsCacheCoherent = ConfigPtr->IsCacheCoherent;
/* Other instance variable initializations */
InstancePtr->SendBufferPtr = NULL;
InstancePtr->RecvBufferPtr = NULL;
@ -928,7 +933,7 @@ void XQspiPsu_SetStatusHandler(XQspiPsu *InstancePtr, void *CallBackRef,
static void StubStatusHandler(void *CallBackRef, u32 StatusEvent,
u32 ByteCount)
{
(void *) CallBackRef;
(void) CallBackRef;
(void) StatusEvent;
(void) ByteCount;
@ -1136,13 +1141,13 @@ static inline void XQspiPsu_SetupRxDma(XQspiPsu *InstancePtr,
XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET,
(u32)AddrTemp);
AddrTemp = AddrTemp >> 32;
if ((AddrTemp & 0xFFFU) != FALSE) {
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET,
(u32)AddrTemp &
XQSPIPSU_QSPIDMA_DST_ADDR_MSB_MASK);
}
#ifdef __aarch64__
AddrTemp = (u64)((INTPTR)(Msg->RxBfrPtr) >> 32);
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET,
(u32)AddrTemp &
XQSPIPSU_QSPIDMA_DST_ADDR_MSB_MASK);
#endif
Remainder = InstancePtr->RxBytes % 4;
DmaRxBytes = InstancePtr->RxBytes;
@ -1151,8 +1156,10 @@ static inline void XQspiPsu_SetupRxDma(XQspiPsu *InstancePtr,
DmaRxBytes = InstancePtr->RxBytes - Remainder;
Msg->ByteCount = (u32)DmaRxBytes;
}
Xil_DCacheInvalidateRange((INTPTR)InstancePtr->RecvBufferPtr, Msg->ByteCount);
if (InstancePtr->Config.IsCacheCoherent == 0) {
Xil_DCacheInvalidateRange((INTPTR)InstancePtr->RecvBufferPtr,
Msg->ByteCount);
}
/* Write no. of words to DMA DST SIZE */
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
@ -1511,4 +1518,37 @@ static inline u32 XQspiPsu_Create_PollConfigData(XQspiPsu *QspiPsuPtr,
& XQSPIPSU_POLL_CFG_DATA_VALUE_MASK);
return ConfigData;
}
/*****************************************************************************/
/**
* @brief
* This API enables/ disables Write Protect pin on the flash parts.
*
* @param QspiPtr is a pointer to the QSPIPSU driver component to use.
*
* @return None
*
* @note By default WP pin as per the QSPI controller is driven High
* which means no write protection. Calling this function once
* will enable the protection.
*
******************************************************************************/
void XQspiPsu_WriteProtectToggle(XQspiPsu *QspiPsuPtr, u32 Toggle)
{
/* For Single and Stacked flash configuration with x1 or x2 mode*/
if (QspiPsuPtr->Config.ConnectionMode == XQSPIPSU_CONNECTION_MODE_SINGLE) {
/* Enable */
XQspiPsu_Enable(QspiPsuPtr);
/* Select slave */
XQspiPsu_GenFifoEntryCSAssert(QspiPsuPtr);
XQspiPsu_WriteReg(QspiPsuPtr->Config.BaseAddress, XQSPIPSU_GPIO_OFFSET,
Toggle);
} else if (QspiPsuPtr->Config.ConnectionMode == XQSPIPSU_CONNECTION_MODE_PARALLEL ||
QspiPsuPtr->Config.ConnectionMode == XQSPIPSU_CONNECTION_MODE_STACKED) {
xil_printf("Dual Parallel/Stacked configuration is not supported by this API\r\n");
}
}
/** @} */

39
FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu.h → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_7/src/xqspipsu.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -33,7 +33,7 @@
/**
*
* @file xqspipsu.h
* @addtogroup qspipsu_v1_0
* @addtogroup qspipsu_v1_7
* @{
* @details
*
@ -112,7 +112,33 @@
* configuration. Updated XQspiPsu_PollData() and
* XQspiPsu_Create_PollConfigData() functions in xqspipsu.c
* and also modified the polldata example
*
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
* ms 04/05/17 Modified Comment lines in functions of qspipsu
* examples to recognize it as documentation block
* and modified filename tag to include them in
* doxygen examples.
* 1.4 tjs 05/26/17 Added support for accessing upper DDR (0x800000000)
* while booting images from QSPI
* 1.5 tjs 08/08/17 Added index.html file for importing examples from system.mss
* 1.5 nsk 08/14/17 Added CCI support
* 1.5 tjs 09/14/17 Modified the checks for 4 byte addressing and commands.
* 1.6 tjs 10/16/17 Flow for accessing flash is made similar to u-boot and linux
* For CR-984966
* 1.6 tjs 11/02/17 Resolved the compilation errors for ICCARM. CR-988625
* 1.7 tjs 11/16/17 Removed the unsupported 4 Byte write and sector erase
* commands.
* 1.7 tjs 12/01/17 Added support for MT25QL02G Flash from Micron. CR-990642
* 1.7 tjs 12/19/17 Added support for S25FL064L from Spansion. CR-990724
* 1.7 tjs 01/11/18 Added support for MX66L1G45G flash from Macronix CR-992367
* 1.7 tjs 01/16/18 Removed the check for DMA MSB to be written. (CR#992560)
* 1.7 tjs 01/17/18 Added support to toggle the WP pin of flash. (PR#2448)
* Added XQspiPsu_SetWP() in xqspipsu_options.c
* Added XQspiPsu_WriteProtectToggle() in xqspipsu.c and
* also added write protect example.
* 1.7 tjs 03/14/18 Added support in EL1 NS mode (CR#974882)
* 1.7 tjs 26/03/18 In dual parallel mode enable both CS when issuing Write
* enable command. CR-998478
* </pre>
*
******************************************************************************/
@ -175,6 +201,7 @@ typedef struct {
u32 InputClockHz; /**< Input clock frequency */
u8 ConnectionMode; /**< Single, Stacked and Parallel mode */
u8 BusWidth; /**< Bus width available on board */
u8 IsCacheCoherent; /**< Describes whether Cache Coherent or not */
} XQspiPsu_Config;
/**
@ -259,6 +286,9 @@ typedef struct {
#define XQSPIPSU_MSG_FLAG_TX 0x4U
#define XQSPIPSU_MSG_FLAG_POLL 0x8U
/* GQSPI configuration to toggle WP of flash*/
#define XQSPIPSU_SET_WP 1
#define XQspiPsu_Select(InstancePtr, Mask) XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + XQSPIPSU_SEL_OFFSET, Mask)
#define XQspiPsu_Enable(InstancePtr) XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + XQSPIPSU_EN_OFFSET, XQSPIPSU_EN_MASK)
@ -267,6 +297,7 @@ typedef struct {
#define XQspiPsu_GetLqspiConfigReg(InstancePtr) XQspiPsu_In32((XQSPIPS_BASEADDR) + XQSPIPSU_LQSPI_CR_OFFSET)
/************************** Function Prototypes ******************************/
/* Initialization and reset */
@ -292,6 +323,8 @@ s32 XQspiPsu_SetOptions(XQspiPsu *InstancePtr, u32 Options);
s32 XQspiPsu_ClearOptions(XQspiPsu *InstancePtr, u32 Options);
u32 XQspiPsu_GetOptions(XQspiPsu *InstancePtr);
s32 XQspiPsu_SetReadMode(XQspiPsu *InstancePtr, u32 Mode);
void XQspiPsu_SetWP(XQspiPsu *InstancePtr, u8 Value);
void XQspiPsu_WriteProtectToggle(XQspiPsu *InstancePtr, u32 Toggle);
#ifdef __cplusplus
}

7
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_3/src/xqspipsu_g.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_7/src/xqspipsu_g.c
View File

@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
@ -44,14 +44,15 @@
* The configuration table for devices
*/
XQspiPsu_Config XQspiPsu_ConfigTable[] =
XQspiPsu_Config XQspiPsu_ConfigTable[XPAR_XQSPIPSU_NUM_INSTANCES] =
{
{
XPAR_PSU_QSPI_0_DEVICE_ID,
XPAR_PSU_QSPI_0_BASEADDR,
XPAR_PSU_QSPI_0_QSPI_CLK_FREQ_HZ,
XPAR_PSU_QSPI_0_QSPI_MODE,
XPAR_PSU_QSPI_0_QSPI_BUS_WIDTH
XPAR_PSU_QSPI_0_QSPI_BUS_WIDTH,
XPAR_PSU_QSPI_0_IS_CACHE_COHERENT
}
};

5
FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_hw.h → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_7/src/xqspipsu_hw.h
View File

@ -33,7 +33,7 @@
/**
*
* @file xqspipsu_hw.h
* @addtogroup qspipsu_v1_0
* @addtogroup qspipsu_v1_7
* @{
*
* This file contains low level access funcitons using the base address
@ -49,6 +49,7 @@
* sk 04/24/15 Modified the code according to MISRAC-2012.
* 1.2 nsk 07/01/16 Added LQSPI supported Masks
* rk 07/15/16 Added support for TapDelays at different frequencies.
* 1.7 tjs 03/14/18 Added support in EL1 NS mode.
*
* </pre>
*
@ -147,6 +148,7 @@ extern "C" {
or quad I/O */
#define XQSPIPS_LQSPI_CR_INST_MASK 0x000000FF /**< Read instr code */
#define XQSPIPS_LQSPI_CR_RST_STATE 0x80000003 /**< Default LQSPI CR value */
#define XQSPIPS_LQSPI_CR_4_BYTE_STATE 0x88000013 /**< Default 4 Byte LQSPI CR value */
#define XQSPIPS_LQSPI_CFG_RST_STATE 0x800238C1 /**< Default LQSPI CFG value */
/**
* Register: XQSPIPSU_ISR
@ -828,6 +830,7 @@ extern "C" {
#define IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT 0X02
#define IOU_TAPDLY_BYPASS_LQSPI_RX_WIDTH 0X01
#define IOU_TAPDLY_BYPASS_LQSPI_RX_MASK 0x00000004
#define IOU_TAPDLY_RESET_STATE 0x7
/***************** Macros (Inline Functions) Definitions *********************/

51
FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_options.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_7/src/xqspipsu_options.c
View File

@ -33,7 +33,7 @@
/**
*
* @file xqspipsu_options.c
* @addtogroup qspipsu_v1_0
* @addtogroup qspipsu_v1_7
* @{
*
* This file implements funcitons to configure the QSPIPSU component,
@ -51,6 +51,8 @@
* 1.2 nsk 07/01/16 Modified XQspiPsu_SetOptions() to support
* LQSPI options and updated OptionsTable
* rk 07/15/16 Added support for TapDelays at different frequencies.
* 1.7 tjs 01/17/18 Added support to toggle the WP pin of flash. (PR#2448)
* 1.7 tjs 03/14/18 Added support in EL1 NS mode. (CR#974882)
*
* </pre>
*
@ -59,6 +61,9 @@
/***************************** Include Files *********************************/
#include "xqspipsu.h"
#if defined (__aarch64__)
#include "xil_smc.h"
#endif
/************************** Constant Definitions *****************************/
@ -179,7 +184,7 @@ s32 XQspiPsu_SetOptions(XQspiPsu *InstancePtr, u32 Options)
ConfigReg = XQspiPsu_ReadReg(XQSPIPS_BASEADDR,XQSPIPSU_LQSPI_CR_OFFSET);
if (QspiPsuOptions & XQSPIPSU_LQSPI_MODE_OPTION) {
XQspiPsu_WriteReg(XQSPIPS_BASEADDR,XQSPIPSU_LQSPI_CR_OFFSET,XQSPIPS_LQSPI_CR_RST_STATE);
XQspiPsu_WriteReg(XQSPIPS_BASEADDR,XQSPIPSU_LQSPI_CR_OFFSET,XQSPIPS_LQSPI_CR_4_BYTE_STATE);
XQspiPsu_WriteReg(XQSPIPS_BASEADDR,XQSPIPSU_CFG_OFFSET,XQSPIPS_LQSPI_CFG_RST_STATE);
/* Enable the QSPI controller */
XQspiPsu_WriteReg(XQSPIPS_BASEADDR,XQSPIPSU_EN_OFFSET,XQSPIPSU_EN_MASK);
@ -344,8 +349,15 @@ s32 XQspi_Set_TapDelay(XQspiPsu * InstancePtr,u32 TapdelayBypass,
if (InstancePtr->IsBusy == TRUE) {
Status = XST_DEVICE_BUSY;
} else {
#if EL1_NONSECURE && defined (__aarch64__)
Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
IOU_TAPDLY_BYPASS_OFFSET) |
((u64)(0x4) << 32),
(u64)TapdelayBypass, 0, 0, 0, 0, 0);
#else
XQspiPsu_WriteReg(XPS_SYS_CTRL_BASEADDR,IOU_TAPDLY_BYPASS_OFFSET,
TapdelayBypass);
#endif
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_LPBK_DLY_ADJ_OFFSET,LPBKDelay);
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
@ -380,8 +392,12 @@ static s32 XQspipsu_Calculate_Tapdelay(XQspiPsu *InstancePtr, u8 Prescaler)
Divider = (1 << (Prescaler+1));
FreqDiv = (InstancePtr->Config.InputClockHz)/Divider;
#if EL1_NONSECURE && defined (__aarch64__)
Tapdelay = IOU_TAPDLY_RESET_STATE;
#else
Tapdelay = XQspiPsu_ReadReg(XPS_SYS_CTRL_BASEADDR,
IOU_TAPDLY_BYPASS_OFFSET);
IOU_TAPDLY_BYPASS_OFFSET);
#endif
Tapdelay = Tapdelay & (~IOU_TAPDLY_BYPASS_LQSPI_RX_MASK);
@ -618,4 +634,33 @@ s32 XQspiPsu_SetReadMode(XQspiPsu *InstancePtr, u32 Mode)
#endif
return Status;
}
/*****************************************************************************/
/**
*
* This function sets the Write Protect and Hold options for the QSPIPSU device
* driver.The device must be idle rather than busy transferring data before
* setting Write Protect and Hold options.
*
* @param InstancePtr is a pointer to the XQspiPsu instance.
* @param Value of the WP_HOLD bit in configuration register
*
* @return None
*
* @note
* This function is not thread-safe. This function can only be used with single
* flash configuration and x1/x2 data mode. This function cannot be used with
* x4 data mode and dual parallel and stacked flash configuration.
*
******************************************************************************/
void XQspiPsu_SetWP(XQspiPsu *InstancePtr, u8 Value)
{
u32 ConfigReg;
ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_CFG_OFFSET);
ConfigReg |= Value << XQSPIPSU_CFG_WP_HOLD_SHIFT;
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
ConfigReg);
}
/** @} */

2
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_3/src/xqspipsu_sinit.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_7/src/xqspipsu_sinit.c
View File

@ -33,7 +33,7 @@
/**
*
* @file xqspipsu_sinit.c
* @addtogroup qspipsu_v1_0
* @addtogroup qspipsu_v1_7
* @{
*
* The implementation of the XQspiPsu component's static initialization

40
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/resetps_v1_0/src/Makefile Normal file
View File

@ -0,0 +1,40 @@
COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
CC_FLAGS = $(COMPILER_FLAGS)
ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
OUTS = *.o
LIBSOURCES:=*.c
INCLUDEFILES:=*.h
OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
libs: banner resetps_libs clean
%.o: %.c
${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
banner:
echo "Compiling resetps"
resetps_libs: ${OBJECTS}
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
.PHONY: include
include: resetps_includes
resetps_includes:
${CP} ${INCLUDEFILES} ${INCLUDEDIR}
clean:
rm -rf ${OBJECTS}

1030
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/resetps_v1_0/src/xresetps.c Normal file
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