mirror of
https://github.com/espressif/ESP8266_RTOS_SDK.git
synced 2025-06-18 12:28:52 +08:00
fix(system): Fix wdt crash issue
1. only lock nmi in soft isr; 2. simplify PendSV; 3. more log info when wdt happen; 4. Fix nmi reentried issue; 5. Add some protection code; internal: 5c208f68
This commit is contained in:
Espressif Systems
6
VERSION
6
VERSION
@ -1,10 +1,10 @@
|
||||
gwen:
|
||||
crypto: 9ec59b5
|
||||
espnow: 9ec59b5
|
||||
main: cc0968d
|
||||
main: e9e3ace
|
||||
minic: 9ec59b5
|
||||
net80211: f2108f6
|
||||
pp: 1cf9bb0
|
||||
pp: e9e3ace
|
||||
pwm: 9ec59b5
|
||||
smartconfig:9ec59b5
|
||||
wpa: f2108f6
|
||||
@ -12,7 +12,7 @@ gwen:
|
||||
|
||||
gitlab:
|
||||
espconn: 3a998034
|
||||
freertos: 66a199b7
|
||||
freertos: a9985a9c
|
||||
lwip: 4dd2bcd3
|
||||
driver: 7bee5263
|
||||
mbedtls: 1ac9f1f4
|
||||
|
||||
Binary file not shown.
BIN
lib/libmain.a
BIN
lib/libmain.a
Binary file not shown.
BIN
lib/libpp.a
BIN
lib/libpp.a
Binary file not shown.
161
third_party/freertos/port.c
vendored
161
third_party/freertos/port.c
vendored
@ -80,7 +80,6 @@
|
||||
extern char NMIIrqIsOn;
|
||||
static char HdlMacSig = 0;
|
||||
static char SWReq = 0;
|
||||
static char PendSvIsPosted = 0;
|
||||
|
||||
unsigned cpu_sr;
|
||||
|
||||
@ -103,8 +102,9 @@ pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *p
|
||||
sp = (portSTACK_TYPE*)(((INT32U)(pxTopOfStack + 1) - XT_CP_SIZE - XT_STK_FRMSZ) & ~0xf);
|
||||
|
||||
/* Clear the entire frame (do not use memset() because we don't depend on C library) */
|
||||
for (tp = sp; tp <= pxTopOfStack; ++tp)
|
||||
for (tp = sp; tp <= pxTopOfStack; ++tp) {
|
||||
*tp = 0;
|
||||
}
|
||||
|
||||
/* Explicitly initialize certain saved registers */
|
||||
SET_STKREG(XT_STK_PC, pxCode); /* task entrypoint */
|
||||
@ -124,101 +124,46 @@ pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *p
|
||||
return sp;
|
||||
}
|
||||
|
||||
|
||||
void PendSV(char req)
|
||||
{
|
||||
char tmp=0;
|
||||
//ETS_INTR_LOCK();
|
||||
|
||||
if( NMIIrqIsOn == 0 )
|
||||
{
|
||||
if (req == 1) {
|
||||
vPortEnterCritical();
|
||||
//PortDisableInt_NoNest();
|
||||
tmp = 1;
|
||||
}
|
||||
|
||||
if(req ==1)
|
||||
{
|
||||
SWReq = 1;
|
||||
}
|
||||
else if(req ==2)
|
||||
xthal_set_intset(1 << ETS_SOFT_INUM);
|
||||
vPortExitCritical();
|
||||
} else if (req == 2) {
|
||||
HdlMacSig = 1;
|
||||
#if 0
|
||||
GPIO_REG_WRITE(GPIO_STATUS_W1TS_ADDRESS, 0x40);
|
||||
#else
|
||||
if(PendSvIsPosted == 0)
|
||||
{
|
||||
PendSvIsPosted = 1;
|
||||
xthal_set_intset(1 << ETS_SOFT_INUM);
|
||||
}
|
||||
#endif
|
||||
if(tmp == 1)
|
||||
vPortExitCritical();
|
||||
}
|
||||
|
||||
extern portBASE_TYPE MacIsrSigPostDefHdl(void);
|
||||
#if 0
|
||||
void IRAM_FUNC_ATTR
|
||||
GPIOIntrHdl(void)
|
||||
{
|
||||
//if( (GPIO_REG_READ(GPIO_STATUS_ADDRESS) & (1<<6)) == 0 )
|
||||
//printf("i");
|
||||
//printf("g,%08x\n",GPIO_REG_READ(GPIO_STATUS_ADDRESS));
|
||||
//SDIO_CLK GPIO interrupt
|
||||
|
||||
if( (GPIO_REG_READ(GPIO_STATUS_ADDRESS) & (1<<6)) != 0 )
|
||||
{
|
||||
//CloseNMI();
|
||||
|
||||
portBASE_TYPE xHigherPriorityTaskWoken=pdFALSE ;
|
||||
if(HdlMacSig == 1)
|
||||
{
|
||||
HdlMacSig = 0;
|
||||
xHigherPriorityTaskWoken = MacIsrSigPostDefHdl();
|
||||
}
|
||||
if( xHigherPriorityTaskWoken || (SWReq==1))
|
||||
{
|
||||
SWReq = 0;
|
||||
_xt_timer_int1();
|
||||
}
|
||||
//OpenNMI();
|
||||
GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, 0x40);
|
||||
}
|
||||
}
|
||||
#else
|
||||
void SoftIsrHdl(void* arg)
|
||||
{
|
||||
//if(DbgVal5==1)
|
||||
//printf("GP_%d,",SWReq);
|
||||
PendSvIsPosted = 0;
|
||||
ETS_NMI_LOCK();
|
||||
|
||||
portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
|
||||
if(HdlMacSig == 1)
|
||||
{
|
||||
xHigherPriorityTaskWoken = MacIsrSigPostDefHdl();
|
||||
|
||||
if (HdlMacSig == 1) {
|
||||
HdlMacSig = 0;
|
||||
xHigherPriorityTaskWoken = MacIsrSigPostDefHdl();
|
||||
}
|
||||
if( xHigherPriorityTaskWoken || (SWReq==1))
|
||||
{
|
||||
//if( DbgVal5==1 || DbgVal10==1 )
|
||||
//printf("_x_s,");
|
||||
|
||||
if (xHigherPriorityTaskWoken || (SWReq == 1)) {
|
||||
_xt_timer_int1();
|
||||
SWReq = 0;
|
||||
}
|
||||
|
||||
ETS_NMI_UNLOCK();
|
||||
}
|
||||
#endif
|
||||
|
||||
void xPortSysTickHandle(void)
|
||||
{
|
||||
//CloseNMI();
|
||||
{
|
||||
if(xTaskIncrementTick() !=pdFALSE )
|
||||
{
|
||||
//GPIO_REG_WRITE(GPIO_STATUS_W1TS_ADDRESS, 0x40);
|
||||
if (xTaskIncrementTick() != pdFALSE) {
|
||||
vTaskSwitchContext();
|
||||
}
|
||||
}
|
||||
//OpenNMI();
|
||||
}
|
||||
|
||||
/*
|
||||
* See header file for description.
|
||||
@ -226,27 +171,16 @@ void xPortSysTickHandle (void)
|
||||
portBASE_TYPE ICACHE_FLASH_ATTR
|
||||
xPortStartScheduler(void)
|
||||
{
|
||||
//set pendsv and systemtick as lowest priority ISR.
|
||||
//pendsv setting
|
||||
/*******GPIO sdio_clk isr*********/
|
||||
#if 0
|
||||
_xt_isr_attach(ETS_GPIO_INUM, GPIOIntrHdl, NULL);
|
||||
_xt_isr_unmask(1<<ETS_GPIO_INUM);
|
||||
#else
|
||||
/*******software isr*********/
|
||||
_xt_isr_attach(ETS_SOFT_INUM, SoftIsrHdl, NULL);
|
||||
_xt_isr_unmask(1 << ETS_SOFT_INUM);
|
||||
#endif
|
||||
|
||||
/* Initialize system tick timer interrupt and schedule the first tick. */
|
||||
_xt_tick_timer_init();
|
||||
|
||||
// os_printf("xPortStartScheduler\n");
|
||||
vTaskSwitchContext();
|
||||
|
||||
// REG_SET_BIT(0x3ff2006c, BIT(4));
|
||||
/* Restore the context of the first task that is going to run. */
|
||||
|
||||
XT_RTOS_INT_EXIT();
|
||||
|
||||
/* Should not get here as the tasks are now running! */
|
||||
@ -261,25 +195,17 @@ vPortEndScheduler( void )
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static unsigned int tick_lock=0;
|
||||
static char ClosedLv1Isr = 0;
|
||||
|
||||
void vPortEnterCritical(void)
|
||||
{
|
||||
if(NMIIrqIsOn == 0)
|
||||
{
|
||||
//if( uxCriticalNesting == 0 )
|
||||
{
|
||||
if( ClosedLv1Isr !=1 )
|
||||
{
|
||||
if (NMIIrqIsOn == 0) {
|
||||
if (ClosedLv1Isr != 1) {
|
||||
portDISABLE_INTERRUPTS();
|
||||
ClosedLv1Isr = 1;
|
||||
}
|
||||
//tick_lock = WDEV_NOW();
|
||||
}
|
||||
uxCriticalNesting++;
|
||||
}
|
||||
}
|
||||
@ -287,35 +213,32 @@ void vPortEnterCritical( void )
|
||||
|
||||
void vPortExitCritical(void)
|
||||
{
|
||||
if(NMIIrqIsOn == 0)
|
||||
{
|
||||
if(uxCriticalNesting > 0)
|
||||
{
|
||||
if (NMIIrqIsOn == 0) {
|
||||
if (uxCriticalNesting > 0) {
|
||||
uxCriticalNesting--;
|
||||
if( uxCriticalNesting == 0 )
|
||||
{
|
||||
if( ClosedLv1Isr ==1 )
|
||||
{
|
||||
|
||||
if (uxCriticalNesting == 0) {
|
||||
if (ClosedLv1Isr == 1) {
|
||||
ClosedLv1Isr = 0;
|
||||
portENABLE_INTERRUPTS();
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
} else {
|
||||
ets_printf("E:C:%d\n", uxCriticalNesting);
|
||||
PORT_ASSERT((uxCriticalNesting > 0));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void ShowCritical(void)
|
||||
void ICACHE_FLASH_ATTR ShowCritical(void)
|
||||
{
|
||||
ets_printf("ShowCritical:%d\n",uxCriticalNesting);
|
||||
os_printf("ShowCritical:%d\n", uxCriticalNesting);
|
||||
os_printf("HdlMacSig:%d\n", HdlMacSig);
|
||||
os_printf("SWReq:%d\n", SWReq);
|
||||
|
||||
ets_delay_us(50000);
|
||||
}
|
||||
|
||||
|
||||
void vPortETSIntrLock(void)
|
||||
{
|
||||
ETS_INTR_LOCK();
|
||||
@ -326,29 +249,20 @@ void vPortETSIntrUnlock( void )
|
||||
ETS_INTR_UNLOCK();
|
||||
}
|
||||
|
||||
void
|
||||
PortDisableInt_NoNest( void )
|
||||
{
|
||||
// printf("ERRRRRRR\n");
|
||||
if(NMIIrqIsOn == 0)
|
||||
{
|
||||
if( ClosedLv1Isr !=1 )
|
||||
void PortDisableInt_NoNest(void)
|
||||
{
|
||||
if (NMIIrqIsOn == 0) {
|
||||
if (ClosedLv1Isr != 1) {
|
||||
portDISABLE_INTERRUPTS();
|
||||
ClosedLv1Isr = 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
PortEnableInt_NoNest( void )
|
||||
{
|
||||
// printf("ERRRRR\n");
|
||||
|
||||
if(NMIIrqIsOn == 0)
|
||||
{
|
||||
if( ClosedLv1Isr ==1 )
|
||||
void PortEnableInt_NoNest(void)
|
||||
{
|
||||
if (NMIIrqIsOn == 0) {
|
||||
if (ClosedLv1Isr == 1) {
|
||||
ClosedLv1Isr = 0;
|
||||
portENABLE_INTERRUPTS();
|
||||
}
|
||||
@ -358,7 +272,6 @@ PortEnableInt_NoNest( void )
|
||||
/*-----------------------------------------------------------*/
|
||||
void ICACHE_FLASH_ATTR ResetCcountVal(unsigned int cnt_val)
|
||||
{
|
||||
// XT_WSR_CCOUNT(cnt_val);
|
||||
asm volatile("wsr a2, ccount");
|
||||
}
|
||||
|
||||
@ -377,10 +290,8 @@ uint16 _xt_isr_handler(uint16 i)
|
||||
uint8 index;
|
||||
|
||||
if (i & (1 << ETS_WDT_INUM)) {
|
||||
// printf("i %x %u\n", i, REG_READ(0x3ff20c00));
|
||||
index = ETS_WDT_INUM;
|
||||
}
|
||||
else if (i & (1 << ETS_GPIO_INUM)) {
|
||||
} else if (i & (1 << ETS_GPIO_INUM)) {
|
||||
index = ETS_GPIO_INUM;
|
||||
} else {
|
||||
index = __builtin_ffs(i) - 1;
|
||||
|
||||
Reference in New Issue
Block a user