mirror of
https://github.com/espressif/ESP8266_RTOS_SDK.git
synced 2025-05-22 01:27:11 +08:00
feat(esp8266): Add full icache mode
Use full 32 KB iram as icache.
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@ -52,9 +52,8 @@ void chip_boot(size_t start_addr, size_t map)
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extern esp_spi_flash_chip_t flashchip;
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extern void phy_get_bb_evm(void);
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extern void cache_init(uint32_t , uint32_t, uint32_t);
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extern void cache_init(uint8_t);
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extern void user_spi_flash_dio_to_qio_pre_init(void);
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extern int esp_get_boot_param(uint32_t, uint32_t, void *, uint32_t);
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phy_get_bb_evm();
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@ -93,7 +92,7 @@ void chip_boot(size_t start_addr, size_t map)
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SET_PERI_REG_BITS(PERIPHS_SPI_FLASH_CTRL, 0xfff, freqbits, 0);
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ESP_EARLY_LOGD(TAG, "SPI flash cache map is %d\n", map);
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cache_init(map, 0, 0);
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cache_init(map);
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if (fhdr.spi_mode == ESP_IMAGE_SPI_MODE_QIO) {
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ESP_EARLY_LOGD(TAG, "SPI flash enable QIO mode\n");
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39
components/esp8266/source/esp_cache.c
Normal file
39
components/esp8266/source/esp_cache.c
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@ -0,0 +1,39 @@
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// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "sdkconfig.h"
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#include <stdint.h>
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#include "esp_attr.h"
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#include "esp8266/rom_functions.h"
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#ifdef CONFIG_SOC_FULL_ICACHE
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#define SOC_CACHE_SIZE 1 // 32KB
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#else
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#define SOC_CACHE_SIZE 0 // 16KB
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#endif
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static uint8_t s_cache_map;
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static uint8_t s_cache_size = SOC_CACHE_SIZE;
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void IRAM_ATTR Cache_Read_Enable_New(void)
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{
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Cache_Read_Enable(s_cache_map, 0, s_cache_size);
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}
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void cache_init(int map)
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{
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s_cache_map = map;
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Cache_Read_Enable_New();
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}
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