diff --git a/components/bootloader/subproject/main/esp8266.bootloader.ld b/components/bootloader/subproject/main/esp8266.bootloader.ld
index df37355d..122dfd33 100644
--- a/components/bootloader/subproject/main/esp8266.bootloader.ld
+++ b/components/bootloader/subproject/main/esp8266.bootloader.ld
@@ -16,7 +16,7 @@ MEMORY
   dram_seg  :    org = 0x3FFE8000, len = 0x18000
 
   /* Functions which are critical should be put in this segment. */
-  iram_seg  :    org = 0x40100000, len = 0xC000
+  iram_seg  :    org = 0x40100000, len = 0x8000
 }
 
 /*  Default entry point:  */
diff --git a/components/esp8266/Kconfig b/components/esp8266/Kconfig
index d2c9655a..0ce6ee46 100644
--- a/components/esp8266/Kconfig
+++ b/components/esp8266/Kconfig
@@ -28,6 +28,13 @@ config NEWLIB_STDOUT_LINE_ENDING_CR
     bool "CR"
 endchoice
 
+config SOC_FULL_ICACHE
+    bool "Enable full cache mode"
+    default n
+    help
+        Enable this option, full 32 KB iram instead of 16 KB iram will be used as icache, so the heap use can use
+        may reduce a lot.
+
 endmenu
 
 menu WIFI
diff --git a/components/esp8266/include/esp8266/rom_functions.h b/components/esp8266/include/esp8266/rom_functions.h
index 5f847846..c1f20370 100644
--- a/components/esp8266/include/esp8266/rom_functions.h
+++ b/components/esp8266/include/esp8266/rom_functions.h
@@ -33,5 +33,6 @@ int SPI_read_status(esp_spi_flash_chip_t *chip, uint32_t *status);
 int Enable_QMode(esp_spi_flash_chip_t *chip);
 
 void Cache_Read_Disable();
+void Cache_Read_Enable(uint8_t map, uint8_t p, uint8_t v);
 
 #endif
diff --git a/components/esp8266/lib/VERSION b/components/esp8266/lib/VERSION
index 5bdda5a0..6a00e507 100644
--- a/components/esp8266/lib/VERSION
+++ b/components/esp8266/lib/VERSION
@@ -1,7 +1,7 @@
 gwen:
     crypto:     8943c89
     espnow:     8943c89
-    core:       2f2b0ef
+    core:       f4f0d3d
     net80211:   80fc165
     pp:         06e0988
     pwm:        0181338
diff --git a/components/esp8266/lib/libcore.a b/components/esp8266/lib/libcore.a
index 7ead3031..a7165fe0 100644
Binary files a/components/esp8266/lib/libcore.a and b/components/esp8266/lib/libcore.a differ
diff --git a/components/esp8266/source/chip_boot.c b/components/esp8266/source/chip_boot.c
index 9cc08586..7e9020a9 100644
--- a/components/esp8266/source/chip_boot.c
+++ b/components/esp8266/source/chip_boot.c
@@ -52,9 +52,8 @@ void chip_boot(size_t start_addr, size_t map)
 
     extern esp_spi_flash_chip_t flashchip;
     extern void phy_get_bb_evm(void);
-    extern void cache_init(uint32_t , uint32_t, uint32_t);
+    extern void cache_init(uint8_t);
     extern void user_spi_flash_dio_to_qio_pre_init(void);
-    extern int esp_get_boot_param(uint32_t, uint32_t, void *, uint32_t);
 
     phy_get_bb_evm();
 
@@ -93,7 +92,7 @@ void chip_boot(size_t start_addr, size_t map)
     SET_PERI_REG_BITS(PERIPHS_SPI_FLASH_CTRL, 0xfff, freqbits, 0);
 
     ESP_EARLY_LOGD(TAG, "SPI flash cache map is %d\n", map);
-    cache_init(map, 0, 0);
+    cache_init(map);
 
     if (fhdr.spi_mode == ESP_IMAGE_SPI_MODE_QIO) {
         ESP_EARLY_LOGD(TAG, "SPI flash enable QIO mode\n");
diff --git a/components/esp8266/source/esp_cache.c b/components/esp8266/source/esp_cache.c
new file mode 100644
index 00000000..411b7a19
--- /dev/null
+++ b/components/esp8266/source/esp_cache.c
@@ -0,0 +1,39 @@
+// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "sdkconfig.h"
+#include <stdint.h>
+#include "esp_attr.h"
+#include "esp8266/rom_functions.h"
+
+#ifdef CONFIG_SOC_FULL_ICACHE
+#define SOC_CACHE_SIZE 1 // 32KB
+#else
+#define SOC_CACHE_SIZE 0 // 16KB
+#endif
+
+static uint8_t s_cache_map;
+static uint8_t s_cache_size = SOC_CACHE_SIZE;
+
+void IRAM_ATTR Cache_Read_Enable_New(void)
+{
+    Cache_Read_Enable(s_cache_map, 0, s_cache_size);
+}
+
+void cache_init(int map)
+{
+    s_cache_map = map;
+
+    Cache_Read_Enable_New();
+}
diff --git a/components/freertos/port/esp8266/heap_5.c b/components/freertos/port/esp8266/heap_5.c
index 0e94d843..f2ce1f39 100644
--- a/components/freertos/port/esp8266/heap_5.c
+++ b/components/freertos/port/esp8266/heap_5.c
@@ -105,6 +105,8 @@
  * Note 0x80000000 is the lower address so appears in the array first.
  *
  */
+#include "sdkconfig.h"
+
 #include <stdlib.h>
 #include <stdio.h>
 #include <string.h>
@@ -363,8 +365,10 @@ static bool is_inited = false;
         xHeapRegions[0].pucStartAddress = ( uint8_t * )&_heap_start;
         xHeapRegions[0].xSizeInBytes = (( size_t)( 0x40000000 - (uint32_t)&_heap_start));
         
+#ifndef CONFIG_SOC_FULL_ICACHE
         xHeapRegions[1].pucStartAddress = ( uint8_t * )&_lit4_end;
         xHeapRegions[1].xSizeInBytes = (( size_t)( 0x4010C000 - (uint32_t)&_lit4_end));
+#endif
 
         is_inited = true;
         vPortDefineHeapRegions(xHeapRegions);