espressif/ESP8266_RTOS_SDK
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feat(driver): Use astyle to format the code

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This commit is contained in:
Wu Jian Gang
2018-05-19 22:55:14 +08:00
parent ae6c134ec4
commit a08d0711a4
11 changed files with 305 additions and 290 deletions
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2
components/esp8266/driver/hw_timer.c
View File

@ -62,6 +62,7 @@ void hw_timer_disarm(void)
void hw_timer_arm(uint32 val, bool req) void hw_timer_arm(uint32 val, bool req)
{ {
frc1_auto_load = req; frc1_auto_load = req;
if (frc1_auto_load == true) { if (frc1_auto_load == true) {
RTC_REG_WRITE(FRC1_CTRL_ADDRESS, RTC_REG_WRITE(FRC1_CTRL_ADDRESS,
FRC1_AUTO_LOAD | DIVDED_BY_16 | FRC1_ENABLE_TIMER | TM_EDGE_INT); FRC1_AUTO_LOAD | DIVDED_BY_16 | FRC1_ENABLE_TIMER | TM_EDGE_INT);
@ -81,6 +82,7 @@ void hw_timer_set_func(void (* user_hw_timer_cb_set)(void))
void hw_timer_init(void) void hw_timer_init(void)
{ {
#if 0 #if 0
if (req == 1) { if (req == 1) {
RTC_REG_WRITE(FRC1_CTRL_ADDRESS, RTC_REG_WRITE(FRC1_CTRL_ADDRESS,
FRC1_AUTO_LOAD | DIVDED_BY_16 | FRC1_ENABLE_TIMER | TM_EDGE_INT); FRC1_AUTO_LOAD | DIVDED_BY_16 | FRC1_ENABLE_TIMER | TM_EDGE_INT);

3
components/esp8266/driver/i2c_master.c
View File

@ -39,6 +39,7 @@ i2c_master_setDC(uint8 SDA, uint8 SCL)
m_nLastSDA = SDA; m_nLastSDA = SDA;
m_nLastSCL = SCL; m_nLastSCL = SCL;
ETS_INTR_LOCK(); ETS_INTR_LOCK();
if ((0 == SDA) && (0 == SCL)) { if ((0 == SDA) && (0 == SCL)) {
I2C_MASTER_SDA_LOW_SCL_LOW(); I2C_MASTER_SDA_LOW_SCL_LOW();
} else if ((0 == SDA) && (1 == SCL)) { } else if ((0 == SDA) && (1 == SCL)) {
@ -48,6 +49,7 @@ i2c_master_setDC(uint8 SDA, uint8 SCL)
} else { } else {
I2C_MASTER_SDA_HIGH_SCL_HIGH(); I2C_MASTER_SDA_HIGH_SCL_HIGH();
} }
ETS_INTR_UNLOCK(); ETS_INTR_UNLOCK();
} }
@ -239,6 +241,7 @@ i2c_master_send_ack(void)
{ {
i2c_master_setAck(0x0); i2c_master_setAck(0x0);
} }
/****************************************************************************** /******************************************************************************
* FunctionName : i2c_master_send_nack * FunctionName : i2c_master_send_nack
* Description : response nack * Description : response nack

41
components/esp8266/driver/spi_interface.c
View File

@ -61,6 +61,7 @@ void __ShowRegValue(const char * func, uint32_t line)
printf(" ADDR[0x%08x],Value[0x%08x]\r\n", regAddr, READ_PERI_REG(regAddr)); printf(" ADDR[0x%08x],Value[0x%08x]\r\n", regAddr, READ_PERI_REG(regAddr));
regAddr += 4; regAddr += 4;
} }
#endif #endif
} }
@ -77,20 +78,24 @@ void ICACHE_FLASH_ATTR SPIInit(SpiNum spiNum, SpiAttr* pAttr)
|| (NULL == pAttr)) { || (NULL == pAttr)) {
return; return;
} }
// SPI_CPOL & SPI_CPHA // SPI_CPOL & SPI_CPHA
switch (pAttr->subMode) { switch (pAttr->subMode) {
case SpiSubMode_1: case SpiSubMode_1:
CLEAR_PERI_REG_MASK(SPI_PIN(spiNum), SPI_IDLE_EDGE); CLEAR_PERI_REG_MASK(SPI_PIN(spiNum), SPI_IDLE_EDGE);
SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_CK_OUT_EDGE); // CHPA_FALLING_EDGE_SAMPLE SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_CK_OUT_EDGE); // CHPA_FALLING_EDGE_SAMPLE
break; break;
case SpiSubMode_2: case SpiSubMode_2:
SET_PERI_REG_MASK(SPI_PIN(spiNum), SPI_IDLE_EDGE); SET_PERI_REG_MASK(SPI_PIN(spiNum), SPI_IDLE_EDGE);
SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_CK_OUT_EDGE); // CHPA_FALLING_EDGE_SAMPLE SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_CK_OUT_EDGE); // CHPA_FALLING_EDGE_SAMPLE
break; break;
case SpiSubMode_3: case SpiSubMode_3:
SET_PERI_REG_MASK(SPI_PIN(spiNum), SPI_IDLE_EDGE); SET_PERI_REG_MASK(SPI_PIN(spiNum), SPI_IDLE_EDGE);
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_CK_OUT_EDGE); CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_CK_OUT_EDGE);
break; break;
case SpiSubMode_0: case SpiSubMode_0:
default: default:
CLEAR_PERI_REG_MASK(SPI_PIN(spiNum), SPI_IDLE_EDGE); CLEAR_PERI_REG_MASK(SPI_PIN(spiNum), SPI_IDLE_EDGE);
@ -120,9 +125,11 @@ void ICACHE_FLASH_ATTR SPIInit(SpiNum spiNum, SpiAttr* pAttr)
CLEAR_PERI_REG_MASK(SPI_SLAVE(spiNum), SPI_SLAVE_MODE); CLEAR_PERI_REG_MASK(SPI_SLAVE(spiNum), SPI_SLAVE_MODE);
// SPI Send buffer // SPI Send buffer
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO_HIGHPART); // By default slave send buffer C0-C7 CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO_HIGHPART); // By default slave send buffer C0-C7
// SPI Speed // SPI Speed
if (1 < (pAttr->speed)) { if (1 < (pAttr->speed)) {
CLEAR_PERI_REG_MASK(SPI_CLOCK(spiNum), SPI_CLK_EQU_SYSCLK); CLEAR_PERI_REG_MASK(SPI_CLOCK(spiNum), SPI_CLK_EQU_SYSCLK);
if (spiNum == SpiNum_HSPI) { if (spiNum == SpiNum_HSPI) {
CLEAR_PERI_REG_MASK(PERIPHS_IO_MUX_CONF_U, SPI1_CLK_EQU_SYS_CLK); CLEAR_PERI_REG_MASK(PERIPHS_IO_MUX_CONF_U, SPI1_CLK_EQU_SYS_CLK);
} }
@ -134,6 +141,7 @@ void ICACHE_FLASH_ATTR SPIInit(SpiNum spiNum, SpiAttr* pAttr)
} else { } else {
WRITE_PERI_REG(SPI_CLOCK(spiNum), SPI_CLK_EQU_SYSCLK); // 80Mhz speed WRITE_PERI_REG(SPI_CLOCK(spiNum), SPI_CLK_EQU_SYSCLK); // 80Mhz speed
} }
// By default format:CMD+ADDR+DATA // By default format:CMD+ADDR+DATA
SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_CS_SETUP | SPI_CS_HOLD | SPI_USR_MOSI); SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_CS_SETUP | SPI_CS_HOLD | SPI_USR_MOSI);
@ -186,6 +194,7 @@ void ICACHE_FLASH_ATTR SPIMasterCfgAddr(SpiNum spiNum, uint32_t addr)
if (spiNum > SpiNum_HSPI) { if (spiNum > SpiNum_HSPI) {
return; return;
} }
// Set address // Set address
WRITE_PERI_REG(SPI_ADDR(spiNum), addr); WRITE_PERI_REG(SPI_ADDR(spiNum), addr);
} }
@ -199,6 +208,7 @@ void ICACHE_FLASH_ATTR SPIMasterCfgCmd(SpiNum spiNum, uint32_t cmd)
if (spiNum > SpiNum_HSPI) { if (spiNum > SpiNum_HSPI) {
return; return;
} }
// SPI_USER2 bit28-31 is cmd length,cmd bit length is value(0-15)+1, // SPI_USER2 bit28-31 is cmd length,cmd bit length is value(0-15)+1,
// bit15-0 is cmd value. // bit15-0 is cmd value.
SET_PERI_REG_BITS(SPI_USER2(spiNum), SPI_USR_COMMAND_VALUE, cmd, SPI_USR_COMMAND_VALUE_S); SET_PERI_REG_BITS(SPI_USER2(spiNum), SPI_USR_COMMAND_VALUE, cmd, SPI_USR_COMMAND_VALUE_S);
@ -211,13 +221,17 @@ void ICACHE_FLASH_ATTR SPIMasterCfgCmd(SpiNum spiNum, uint32_t cmd)
int ICACHE_FLASH_ATTR SPIMasterSendData(SpiNum spiNum, SpiData* pInData) int ICACHE_FLASH_ATTR SPIMasterSendData(SpiNum spiNum, SpiData* pInData)
{ {
char idx = 0; char idx = 0;
if ((spiNum > SpiNum_HSPI) if ((spiNum > SpiNum_HSPI)
|| (NULL == pInData) || (NULL == pInData)
|| (64 < pInData->dataLen)) { || (64 < pInData->dataLen)) {
return -1; return -1;
} }
uint32_t* value = pInData->data; uint32_t* value = pInData->data;
while (READ_PERI_REG(SPI_CMD(spiNum))&SPI_USR); while (READ_PERI_REG(SPI_CMD(spiNum))&SPI_USR);
// Set command by user. // Set command by user.
if (pInData->cmdLen != 0) { if (pInData->cmdLen != 0) {
// Max command length 16 bits. // Max command length 16 bits.
@ -232,6 +246,7 @@ int ICACHE_FLASH_ATTR SPIMasterSendData(SpiNum spiNum, SpiData* pInData)
SET_PERI_REG_BITS(SPI_USER2(spiNum), SPI_USR_COMMAND_BITLEN, SET_PERI_REG_BITS(SPI_USER2(spiNum), SPI_USR_COMMAND_BITLEN,
0, SPI_USR_COMMAND_BITLEN_S); 0, SPI_USR_COMMAND_BITLEN_S);
} }
// Set Address by user. // Set Address by user.
if (pInData->addrLen == 0) { if (pInData->addrLen == 0) {
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_ADDR); CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_ADDR);
@ -241,6 +256,7 @@ int ICACHE_FLASH_ATTR SPIMasterSendData(SpiNum spiNum, SpiData* pInData)
if (NULL == pInData->addr) { if (NULL == pInData->addr) {
return -1; return -1;
} }
SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_ADDR_BITLEN, SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_ADDR_BITLEN,
((pInData->addrLen << 3) - 1), SPI_USR_ADDR_BITLEN_S); ((pInData->addrLen << 3) - 1), SPI_USR_ADDR_BITLEN_S);
// Enable address // Enable address
@ -248,18 +264,22 @@ int ICACHE_FLASH_ATTR SPIMasterSendData(SpiNum spiNum, SpiData* pInData)
// Load address // Load address
SPIMasterCfgAddr(spiNum, *pInData->addr); SPIMasterCfgAddr(spiNum, *pInData->addr);
} }
// Set data by user. // Set data by user.
if (pInData->dataLen != 0) { if (pInData->dataLen != 0) {
if (NULL == value) { if (NULL == value) {
return -1; return -1;
} }
// Enable MOSI // Enable MOSI
SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI); SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI);
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO); CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO);
// Load send buffer // Load send buffer
do { do {
WRITE_PERI_REG((SPI_W0(spiNum) + (idx << 2)), *value++); WRITE_PERI_REG((SPI_W0(spiNum) + (idx << 2)), *value++);
} while (++idx < (pInData->dataLen / 4)); } while (++idx < (pInData->dataLen / 4));
// Set data send buffer length.Max data length 64 bytes. // Set data send buffer length.Max data length 64 bytes.
SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_MOSI_BITLEN, ((pInData->dataLen << 3) - 1), SPI_USR_MOSI_BITLEN_S); SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_MOSI_BITLEN, ((pInData->dataLen << 3) - 1), SPI_USR_MOSI_BITLEN_S);
} else { } else {
@ -268,6 +288,7 @@ int ICACHE_FLASH_ATTR SPIMasterSendData(SpiNum spiNum, SpiData* pInData)
SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_MOSI_BITLEN, SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_MOSI_BITLEN,
0, SPI_USR_MOSI_BITLEN_S); 0, SPI_USR_MOSI_BITLEN_S);
} }
// Start send data // Start send data
SET_PERI_REG_MASK(SPI_CMD(spiNum), SPI_USR); SET_PERI_REG_MASK(SPI_CMD(spiNum), SPI_USR);
@ -282,13 +303,16 @@ int ICACHE_FLASH_ATTR SPIMasterSendData(SpiNum spiNum, SpiData* pInData)
int ICACHE_FLASH_ATTR SPIMasterRecvData(SpiNum spiNum, SpiData* pOutData) int ICACHE_FLASH_ATTR SPIMasterRecvData(SpiNum spiNum, SpiData* pOutData)
{ {
char idx = 0; char idx = 0;
if ((spiNum > SpiNum_HSPI) if ((spiNum > SpiNum_HSPI)
|| (NULL == pOutData)) { || (NULL == pOutData)) {
return -1; return -1;
} }
uint32_t* value = pOutData->data; uint32_t* value = pOutData->data;
while (READ_PERI_REG(SPI_CMD(spiNum))&SPI_USR); while (READ_PERI_REG(SPI_CMD(spiNum))&SPI_USR);
// Set command by user. // Set command by user.
if (pOutData->cmdLen != 0) { if (pOutData->cmdLen != 0) {
// Max command length 16 bits. // Max command length 16 bits.
@ -303,6 +327,7 @@ int ICACHE_FLASH_ATTR SPIMasterRecvData(SpiNum spiNum, SpiData* pOutData)
SET_PERI_REG_BITS(SPI_USER2(spiNum), SPI_USR_COMMAND_BITLEN, SET_PERI_REG_BITS(SPI_USER2(spiNum), SPI_USR_COMMAND_BITLEN,
0, SPI_USR_COMMAND_BITLEN_S); 0, SPI_USR_COMMAND_BITLEN_S);
} }
// Set Address by user. // Set Address by user.
if (pOutData->addrLen == 0) { if (pOutData->addrLen == 0) {
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_ADDR); CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_ADDR);
@ -312,6 +337,7 @@ int ICACHE_FLASH_ATTR SPIMasterRecvData(SpiNum spiNum, SpiData* pOutData)
if (NULL == pOutData->addr) { if (NULL == pOutData->addr) {
return -1; return -1;
} }
SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_ADDR_BITLEN, SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_ADDR_BITLEN,
((pOutData->addrLen << 3) - 1), SPI_USR_ADDR_BITLEN_S); ((pOutData->addrLen << 3) - 1), SPI_USR_ADDR_BITLEN_S);
// Enable address // Enable address
@ -319,11 +345,13 @@ int ICACHE_FLASH_ATTR SPIMasterRecvData(SpiNum spiNum, SpiData* pOutData)
// Load address // Load address
SPIMasterCfgAddr(spiNum, *pOutData->addr); SPIMasterCfgAddr(spiNum, *pOutData->addr);
} }
// Set data by user. // Set data by user.
if (pOutData->dataLen != 0) { if (pOutData->dataLen != 0) {
if (NULL == value) { if (NULL == value) {
return -1; return -1;
} }
// Clear MOSI enable // Clear MOSI enable
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI); CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI);
// Enable MOSI // Enable MOSI
@ -339,13 +367,16 @@ int ICACHE_FLASH_ATTR SPIMasterRecvData(SpiNum spiNum, SpiData* pOutData)
//CLEAR FIFO DATA //CLEAR FIFO DATA
int fifo_idx = 0; int fifo_idx = 0;
do { do {
WRITE_PERI_REG(SPI_W0(spiNum) + (fifo_idx << 2), 0); WRITE_PERI_REG(SPI_W0(spiNum) + (fifo_idx << 2), 0);
} while (++fifo_idx < (pOutData->dataLen / 4)); } while (++fifo_idx < (pOutData->dataLen / 4));
// Start send data // Start send data
SET_PERI_REG_MASK(SPI_CMD(spiNum), SPI_USR); SET_PERI_REG_MASK(SPI_CMD(spiNum), SPI_USR);
while (READ_PERI_REG(SPI_CMD(spiNum))&SPI_USR); while (READ_PERI_REG(SPI_CMD(spiNum))&SPI_USR);
// Read data out // Read data out
do { do {
*pOutData->data++ = READ_PERI_REG(SPI_W0(spiNum) + (idx << 2)); *pOutData->data++ = READ_PERI_REG(SPI_W0(spiNum) + (idx << 2));
@ -364,10 +395,13 @@ int ICACHE_FLASH_ATTR SPISlaveSendData(SpiNum spiNum, uint32_t *pInData, uint8_t
if (NULL == pInData) { if (NULL == pInData) {
return -1; return -1;
} }
char i; char i;
for (i = 0; i < outLen; ++i) { for (i = 0; i < outLen; ++i) {
WRITE_PERI_REG((SPI_W8(spiNum) + (i << 2)), *pInData++); WRITE_PERI_REG((SPI_W8(spiNum) + (i << 2)), *pInData++);
} }
return 0; return 0;
} }
@ -408,7 +442,9 @@ void ICACHE_FLASH_ATTR SPIMasterSendStatus(SpiNum spiNum, uint8_t data)
if (spiNum > SpiNum_HSPI) { if (spiNum > SpiNum_HSPI) {
return; return;
} }
while (READ_PERI_REG(SPI_CMD(spiNum))&SPI_USR); while (READ_PERI_REG(SPI_CMD(spiNum))&SPI_USR);
// Enable MOSI // Enable MOSI
SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI); SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI);
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO | SPI_USR_DUMMY | SPI_USR_ADDR); CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO | SPI_USR_DUMMY | SPI_USR_ADDR);
@ -439,6 +475,7 @@ int ICACHE_FLASH_ATTR SPIMasterRecvStatus(SpiNum spiNum)
} }
while (READ_PERI_REG(SPI_CMD(spiNum))&SPI_USR); while (READ_PERI_REG(SPI_CMD(spiNum))&SPI_USR);
// Enable MISO // Enable MISO
SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO); SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO);
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI | SPI_USR_DUMMY | SPI_USR_ADDR); CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI | SPI_USR_DUMMY | SPI_USR_ADDR);
@ -471,6 +508,7 @@ void ICACHE_FLASH_ATTR SPICsPinSelect(SpiNum spiNum, SpiPinCS pinCs)
if (spiNum > SpiNum_HSPI) { if (spiNum > SpiNum_HSPI) {
return; return;
} }
// clear select // clear select
SET_PERI_REG_BITS(SPI_PIN(spiNum), 3, 0, 0); SET_PERI_REG_BITS(SPI_PIN(spiNum), 3, 0, 0);
SET_PERI_REG_MASK(SPI_PIN(spiNum), pinCs); SET_PERI_REG_MASK(SPI_PIN(spiNum), pinCs);
@ -485,6 +523,7 @@ void ICACHE_FLASH_ATTR SPIIntEnable(SpiNum spiNum, SpiIntSrc intSrc)
if (spiNum > SpiNum_HSPI) { if (spiNum > SpiNum_HSPI) {
return; return;
} }
SET_PERI_REG_MASK(SPI_SLAVE(spiNum), intSrc); SET_PERI_REG_MASK(SPI_SLAVE(spiNum), intSrc);
} }
@ -497,6 +536,7 @@ void ICACHE_FLASH_ATTR SPIIntDisable(SpiNum spiNum, SpiIntSrc intSrc)
if (spiNum > SpiNum_HSPI) { if (spiNum > SpiNum_HSPI) {
return; return;
} }
CLEAR_PERI_REG_MASK(SPI_SLAVE(spiNum), intSrc); CLEAR_PERI_REG_MASK(SPI_SLAVE(spiNum), intSrc);
} }
@ -509,6 +549,7 @@ void ICACHE_FLASH_ATTR SPIIntClear(SpiNum spiNum)
if (spiNum > SpiNum_HSPI) { if (spiNum > SpiNum_HSPI) {
return; return;
} }
CLEAR_PERI_REG_MASK(SPI_SLAVE(spiNum), SpiIntSrc_TransDoneEn CLEAR_PERI_REG_MASK(SPI_SLAVE(spiNum), SpiIntSrc_TransDoneEn
| SpiIntSrc_WrStaDoneEn | SpiIntSrc_WrStaDoneEn
| SpiIntSrc_RdStaDoneEn | SpiIntSrc_RdStaDoneEn

70
components/esp8266/driver/uart.c
View File

@ -34,8 +34,7 @@ typedef struct _os_event_ {
xTaskHandle xUartTaskHandle; xTaskHandle xUartTaskHandle;
xQueueHandle xQueueUart; xQueueHandle xQueueUart;
LOCAL STATUS LOCAL STATUS uart_tx_one_char(uint8 uart, uint8 TxChar)
uart_tx_one_char(uint8 uart, uint8 TxChar)
{ {
while (true) { while (true) {
uint32 fifo_cnt = READ_PERI_REG(UART_STATUS(uart)) & (UART_TXFIFO_CNT << UART_TXFIFO_CNT_S); uint32 fifo_cnt = READ_PERI_REG(UART_STATUS(uart)) & (UART_TXFIFO_CNT << UART_TXFIFO_CNT_S);
@ -49,8 +48,7 @@ uart_tx_one_char(uint8 uart, uint8 TxChar)
return OK; return OK;
} }
LOCAL void LOCAL void uart1_write_char(char c)
uart1_write_char(char c)
{ {
if (c == '\n') { if (c == '\n') {
uart_tx_one_char(UART1, '\r'); uart_tx_one_char(UART1, '\r');
@ -61,8 +59,7 @@ uart1_write_char(char c)
} }
} }
LOCAL void LOCAL void uart0_write_char(char c)
uart0_write_char(char c)
{ {
if (c == '\n') { if (c == '\n') {
uart_tx_one_char(UART0, '\r'); uart_tx_one_char(UART0, '\r');
@ -74,8 +71,7 @@ uart0_write_char(char c)
} }
#if 0 #if 0
LOCAL void LOCAL void uart_rx_intr_handler_ssc(void *arg)
uart_rx_intr_handler_ssc(void *arg)
{ {
/* uart0 and uart1 intr combine togther, when interrupt occur, see reg 0x3ff20020, bit2, bit0 represents /* uart0 and uart1 intr combine togther, when interrupt occur, see reg 0x3ff20020, bit2, bit0 represents
* uart1 and uart0 respectively * uart1 and uart0 respectively
@ -101,8 +97,7 @@ uart_rx_intr_handler_ssc(void *arg)
portEND_SWITCHING_ISR(xHigherPriorityTaskWoken); portEND_SWITCHING_ISR(xHigherPriorityTaskWoken);
} }
LOCAL void LOCAL void uart_config(uint8 uart_no, UartDevice *uart)
uart_config(uint8 uart_no, UartDevice *uart)
{ {
if (uart_no == UART1) { if (uart_no == UART1) {
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO2_U, FUNC_U1TXD_BK); PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO2_U, FUNC_U1TXD_BK);
@ -141,8 +136,7 @@ uart_config(uint8 uart_no, UartDevice *uart)
#endif #endif
#if 0 #if 0
LOCAL void LOCAL void uart_task(void *pvParameters)
uart_task(void *pvParameters)
{ {
os_event_t e; os_event_t e;
@ -162,8 +156,7 @@ uart_task(void *pvParameters)
vTaskDelete(NULL); vTaskDelete(NULL);
} }
void void uart_init(void)
uart_init(void)
{ {
while (READ_PERI_REG(UART_STATUS(0)) & (UART_TXFIFO_CNT << UART_TXFIFO_CNT_S)); while (READ_PERI_REG(UART_STATUS(0)) & (UART_TXFIFO_CNT << UART_TXFIFO_CNT_S));
@ -193,27 +186,23 @@ uart_init(void)
//================================================================= //=================================================================
void void UART_SetWordLength(UART_Port uart_no, UART_WordLength len)
UART_SetWordLength(UART_Port uart_no, UART_WordLength len)
{ {
SET_PERI_REG_BITS(UART_CONF0(uart_no), UART_BIT_NUM, len, UART_BIT_NUM_S); SET_PERI_REG_BITS(UART_CONF0(uart_no), UART_BIT_NUM, len, UART_BIT_NUM_S);
} }
void void UART_SetStopBits(UART_Port uart_no, UART_StopBits bit_num)
UART_SetStopBits(UART_Port uart_no, UART_StopBits bit_num)
{ {
SET_PERI_REG_BITS(UART_CONF0(uart_no), UART_STOP_BIT_NUM, bit_num, UART_STOP_BIT_NUM_S); SET_PERI_REG_BITS(UART_CONF0(uart_no), UART_STOP_BIT_NUM, bit_num, UART_STOP_BIT_NUM_S);
} }
void void UART_SetLineInverse(UART_Port uart_no, UART_LineLevelInverse inverse_mask)
UART_SetLineInverse(UART_Port uart_no, UART_LineLevelInverse inverse_mask)
{ {
CLEAR_PERI_REG_MASK(UART_CONF0(uart_no), UART_LINE_INV_MASK); CLEAR_PERI_REG_MASK(UART_CONF0(uart_no), UART_LINE_INV_MASK);
SET_PERI_REG_MASK(UART_CONF0(uart_no), inverse_mask); SET_PERI_REG_MASK(UART_CONF0(uart_no), inverse_mask);
} }
void void UART_SetParity(UART_Port uart_no, UART_ParityMode Parity_mode)
UART_SetParity(UART_Port uart_no, UART_ParityMode Parity_mode)
{ {
CLEAR_PERI_REG_MASK(UART_CONF0(uart_no), UART_PARITY | UART_PARITY_EN); CLEAR_PERI_REG_MASK(UART_CONF0(uart_no), UART_PARITY | UART_PARITY_EN);
@ -223,15 +212,13 @@ UART_SetParity(UART_Port uart_no, UART_ParityMode Parity_mode)
} }
} }
void void UART_SetBaudrate(UART_Port uart_no, uint32 baud_rate)
UART_SetBaudrate(UART_Port uart_no, uint32 baud_rate)
{ {
uart_div_modify(uart_no, UART_CLK_FREQ / baud_rate); uart_div_modify(uart_no, UART_CLK_FREQ / baud_rate);
} }
//only when USART_HardwareFlowControl_RTS is set , will the rx_thresh value be set. //only when USART_HardwareFlowControl_RTS is set , will the rx_thresh value be set.
void void UART_SetFlowCtrl(UART_Port uart_no, UART_HwFlowCtrl flow_ctrl, uint8 rx_thresh)
UART_SetFlowCtrl(UART_Port uart_no, UART_HwFlowCtrl flow_ctrl, uint8 rx_thresh)
{ {
if (flow_ctrl & USART_HardwareFlowControl_RTS) { if (flow_ctrl & USART_HardwareFlowControl_RTS) {
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, FUNC_U0RTS); PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, FUNC_U0RTS);
@ -249,39 +236,33 @@ UART_SetFlowCtrl(UART_Port uart_no, UART_HwFlowCtrl flow_ctrl, uint8 rx_thresh)
} }
} }
void void UART_WaitTxFifoEmpty(UART_Port uart_no) //do not use if tx flow control enabled
UART_WaitTxFifoEmpty(UART_Port uart_no) //do not use if tx flow control enabled
{ {
while (READ_PERI_REG(UART_STATUS(uart_no)) & (UART_TXFIFO_CNT << UART_TXFIFO_CNT_S)); while (READ_PERI_REG(UART_STATUS(uart_no)) & (UART_TXFIFO_CNT << UART_TXFIFO_CNT_S));
} }
void void UART_ResetFifo(UART_Port uart_no)
UART_ResetFifo(UART_Port uart_no)
{ {
SET_PERI_REG_MASK(UART_CONF0(uart_no), UART_RXFIFO_RST | UART_TXFIFO_RST); SET_PERI_REG_MASK(UART_CONF0(uart_no), UART_RXFIFO_RST | UART_TXFIFO_RST);
CLEAR_PERI_REG_MASK(UART_CONF0(uart_no), UART_RXFIFO_RST | UART_TXFIFO_RST); CLEAR_PERI_REG_MASK(UART_CONF0(uart_no), UART_RXFIFO_RST | UART_TXFIFO_RST);
} }
void void UART_ClearIntrStatus(UART_Port uart_no, uint32 clr_mask)
UART_ClearIntrStatus(UART_Port uart_no, uint32 clr_mask)
{ {
WRITE_PERI_REG(UART_INT_CLR(uart_no), clr_mask); WRITE_PERI_REG(UART_INT_CLR(uart_no), clr_mask);
} }
void void UART_SetIntrEna(UART_Port uart_no, uint32 ena_mask)
UART_SetIntrEna(UART_Port uart_no, uint32 ena_mask)
{ {
SET_PERI_REG_MASK(UART_INT_ENA(uart_no), ena_mask); SET_PERI_REG_MASK(UART_INT_ENA(uart_no), ena_mask);
} }
void void UART_intr_handler_register(void* fn, void* arg)
UART_intr_handler_register(void *fn, void *arg)
{ {
_xt_isr_attach(ETS_UART_INUM, fn, arg); _xt_isr_attach(ETS_UART_INUM, fn, arg);
} }
void void UART_SetPrintPort(UART_Port uart_no)
UART_SetPrintPort(UART_Port uart_no)
{ {
if (uart_no == 1) { if (uart_no == 1) {
os_install_putc1(uart1_write_char); os_install_putc1(uart1_write_char);
@ -290,8 +271,7 @@ UART_SetPrintPort(UART_Port uart_no)
} }
} }
void void UART_ParamConfig(UART_Port uart_no, UART_ConfigTypeDef* pUARTConfig)
UART_ParamConfig(UART_Port uart_no, UART_ConfigTypeDef *pUARTConfig)
{ {
if (uart_no == UART1) { if (uart_no == UART1) {
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO2_U, FUNC_U1TXD_BK); PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO2_U, FUNC_U1TXD_BK);
@ -314,8 +294,7 @@ UART_ParamConfig(UART_Port uart_no, UART_ConfigTypeDef *pUARTConfig)
UART_ResetFifo(uart_no); UART_ResetFifo(uart_no);
} }
void void UART_IntrConfig(UART_Port uart_no, UART_IntrConfTypeDef* pUARTIntrConf)
UART_IntrConfig(UART_Port uart_no, UART_IntrConfTypeDef *pUARTIntrConf)
{ {
uint32 reg_val = 0; uint32 reg_val = 0;
@ -336,8 +315,7 @@ UART_IntrConfig(UART_Port uart_no, UART_IntrConfTypeDef *pUARTIntrConf)
SET_PERI_REG_MASK(UART_INT_ENA(uart_no), pUARTIntrConf->UART_IntrEnMask); SET_PERI_REG_MASK(UART_INT_ENA(uart_no), pUARTIntrConf->UART_IntrEnMask);
} }
LOCAL void LOCAL void uart0_rx_intr_handler(void* para)
uart0_rx_intr_handler(void *para)
{ {
/* uart0 and uart1 intr combine togther, when interrupt occur, see reg 0x3ff20020, bit2, bit0 represents /* uart0 and uart1 intr combine togther, when interrupt occur, see reg 0x3ff20020, bit2, bit0 represents
* uart1 and uart0 respectively * uart1 and uart0 respectively
@ -386,8 +364,7 @@ uart0_rx_intr_handler(void *para)
} }
} }
void void uart_init_new(void)
uart_init_new(void)
{ {
UART_WaitTxFifoEmpty(UART0); UART_WaitTxFifoEmpty(UART0);
UART_WaitTxFifoEmpty(UART1); UART_WaitTxFifoEmpty(UART1);
@ -420,5 +397,4 @@ uart_init_new(void)
UART_SetBaudrate(UART0,74880); UART_SetBaudrate(UART0,74880);
UART_SetFlowCtrl(UART0,USART_HardwareFlowControl_None,0); UART_SetFlowCtrl(UART0,USART_HardwareFlowControl_None,0);
*/ */
} }

1
components/esp8266/include/driver/gpio.h
View File

@ -18,6 +18,7 @@
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#include "esp8266/gpio_register.h" #include "esp8266/gpio_register.h"
#define ETS_GPIO_INTR_ENABLE() _xt_isr_unmask(1 << ETS_GPIO_INUM) #define ETS_GPIO_INTR_ENABLE() _xt_isr_unmask(1 << ETS_GPIO_INUM)

1
components/esp8266/include/driver/i2c_master.h
View File

@ -16,6 +16,7 @@
#define __I2C_MASTER_H__ #define __I2C_MASTER_H__
#include "esp8266/pin_mux_register.h" #include "esp8266/pin_mux_register.h"
#define I2C_MASTER_SDA_MUX PERIPHS_IO_MUX_GPIO2_U #define I2C_MASTER_SDA_MUX PERIPHS_IO_MUX_GPIO2_U
#define I2C_MASTER_SCL_MUX PERIPHS_IO_MUX_GPIO4_U #define I2C_MASTER_SCL_MUX PERIPHS_IO_MUX_GPIO4_U
#define I2C_MASTER_SDA_GPIO 2 #define I2C_MASTER_SDA_GPIO 2

27
components/esp8266/include/driver/spi_interface.h
View File

@ -47,8 +47,7 @@ extern "C"
* @brief Support HSPI and SPI module. * @brief Support HSPI and SPI module.
* *
*/ */
typedef enum typedef enum {
{
SpiNum_SPI = 0, SpiNum_SPI = 0,
SpiNum_HSPI = 1, SpiNum_HSPI = 1,
} SpiNum; } SpiNum;
@ -57,8 +56,7 @@ typedef enum
* @brief The SPI module can work in either master or slave mode. * @brief The SPI module can work in either master or slave mode.
* *
*/ */
typedef enum typedef enum {
{
SpiMode_Master = 0, SpiMode_Master = 0,
SpiMode_Slave = 1, SpiMode_Slave = 1,
} SpiMode; } SpiMode;
@ -73,8 +71,7 @@ typedef enum
* 1 0 2 * 1 0 2
* 1 1 3 * 1 1 3
*/ */
typedef enum typedef enum {
{
SpiSubMode_0 = 0, SpiSubMode_0 = 0,
SpiSubMode_1 = 1, SpiSubMode_1 = 1,
SpiSubMode_2 = 2, SpiSubMode_2 = 2,
@ -87,8 +84,7 @@ typedef enum
* @attention Max speed 80MHz * @attention Max speed 80MHz
* *
*/ */
typedef enum typedef enum {
{
SpiSpeed_2MHz = 40 - 1, SpiSpeed_2MHz = 40 - 1,
SpiSpeed_5MHz = 16 - 1, SpiSpeed_5MHz = 16 - 1,
SpiSpeed_10MHz = 8 - 1, SpiSpeed_10MHz = 8 - 1,
@ -100,15 +96,13 @@ typedef enum
* @brief The SPI mode working speed. * @brief The SPI mode working speed.
* *
*/ */
typedef enum typedef enum {
{
SpiBitOrder_MSBFirst = 0, SpiBitOrder_MSBFirst = 0,
SpiBitOrder_LSBFirst = 1, SpiBitOrder_LSBFirst = 1,
} SpiBitOrder; } SpiBitOrder;
// @brief SPI interrupt soource defined. // @brief SPI interrupt soource defined.
typedef enum typedef enum {
{
SpiIntSrc_TransDoneEn = SPI_TRANS_DONE_EN, SpiIntSrc_TransDoneEn = SPI_TRANS_DONE_EN,
SpiIntSrc_WrStaDoneEn = SPI_SLV_WR_STA_DONE_EN, SpiIntSrc_WrStaDoneEn = SPI_SLV_WR_STA_DONE_EN,
SpiIntSrc_RdStaDoneEn = SPI_SLV_RD_STA_DONE_EN, SpiIntSrc_RdStaDoneEn = SPI_SLV_RD_STA_DONE_EN,
@ -117,8 +111,7 @@ typedef enum
} SpiIntSrc; } SpiIntSrc;
// @brief SPI CS pin. // @brief SPI CS pin.
typedef enum typedef enum {
{
SpiPinCS_0 = 0, SpiPinCS_0 = 0,
SpiPinCS_1 = 1, SpiPinCS_1 = 1,
SpiPinCS_2 = 2, SpiPinCS_2 = 2,
@ -127,8 +120,7 @@ typedef enum
/** /**
* @brief SPI attribute * @brief SPI attribute
*/ */
typedef struct typedef struct {
{
SpiMode mode; ///< Master or slave mode SpiMode mode; ///< Master or slave mode
SpiSubMode subMode; ///< SPI SPI_CPOL SPI_CPHA mode SpiSubMode subMode; ///< SPI SPI_CPOL SPI_CPHA mode
SpiSpeed speed; ///< SPI Clock SpiSpeed speed; ///< SPI Clock
@ -138,8 +130,7 @@ typedef struct
/** /**
* @brief SPI attribute * @brief SPI attribute
*/ */
typedef struct typedef struct {
{
uint16_t cmd; ///< Command value uint16_t cmd; ///< Command value
uint8_t cmdLen; ///< Command byte length uint8_t cmdLen; ///< Command byte length
uint32_t* addr; ///< Point to address value uint32_t* addr; ///< Point to address value