espressif/ESP8266_RTOS_SDK
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feat(driver): Use astyle to format the code

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This commit is contained in:
Wu Jian Gang
2018-05-19 22:55:14 +08:00
parent ae6c134ec4
commit a08d0711a4
11 changed files with 305 additions and 290 deletions
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101
components/esp8266/driver/spi_interface.c
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@ -36,7 +36,7 @@ extern "C"
// Show the spi registers.
#define SHOWDEBUG
void __ShowRegValue(const char * func, uint32_t line)
void __ShowRegValue(const char* func, uint32_t line)
{
#ifndef SHOWDEBUG
int i;
@ -61,6 +61,7 @@ void __ShowRegValue(const char * func, uint32_t line)
printf(" ADDR[0x%08x],Value[0x%08x]\r\n", regAddr, READ_PERI_REG(regAddr));
regAddr += 4;
}
#endif
}
@ -74,29 +75,33 @@ void __ShowRegValue(const char * func, uint32_t line)
void ICACHE_FLASH_ATTR SPIInit(SpiNum spiNum, SpiAttr* pAttr)
{
if ((spiNum > SpiNum_HSPI)
|| (NULL == pAttr)) {
|| (NULL == pAttr)) {
return;
}
// SPI_CPOL & SPI_CPHA
switch (pAttr->subMode) {
case SpiSubMode_1:
CLEAR_PERI_REG_MASK(SPI_PIN(spiNum), SPI_IDLE_EDGE);
SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_CK_OUT_EDGE); // CHPA_FALLING_EDGE_SAMPLE
break;
case SpiSubMode_2:
SET_PERI_REG_MASK(SPI_PIN(spiNum), SPI_IDLE_EDGE);
SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_CK_OUT_EDGE); // CHPA_FALLING_EDGE_SAMPLE
break;
case SpiSubMode_3:
SET_PERI_REG_MASK(SPI_PIN(spiNum), SPI_IDLE_EDGE);
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_CK_OUT_EDGE);
break;
case SpiSubMode_0:
default:
CLEAR_PERI_REG_MASK(SPI_PIN(spiNum), SPI_IDLE_EDGE);
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_CK_OUT_EDGE);
// To do nothing
break;
case SpiSubMode_1:
CLEAR_PERI_REG_MASK(SPI_PIN(spiNum), SPI_IDLE_EDGE);
SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_CK_OUT_EDGE); // CHPA_FALLING_EDGE_SAMPLE
break;
case SpiSubMode_2:
SET_PERI_REG_MASK(SPI_PIN(spiNum), SPI_IDLE_EDGE);
SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_CK_OUT_EDGE); // CHPA_FALLING_EDGE_SAMPLE
break;
case SpiSubMode_3:
SET_PERI_REG_MASK(SPI_PIN(spiNum), SPI_IDLE_EDGE);
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_CK_OUT_EDGE);
break;
case SpiSubMode_0:
default:
CLEAR_PERI_REG_MASK(SPI_PIN(spiNum), SPI_IDLE_EDGE);
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_CK_OUT_EDGE);
// To do nothing
break;
}
// SPI bit order
@ -119,10 +124,12 @@ void ICACHE_FLASH_ATTR SPIInit(SpiNum spiNum, SpiAttr* pAttr)
// SPI mode type
CLEAR_PERI_REG_MASK(SPI_SLAVE(spiNum), SPI_SLAVE_MODE);
// SPI Send buffer
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO_HIGHPART );// By default slave send buffer C0-C7
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO_HIGHPART); // By default slave send buffer C0-C7
// SPI Speed
if (1 < (pAttr->speed)) {
CLEAR_PERI_REG_MASK(SPI_CLOCK(spiNum), SPI_CLK_EQU_SYSCLK);
if (spiNum == SpiNum_HSPI) {
CLEAR_PERI_REG_MASK(PERIPHS_IO_MUX_CONF_U, SPI1_CLK_EQU_SYS_CLK);
}
@ -134,8 +141,9 @@ void ICACHE_FLASH_ATTR SPIInit(SpiNum spiNum, SpiAttr* pAttr)
} else {
WRITE_PERI_REG(SPI_CLOCK(spiNum), SPI_CLK_EQU_SYSCLK); // 80Mhz speed
}
// By default format:CMD+ADDR+DATA
SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_CS_SETUP | SPI_CS_HOLD | SPI_USR_MOSI );
SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_CS_SETUP | SPI_CS_HOLD | SPI_USR_MOSI);
//delay num
SET_PERI_REG_MASK(SPI_CTRL2(spiNum), ((0x1 & SPI_MISO_DELAY_NUM) << SPI_MISO_DELAY_NUM_S));
@ -186,6 +194,7 @@ void ICACHE_FLASH_ATTR SPIMasterCfgAddr(SpiNum spiNum, uint32_t addr)
if (spiNum > SpiNum_HSPI) {
return;
}
// Set address
WRITE_PERI_REG(SPI_ADDR(spiNum), addr);
}
@ -199,6 +208,7 @@ void ICACHE_FLASH_ATTR SPIMasterCfgCmd(SpiNum spiNum, uint32_t cmd)
if (spiNum > SpiNum_HSPI) {
return;
}
// SPI_USER2 bit28-31 is cmd length,cmd bit length is value(0-15)+1,
// bit15-0 is cmd value.
SET_PERI_REG_BITS(SPI_USER2(spiNum), SPI_USR_COMMAND_VALUE, cmd, SPI_USR_COMMAND_VALUE_S);
@ -211,13 +221,17 @@ void ICACHE_FLASH_ATTR SPIMasterCfgCmd(SpiNum spiNum, uint32_t cmd)
int ICACHE_FLASH_ATTR SPIMasterSendData(SpiNum spiNum, SpiData* pInData)
{
char idx = 0;
if ((spiNum > SpiNum_HSPI)
|| (NULL == pInData)
|| (64 < pInData->dataLen)) {
|| (NULL == pInData)
|| (64 < pInData->dataLen)) {
return -1;
}
uint32_t *value = pInData->data;
uint32_t* value = pInData->data;
while (READ_PERI_REG(SPI_CMD(spiNum))&SPI_USR);
// Set command by user.
if (pInData->cmdLen != 0) {
// Max command length 16 bits.
@ -232,6 +246,7 @@ int ICACHE_FLASH_ATTR SPIMasterSendData(SpiNum spiNum, SpiData* pInData)
SET_PERI_REG_BITS(SPI_USER2(spiNum), SPI_USR_COMMAND_BITLEN,
0, SPI_USR_COMMAND_BITLEN_S);
}
// Set Address by user.
if (pInData->addrLen == 0) {
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_ADDR);
@ -241,6 +256,7 @@ int ICACHE_FLASH_ATTR SPIMasterSendData(SpiNum spiNum, SpiData* pInData)
if (NULL == pInData->addr) {
return -1;
}
SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_ADDR_BITLEN,
((pInData->addrLen << 3) - 1), SPI_USR_ADDR_BITLEN_S);
// Enable address
@ -248,18 +264,22 @@ int ICACHE_FLASH_ATTR SPIMasterSendData(SpiNum spiNum, SpiData* pInData)
// Load address
SPIMasterCfgAddr(spiNum, *pInData->addr);
}
// Set data by user.
if (pInData->dataLen != 0) {
if (NULL == value) {
return -1;
}
// Enable MOSI
SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI);
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO);
// Load send buffer
do {
WRITE_PERI_REG((SPI_W0(spiNum) + (idx << 2)), *value++);
} while (++idx < (pInData->dataLen / 4));
// Set data send buffer length.Max data length 64 bytes.
SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_MOSI_BITLEN, ((pInData->dataLen << 3) - 1), SPI_USR_MOSI_BITLEN_S);
} else {
@ -268,6 +288,7 @@ int ICACHE_FLASH_ATTR SPIMasterSendData(SpiNum spiNum, SpiData* pInData)
SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_MOSI_BITLEN,
0, SPI_USR_MOSI_BITLEN_S);
}
// Start send data
SET_PERI_REG_MASK(SPI_CMD(spiNum), SPI_USR);
@ -282,13 +303,16 @@ int ICACHE_FLASH_ATTR SPIMasterSendData(SpiNum spiNum, SpiData* pInData)
int ICACHE_FLASH_ATTR SPIMasterRecvData(SpiNum spiNum, SpiData* pOutData)
{
char idx = 0;
if ((spiNum > SpiNum_HSPI)
|| (NULL == pOutData)) {
|| (NULL == pOutData)) {
return -1;
}
uint32_t *value = pOutData->data;
uint32_t* value = pOutData->data;
while (READ_PERI_REG(SPI_CMD(spiNum))&SPI_USR);
// Set command by user.
if (pOutData->cmdLen != 0) {
// Max command length 16 bits.
@ -303,6 +327,7 @@ int ICACHE_FLASH_ATTR SPIMasterRecvData(SpiNum spiNum, SpiData* pOutData)
SET_PERI_REG_BITS(SPI_USER2(spiNum), SPI_USR_COMMAND_BITLEN,
0, SPI_USR_COMMAND_BITLEN_S);
}
// Set Address by user.
if (pOutData->addrLen == 0) {
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_ADDR);
@ -312,6 +337,7 @@ int ICACHE_FLASH_ATTR SPIMasterRecvData(SpiNum spiNum, SpiData* pOutData)
if (NULL == pOutData->addr) {
return -1;
}
SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_ADDR_BITLEN,
((pOutData->addrLen << 3) - 1), SPI_USR_ADDR_BITLEN_S);
// Enable address
@ -319,11 +345,13 @@ int ICACHE_FLASH_ATTR SPIMasterRecvData(SpiNum spiNum, SpiData* pOutData)
// Load address
SPIMasterCfgAddr(spiNum, *pOutData->addr);
}
// Set data by user.
if (pOutData->dataLen != 0) {
if (NULL == value) {
return -1;
}
// Clear MOSI enable
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI);
// Enable MOSI
@ -339,13 +367,16 @@ int ICACHE_FLASH_ATTR SPIMasterRecvData(SpiNum spiNum, SpiData* pOutData)
//CLEAR FIFO DATA
int fifo_idx = 0;
do {
WRITE_PERI_REG(SPI_W0(spiNum) + (fifo_idx << 2), 0);
} while (++fifo_idx < (pOutData->dataLen / 4));
// Start send data
SET_PERI_REG_MASK(SPI_CMD(spiNum), SPI_USR);
while (READ_PERI_REG(SPI_CMD(spiNum))&SPI_USR);
// Read data out
do {
*pOutData->data++ = READ_PERI_REG(SPI_W0(spiNum) + (idx << 2));
@ -359,15 +390,18 @@ int ICACHE_FLASH_ATTR SPIMasterRecvData(SpiNum spiNum, SpiData* pOutData)
* @brief Load data to send buffer by slave mode.
*
*/
int ICACHE_FLASH_ATTR SPISlaveSendData(SpiNum spiNum, uint32_t *pInData, uint8_t outLen)
int ICACHE_FLASH_ATTR SPISlaveSendData(SpiNum spiNum, uint32_t* pInData, uint8_t outLen)
{
if (NULL == pInData) {
return -1;
}
char i;
for (i = 0; i < outLen; ++i) {
WRITE_PERI_REG((SPI_W8(spiNum) + (i << 2)), *pInData++);
}
return 0;
}
@ -388,8 +422,8 @@ int ICACHE_FLASH_ATTR SPISlaveRecvData(SpiNum spiNum, void(*isrFunc)(void*))
// Maybe enable slave transmission liston
SET_PERI_REG_MASK(SPI_CMD(spiNum), SPI_USR);
//
_xt_isr_attach(ETS_SPI_INUM, isrFunc, NULL);
// ETS_SPI_INTR_ATTACH(isrFunc, NULL);
_xt_isr_attach(ETS_SPI_INUM, isrFunc, NULL);
// ETS_SPI_INTR_ATTACH(isrFunc, NULL);
// Enable isr
ETS_SPI_INTR_ENABLE();
@ -408,7 +442,9 @@ void ICACHE_FLASH_ATTR SPIMasterSendStatus(SpiNum spiNum, uint8_t data)
if (spiNum > SpiNum_HSPI) {
return;
}
while (READ_PERI_REG(SPI_CMD(spiNum))&SPI_USR);
// Enable MOSI
SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI);
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO | SPI_USR_DUMMY | SPI_USR_ADDR);
@ -439,6 +475,7 @@ int ICACHE_FLASH_ATTR SPIMasterRecvStatus(SpiNum spiNum)
}
while (READ_PERI_REG(SPI_CMD(spiNum))&SPI_USR);
// Enable MISO
SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO);
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI | SPI_USR_DUMMY | SPI_USR_ADDR);
@ -471,6 +508,7 @@ void ICACHE_FLASH_ATTR SPICsPinSelect(SpiNum spiNum, SpiPinCS pinCs)
if (spiNum > SpiNum_HSPI) {
return;
}
// clear select
SET_PERI_REG_BITS(SPI_PIN(spiNum), 3, 0, 0);
SET_PERI_REG_MASK(SPI_PIN(spiNum), pinCs);
@ -485,6 +523,7 @@ void ICACHE_FLASH_ATTR SPIIntEnable(SpiNum spiNum, SpiIntSrc intSrc)
if (spiNum > SpiNum_HSPI) {
return;
}
SET_PERI_REG_MASK(SPI_SLAVE(spiNum), intSrc);
}
@ -497,6 +536,7 @@ void ICACHE_FLASH_ATTR SPIIntDisable(SpiNum spiNum, SpiIntSrc intSrc)
if (spiNum > SpiNum_HSPI) {
return;
}
CLEAR_PERI_REG_MASK(SPI_SLAVE(spiNum), intSrc);
}
@ -509,6 +549,7 @@ void ICACHE_FLASH_ATTR SPIIntClear(SpiNum spiNum)
if (spiNum > SpiNum_HSPI) {
return;
}
CLEAR_PERI_REG_MASK(SPI_SLAVE(spiNum), SpiIntSrc_TransDoneEn
| SpiIntSrc_WrStaDoneEn
| SpiIntSrc_RdStaDoneEn