Merge branch 'feature/support_40MHz_XTAL' into 'master'

feat(esp8266): Support 40MHz XTAL

See merge request sdk/ESP8266_RTOS_SDK!1555

components/bootloader_support/src/bootloader_init.c

@@ -553,7 +553,24 @@ void __assert_func(const char *file, int line, const char *func, const char *exp
 #include "esp8266/pin_mux_register.h"
 #include "esp8266/rom_functions.h"
 
-#define BOOTLOADER_CONSOLE_CLK_FREQ 52 * 1000 * 1000
+#define BOOTLOADER_CONSOLE_CLK_FREQ ((CONFIG_ESP8266_XTAL_FREQ * 2) * 1000 * 1000)
+
+/**
+ * XTAL=26MHz, UART baudrate=74880 (default)
+ * XTAL=40MHz, UART baudrate=115200 (default)
+ */
+
+#if CONFIG_ESP_CONSOLE_UART_NUM == 0
+#  if CONFIG_ESP8266_XTAL_FREQ == 26 && CONFIG_ESP_CONSOLE_UART_BAUDRATE == 74880
+#    define ESP8266_MODIFY_UART_BAUDRATE 0
+#  elif CONFIG_ESP8266_XTAL_FREQ == 40 && CONFIG_ESP_CONSOLE_UART_BAUDRATE == 115200
+#    define ESP8266_MODIFY_UART_BAUDRATE 0
+#  endif
+#endif
+
+#ifndef ESP8266_MODIFY_UART_BAUDRATE
+#  define ESP8266_MODIFY_UART_BAUDRATE 1
+#endif
 
 extern int _bss_start;
 extern int _bss_end;
@@ -595,7 +612,19 @@ static void uart_console_configure(void)
     CLEAR_PERI_REG_MASK(UART_CONF0(CONFIG_ESP_CONSOLE_UART_NUM), UART_RXFIFO_RST | UART_TXFIFO_RST);
 #endif
 
-#ifdef CONFIG_ESP_CONSOLE_UART_BAUDRATE
+#if ESP8266_MODIFY_UART_BAUDRATE
+
+    /* Wait UART TX over */
+
+    while(1) {
+        int uart_status = REG_READ(UART_STATUS(CONFIG_ESP_CONSOLE_UART_NUM));
+        int tx_bytes = (uart_status >> UART_TXFIFO_CNT_S) & UART_TXFIFO_CNT;
+
+        if (!tx_bytes) {
+            break;
+        }
+    }
+
     uart_div_modify(CONFIG_ESP_CONSOLE_UART_NUM, BOOTLOADER_CONSOLE_CLK_FREQ / CONFIG_ESP_CONSOLE_UART_BAUDRATE);
 #endif
 }

components/esp8266/Kconfig

@@ -10,6 +10,26 @@ config ESP8266_NMI_WDT
         Enable this non-mask watch dog can help users to debug blocking code
         when CPU is at critical state(disable interrupt).
 
+
+choice ESP8266_XTAL_FREQ_SEL
+    prompt "Main XTAL frequency"
+    default ESP8266_XTAL_FREQ_26
+    help
+        ESP8266 currently supports the following XTAL frequencies:
+
+        - 26 MHz
+        - 40 MHz
+    config ESP8266_XTAL_FREQ_40
+        bool "40 MHz"
+    config ESP8266_XTAL_FREQ_26
+        bool "26 MHz"
+endchoice
+
+config ESP8266_XTAL_FREQ
+    int
+    default 40 if ESP8266_XTAL_FREQ_40
+    default 26 if ESP8266_XTAL_FREQ_26
+
 choice ESP8266_DEFAULT_CPU_FREQ_MHZ
     prompt "CPU frequency"
     default ESP8266_DEFAULT_CPU_FREQ_160

components/esp8266/include/esp_phy_init.h

@@ -14,7 +14,7 @@
 
 #pragma once
 #include <stdint.h>
-
+#include "sdkconfig.h"
 #include "esp_err.h"
 
 #ifdef __cplusplus
@@ -75,6 +75,15 @@ typedef enum {
     PHY_MODULE_COUNT        //!< Number of items
 } phy_rf_module_t;
 
+/**
+ * @brief Outside XTAL 40MHz: 0, 26MHz: 1
+ */
+#ifdef CONFIG_ESP8266_XTAL_FREQ_40
+#define ESP8266_XTAL_FLAG   (0)
+#elif defined(CONFIG_ESP8266_XTAL_FREQ_26)
+#define ESP8266_XTAL_FLAG   (1)
+#endif
+
 /**
  * @brief Get PHY init data
  *

components/esp8266/include/esp_private/phy_init_data.h

@@ -14,8 +14,8 @@
 
 #pragma once
 
-#include "esp_phy_init.h"
 #include "sdkconfig.h"
+#include "esp_phy_init.h"
 
 // constrain a value between 'low' and 'high', inclusive
 #define LIMIT(val, low, high) ((val < low) ? low : (val > high) ? high : val)
@@ -75,7 +75,7 @@ static const esp_phy_init_data_t phy_init_data= { {
         0x03,
         0x04,
         0x05,
-        0x01,
+        ESP8266_XTAL_FLAG,
         0x00,
         0x00,
         0x00,

components/esp8266/include/esp_system.h

@@ -27,7 +27,7 @@
 extern "C" {
 #endif
 
-#define CRYSTAL_USED 26
+#define CRYSTAL_USED CONFIG_ESP8266_XTAL_FREQ
 
 typedef enum {
     ESP_MAC_WIFI_STA,