mirror of
https://github.com/espressif/ESP8266_RTOS_SDK.git
synced 2025-05-31 15:41:02 +08:00
1.add gpio/pin_mux/spi/timer/uart register define headers;
2.add gpio driver;
This commit is contained in:
Espressif Systems
44
examples/dirver_lib/driver/Makefile
Normal file
44
examples/dirver_lib/driver/Makefile
Normal file
@ -0,0 +1,44 @@
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#############################################################
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||||
# Required variables for each makefile
|
||||
# Discard this section from all parent makefiles
|
||||
# Expected variables (with automatic defaults):
|
||||
# CSRCS (all "C" files in the dir)
|
||||
# SUBDIRS (all subdirs with a Makefile)
|
||||
# GEN_LIBS - list of libs to be generated ()
|
||||
# GEN_IMAGES - list of images to be generated ()
|
||||
# COMPONENTS_xxx - a list of libs/objs in the form
|
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# subdir/lib to be extracted and rolled up into
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# a generated lib/image xxx.a ()
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#
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ifndef PDIR
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GEN_LIBS = libdriver.a
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endif
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||||
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#############################################################
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# Configuration i.e. compile options etc.
|
||||
# Target specific stuff (defines etc.) goes in here!
|
||||
# Generally values applying to a tree are captured in the
|
||||
# makefile at its root level - these are then overridden
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# for a subtree within the makefile rooted therein
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#
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#DEFINES +=
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||||
#############################################################
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||||
# Recursion Magic - Don't touch this!!
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||||
#
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||||
# Each subtree potentially has an include directory
|
||||
# corresponding to the common APIs applicable to modules
|
||||
# rooted at that subtree. Accordingly, the INCLUDE PATH
|
||||
# of a module can only contain the include directories up
|
||||
# its parent path, and not its siblings
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||||
#
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||||
# Required for each makefile to inherit from the parent
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#
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INCLUDES := $(INCLUDES) -I $(PDIR)include
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INCLUDES += -I ./
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PDIR := ../$(PDIR)
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sinclude $(PDIR)Makefile
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207
examples/dirver_lib/driver/gpio.c
Normal file
207
examples/dirver_lib/driver/gpio.c
Normal file
@ -0,0 +1,207 @@
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/*
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* Copyright (C) 2014 -2016 Espressif System
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*
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*/
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#include "espressif/esp_common.h"
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#include "freertos/portmacro.h"
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#include "gpio.h"
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void ICACHE_FLASH_ATTR
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gpio_config(GPIO_ConfigTypeDef *pGPIOConfig)
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{
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uint16 gpio_pin_mask = pGPIOConfig->GPIO_Pin;
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uint32 io_reg;
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uint8 io_num = 0;
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uint32 pin_reg;
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if (pGPIOConfig->GPIO_Mode == GPIO_Mode_Input) {
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GPIO_AS_INPUT(gpio_pin_mask);
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} else if (pGPIOConfig->GPIO_Mode == GPIO_Mode_Output) {
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GPIO_AS_OUTPUT(gpio_pin_mask);
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}
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do {
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if ((gpio_pin_mask >> io_num) & 0x1) {
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io_reg = GPIO_PIN_REG(io_num);
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if ((0x1 << io_num) & (GPIO_Pin_0 | GPIO_Pin_2 | GPIO_Pin_4 | GPIO_Pin_5)) {
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PIN_FUNC_SELECT(io_reg, 0);
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} else {
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PIN_FUNC_SELECT(io_reg, 3);
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}
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if (pGPIOConfig->GPIO_Pullup) {
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PIN_PULLUP_EN(io_reg);
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} else {
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PIN_PULLUP_DIS(io_reg);
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}
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if (pGPIOConfig->GPIO_Mode == GPIO_Mode_Out_OD) {
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portENTER_CRITICAL();
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pin_reg = GPIO_REG_READ(GPIO_PIN_ADDR(io_num));
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pin_reg &= (~GPIO_PIN_DRIVER_MASK);
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pin_reg |= (GPIO_PAD_DRIVER_ENABLE << GPIO_PIN_DRIVER_LSB);
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GPIO_REG_WRITE(GPIO_PIN_ADDR(io_num), pin_reg);
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portEXIT_CRITICAL();
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} else if (pGPIOConfig->GPIO_Mode == GPIO_Mode_Sigma_Delta) {
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portENTER_CRITICAL();
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pin_reg = GPIO_REG_READ(GPIO_PIN_ADDR(io_num));
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pin_reg &= (~GPIO_PIN_SOURCE_MASK);
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pin_reg |= (0x1 << GPIO_PIN_SOURCE_LSB);
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GPIO_REG_WRITE(GPIO_PIN_ADDR(io_num), pin_reg);
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GPIO_REG_WRITE(GPIO_SIGMA_DELTA_ADDRESS, SIGMA_DELTA_ENABLE);
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portEXIT_CRITICAL();
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}
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gpio_pin_intr_state_set(io_num, pGPIOConfig->GPIO_IntrType);
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}
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io_num++;
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} while (io_num < 16);
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}
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/*
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* Change GPIO pin output by setting, clearing, or disabling pins.
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* In general, it is expected that a bit will be set in at most one
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* of these masks. If a bit is clear in all masks, the output state
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* remains unchanged.
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*
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* There is no particular ordering guaranteed; so if the order of
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* writes is significant, calling code should divide a single call
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* into multiple calls.
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*/
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void ICACHE_FLASH_ATTR
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gpio_output_conf(uint32 set_mask, uint32 clear_mask, uint32 enable_mask, uint32 disable_mask)
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{
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GPIO_REG_WRITE(GPIO_OUT_W1TS_ADDRESS, set_mask);
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GPIO_REG_WRITE(GPIO_OUT_W1TC_ADDRESS, clear_mask);
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GPIO_REG_WRITE(GPIO_ENABLE_W1TS_ADDRESS, enable_mask);
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GPIO_REG_WRITE(GPIO_ENABLE_W1TC_ADDRESS, disable_mask);
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}
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/*
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* Sample the value of GPIO input pins and returns a bitmask.
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*/
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uint32 ICACHE_FLASH_ATTR
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gpio_input_get(void)
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{
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return GPIO_REG_READ(GPIO_IN_ADDRESS);
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}
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/*
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* Register an application-specific interrupt handler for GPIO pin
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* interrupts. Once the interrupt handler is called, it will not
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* be called again until after a call to gpio_intr_ack. Any GPIO
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* interrupts that occur during the interim are masked.
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*
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* The application-specific handler is called with a mask of
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* pending GPIO interrupts. After processing pin interrupts, the
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* application-specific handler may wish to use gpio_intr_pending
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* to check for any additional pending interrupts before it returns.
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*/
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void ICACHE_FLASH_ATTR
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gpio_intr_handler_register(void *fn)
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{
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_xt_isr_attach(ETS_GPIO_INUM, fn);
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}
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/*
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only highlevel and lowlevel intr can use for wakeup
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*/
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void ICACHE_FLASH_ATTR
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gpio_pin_wakeup_enable(uint32 i, GPIO_INT_TYPE intr_state)
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{
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uint32 pin_reg;
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if ((intr_state == GPIO_PIN_INTR_LOLEVEL) || (intr_state == GPIO_PIN_INTR_HILEVEL)) {
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portENTER_CRITICAL();
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pin_reg = GPIO_REG_READ(GPIO_PIN_ADDR(i));
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pin_reg &= (~GPIO_PIN_INT_TYPE_MASK);
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pin_reg |= (intr_state << GPIO_PIN_INT_TYPE_LSB);
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pin_reg |= GPIO_PIN_WAKEUP_ENABLE_SET(GPIO_WAKEUP_ENABLE);
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GPIO_REG_WRITE(GPIO_PIN_ADDR(i), pin_reg);
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portEXIT_CRITICAL();
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}
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}
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void ICACHE_FLASH_ATTR
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gpio_pin_wakeup_disable(void)
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{
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uint8 i;
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uint32 pin_reg;
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for (i = 0; i < GPIO_PIN_COUNT; i++) {
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pin_reg = GPIO_REG_READ(GPIO_PIN_ADDR(i));
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if (pin_reg & GPIO_PIN_WAKEUP_ENABLE_MASK) {
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pin_reg &= (~GPIO_PIN_INT_TYPE_MASK);
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pin_reg |= (GPIO_PIN_INTR_DISABLE << GPIO_PIN_INT_TYPE_LSB);
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pin_reg &= ~(GPIO_PIN_WAKEUP_ENABLE_SET(GPIO_WAKEUP_ENABLE));
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GPIO_REG_WRITE(GPIO_PIN_ADDR(i), pin_reg);
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}
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}
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}
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void ICACHE_FLASH_ATTR
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gpio_pin_intr_state_set(uint32 i, GPIO_INT_TYPE intr_state)
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{
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uint32 pin_reg;
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portENTER_CRITICAL();
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pin_reg = GPIO_REG_READ(GPIO_PIN_ADDR(i));
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pin_reg &= (~GPIO_PIN_INT_TYPE_MASK);
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pin_reg |= (intr_state << GPIO_PIN_INT_TYPE_LSB);
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GPIO_REG_WRITE(GPIO_PIN_ADDR(i), pin_reg);
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portEXIT_CRITICAL();
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}
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void ICACHE_FLASH_ATTR
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gpio16_output_conf(void)
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{
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WRITE_PERI_REG(PAD_XPD_DCDC_CONF,
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(READ_PERI_REG(PAD_XPD_DCDC_CONF) & 0xffffffbc) | (uint32)0x1); // mux configuration for XPD_DCDC to output rtc_gpio0
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WRITE_PERI_REG(RTC_GPIO_CONF,
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(READ_PERI_REG(RTC_GPIO_CONF) & (uint32)0xfffffffe) | (uint32)0x0); //mux configuration for out enable
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WRITE_PERI_REG(RTC_GPIO_ENABLE,
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(READ_PERI_REG(RTC_GPIO_ENABLE) & (uint32)0xfffffffe) | (uint32)0x1); //out enable
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}
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void ICACHE_FLASH_ATTR
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gpio16_output_set(uint8 value)
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{
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WRITE_PERI_REG(RTC_GPIO_OUT,
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(READ_PERI_REG(RTC_GPIO_OUT) & (uint32)0xfffffffe) | (uint32)(value & 1));
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}
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void ICACHE_FLASH_ATTR
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gpio16_input_conf(void)
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{
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WRITE_PERI_REG(PAD_XPD_DCDC_CONF,
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(READ_PERI_REG(PAD_XPD_DCDC_CONF) & 0xffffffbc) | (uint32)0x1); // mux configuration for XPD_DCDC and rtc_gpio0 connection
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WRITE_PERI_REG(RTC_GPIO_CONF,
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(READ_PERI_REG(RTC_GPIO_CONF) & (uint32)0xfffffffe) | (uint32)0x0); //mux configuration for out enable
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WRITE_PERI_REG(RTC_GPIO_ENABLE,
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READ_PERI_REG(RTC_GPIO_ENABLE) & (uint32)0xfffffffe); //out disable
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}
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uint8 ICACHE_FLASH_ATTR
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gpio16_input_get(void)
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{
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return (uint8)(READ_PERI_REG(RTC_GPIO_IN_DATA) & 1);
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}
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121
examples/dirver_lib/include/gpio.h
Normal file
121
examples/dirver_lib/include/gpio.h
Normal file
@ -0,0 +1,121 @@
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/*
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* Copyright (C) 2014 -2016 Espressif System
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*
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*/
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#ifndef __GPIO_H__
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#define __GPIO_H__
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#define GPIO_Pin_0 (BIT(0)) /* Pin 0 selected */
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#define GPIO_Pin_1 (BIT(1)) /* Pin 1 selected */
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#define GPIO_Pin_2 (BIT(2)) /* Pin 2 selected */
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#define GPIO_Pin_3 (BIT(3)) /* Pin 3 selected */
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#define GPIO_Pin_4 (BIT(4)) /* Pin 4 selected */
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#define GPIO_Pin_5 (BIT(5)) /* Pin 5 selected */
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#define GPIO_Pin_6 (BIT(6)) /* Pin 6 selected */
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#define GPIO_Pin_7 (BIT(7)) /* Pin 7 selected */
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#define GPIO_Pin_8 (BIT(8)) /* Pin 8 selected */
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#define GPIO_Pin_9 (BIT(9)) /* Pin 9 selected */
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#define GPIO_Pin_10 (BIT(10)) /* Pin 10 selected */
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#define GPIO_Pin_11 (BIT(11)) /* Pin 11 selected */
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#define GPIO_Pin_12 (BIT(12)) /* Pin 12 selected */
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#define GPIO_Pin_13 (BIT(13)) /* Pin 13 selected */
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#define GPIO_Pin_14 (BIT(14)) /* Pin 14 selected */
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#define GPIO_Pin_15 (BIT(15)) /* Pin 15 selected */
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#define GPIO_Pin_All (0xFFFF) /* All pins selected */
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#define GPIO_PIN_REG_0 PERIPHS_IO_MUX_GPIO0_U
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#define GPIO_PIN_REG_1 PERIPHS_IO_MUX_U0TXD_U
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#define GPIO_PIN_REG_2 PERIPHS_IO_MUX_GPIO2_U
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#define GPIO_PIN_REG_3 PERIPHS_IO_MUX_U0RXD_U
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#define GPIO_PIN_REG_4 PERIPHS_IO_MUX_GPIO4_U
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#define GPIO_PIN_REG_5 PERIPHS_IO_MUX_GPIO5_U
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#define GPIO_PIN_REG_6 PERIPHS_IO_MUX_SD_CLK_U
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#define GPIO_PIN_REG_7 PERIPHS_IO_MUX_SD_DATA0_U
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#define GPIO_PIN_REG_8 PERIPHS_IO_MUX_SD_DATA1_U
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#define GPIO_PIN_REG_9 PERIPHS_IO_MUX_SD_DATA2_U
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#define GPIO_PIN_REG_10 PERIPHS_IO_MUX_SD_DATA3_U
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#define GPIO_PIN_REG_11 PERIPHS_IO_MUX_SD_CMD_U
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#define GPIO_PIN_REG_12 PERIPHS_IO_MUX_MTDI_U
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#define GPIO_PIN_REG_13 PERIPHS_IO_MUX_MTCK_U
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#define GPIO_PIN_REG_14 PERIPHS_IO_MUX_MTMS_U
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#define GPIO_PIN_REG_15 PERIPHS_IO_MUX_MTDO_U
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#define GPIO_PIN_REG(i) \
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(i==0) ? GPIO_PIN_REG_0: \
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(i==1) ? GPIO_PIN_REG_1: \
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(i==2) ? GPIO_PIN_REG_2: \
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(i==3) ? GPIO_PIN_REG_3: \
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(i==4) ? GPIO_PIN_REG_4: \
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(i==5) ? GPIO_PIN_REG_5: \
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(i==6) ? GPIO_PIN_REG_6: \
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(i==7) ? GPIO_PIN_REG_7: \
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(i==8) ? GPIO_PIN_REG_8: \
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(i==9) ? GPIO_PIN_REG_9: \
|
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(i==10)? GPIO_PIN_REG_10: \
|
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(i==11)? GPIO_PIN_REG_11: \
|
||||
(i==12)? GPIO_PIN_REG_12: \
|
||||
(i==13)? GPIO_PIN_REG_13: \
|
||||
(i==14)? GPIO_PIN_REG_14: \
|
||||
GPIO_PIN_REG_15
|
||||
|
||||
#define GPIO_PIN_ADDR(i) (GPIO_PIN0_ADDRESS + i*4)
|
||||
|
||||
#define GPIO_ID_IS_PIN_REGISTER(reg_id) \
|
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((reg_id >= GPIO_ID_PIN0) && (reg_id <= GPIO_ID_PIN(GPIO_PIN_COUNT-1)))
|
||||
|
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#define GPIO_REGID_TO_PINIDX(reg_id) ((reg_id) - GPIO_ID_PIN0)
|
||||
|
||||
typedef enum {
|
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GPIO_PIN_INTR_DISABLE = 0,
|
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GPIO_PIN_INTR_POSEDGE = 1,
|
||||
GPIO_PIN_INTR_NEGEDGE = 2,
|
||||
GPIO_PIN_INTR_ANYEGDE = 3,
|
||||
GPIO_PIN_INTR_LOLEVEL = 4,
|
||||
GPIO_PIN_INTR_HILEVEL = 5
|
||||
} GPIO_INT_TYPE;
|
||||
|
||||
typedef enum {
|
||||
GPIO_Mode_Input = 0x0,
|
||||
GPIO_Mode_Out_OD,
|
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GPIO_Mode_Output ,
|
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GPIO_Mode_Sigma_Delta ,
|
||||
} GPIOMode_TypeDef;
|
||||
|
||||
typedef enum {
|
||||
GPIO_PullUp_DIS = 0x0,
|
||||
GPIO_PullUp_EN = 0x1,
|
||||
} GPIO_Pullup_IF;
|
||||
|
||||
typedef struct {
|
||||
uint16 GPIO_Pin;
|
||||
GPIOMode_TypeDef GPIO_Mode;
|
||||
GPIO_Pullup_IF GPIO_Pullup;
|
||||
GPIO_INT_TYPE GPIO_IntrType;
|
||||
} GPIO_ConfigTypeDef;
|
||||
|
||||
#define GPIO_OUTPUT_SET(gpio_no, bit_value) \
|
||||
gpio_output_conf(bit_value<<gpio_no, ((~bit_value)&0x01)<<gpio_no, 1<<gpio_no, 0)
|
||||
|
||||
#define GPIO_OUTPUT(gpio_bits, bit_value) \
|
||||
if(bit_value) gpio_output_conf(gpio_bits, 0, gpio_bits, 0);\
|
||||
else gpio_output_conf(0, gpio_bits, gpio_bits, 0)
|
||||
|
||||
#define GPIO_DIS_OUTPUT(gpio_no) gpio_output_conf(0, 0, 0, 1<<gpio_no)
|
||||
#define GPIO_AS_INPUT(gpio_bits) gpio_output_conf(0, 0, 0, gpio_bits)
|
||||
#define GPIO_AS_OUTPUT(gpio_bits) gpio_output_conf(0, 0, gpio_bits, 0)
|
||||
#define GPIO_INPUT_GET(gpio_no) ((gpio_input_get()>>gpio_no)&BIT0)
|
||||
|
||||
void gpio16_output_conf(void);
|
||||
void gpio16_output_set(uint8 value);
|
||||
void gpio16_input_conf(void);
|
||||
uint8 gpio16_input_get(void);
|
||||
|
||||
void gpio_output_conf(uint32 set_mask, uint32 clear_mask, uint32 enable_mask, uint32 disable_mask);
|
||||
void gpio_intr_handler_register(void *fn);
|
||||
void gpio_pin_wakeup_enable(uint32 i, GPIO_INT_TYPE intr_state);
|
||||
void gpio_pin_wakeup_disable();
|
||||
void gpio_pin_intr_state_set(uint32 i, GPIO_INT_TYPE intr_state);
|
||||
uint32 gpio_input_get(void);
|
||||
|
||||
#endif
|
||||
63
examples/dirver_lib/include/uart.h
Normal file
63
examples/dirver_lib/include/uart.h
Normal file
@ -0,0 +1,63 @@
|
||||
/*
|
||||
* Copyright (C) 2010 -2011 Espressif System
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __UART_H__
|
||||
#define __UART_H__
|
||||
|
||||
#define UART0 0
|
||||
#define UART1 1
|
||||
|
||||
typedef enum {
|
||||
FIVE_BITS = 0x0,
|
||||
SIX_BITS = 0x1,
|
||||
SEVEN_BITS = 0x2,
|
||||
EIGHT_BITS = 0x3
|
||||
} UartBitsNum4Char;
|
||||
|
||||
typedef enum {
|
||||
ONE_STOP_BIT = 0,
|
||||
ONE_HALF_STOP_BIT = BIT(2),
|
||||
TWO_STOP_BIT = BIT(2)
|
||||
} UartStopBitsNum;
|
||||
|
||||
typedef enum {
|
||||
NONE_BITS = 0,
|
||||
ODD_BITS = 0,
|
||||
EVEN_BITS = BIT(4)
|
||||
} UartParityMode;
|
||||
|
||||
typedef enum {
|
||||
STICK_PARITY_DIS = 0,
|
||||
STICK_PARITY_EN = BIT(3) | BIT(5)
|
||||
} UartExistParity;
|
||||
|
||||
typedef enum {
|
||||
BIT_RATE_9600 = 9600,
|
||||
BIT_RATE_19200 = 19200,
|
||||
BIT_RATE_38400 = 38400,
|
||||
BIT_RATE_57600 = 57600,
|
||||
BIT_RATE_74880 = 74880,
|
||||
BIT_RATE_115200 = 115200,
|
||||
BIT_RATE_230400 = 230400,
|
||||
BIT_RATE_460800 = 460800,
|
||||
BIT_RATE_921600 = 921600
|
||||
} UartBautRate;
|
||||
|
||||
typedef enum {
|
||||
NONE_CTRL,
|
||||
HARDWARE_CTRL,
|
||||
XON_XOFF_CTRL
|
||||
} UartFlowCtrl;
|
||||
|
||||
typedef struct {
|
||||
UartBautRate baut_rate;
|
||||
UartBitsNum4Char data_bits;
|
||||
UartExistParity exist_parity;
|
||||
UartParityMode parity; // chip size in byte
|
||||
UartStopBitsNum stop_bits;
|
||||
UartFlowCtrl flow_ctrl;
|
||||
} UartDevice;
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user