diff --git a/examples/dirver_lib/driver/Makefile b/examples/dirver_lib/driver/Makefile new file mode 100644 index 00000000..ffdb4d0e --- /dev/null +++ b/examples/dirver_lib/driver/Makefile @@ -0,0 +1,44 @@ + +############################################################# +# Required variables for each makefile +# Discard this section from all parent makefiles +# Expected variables (with automatic defaults): +# CSRCS (all "C" files in the dir) +# SUBDIRS (all subdirs with a Makefile) +# GEN_LIBS - list of libs to be generated () +# GEN_IMAGES - list of images to be generated () +# COMPONENTS_xxx - a list of libs/objs in the form +# subdir/lib to be extracted and rolled up into +# a generated lib/image xxx.a () +# +ifndef PDIR +GEN_LIBS = libdriver.a +endif + + +############################################################# +# Configuration i.e. compile options etc. +# Target specific stuff (defines etc.) goes in here! +# Generally values applying to a tree are captured in the +# makefile at its root level - these are then overridden +# for a subtree within the makefile rooted therein +# +#DEFINES += + +############################################################# +# Recursion Magic - Don't touch this!! +# +# Each subtree potentially has an include directory +# corresponding to the common APIs applicable to modules +# rooted at that subtree. Accordingly, the INCLUDE PATH +# of a module can only contain the include directories up +# its parent path, and not its siblings +# +# Required for each makefile to inherit from the parent +# + +INCLUDES := $(INCLUDES) -I $(PDIR)include +INCLUDES += -I ./ +PDIR := ../$(PDIR) +sinclude $(PDIR)Makefile + diff --git a/examples/dirver_lib/driver/gpio.c b/examples/dirver_lib/driver/gpio.c new file mode 100644 index 00000000..4032e175 --- /dev/null +++ b/examples/dirver_lib/driver/gpio.c @@ -0,0 +1,207 @@ +/* + * Copyright (C) 2014 -2016 Espressif System + * + */ + +#include "espressif/esp_common.h" +#include "freertos/portmacro.h" + +#include "gpio.h" + +void ICACHE_FLASH_ATTR +gpio_config(GPIO_ConfigTypeDef *pGPIOConfig) +{ + uint16 gpio_pin_mask = pGPIOConfig->GPIO_Pin; + uint32 io_reg; + uint8 io_num = 0; + uint32 pin_reg; + + if (pGPIOConfig->GPIO_Mode == GPIO_Mode_Input) { + GPIO_AS_INPUT(gpio_pin_mask); + } else if (pGPIOConfig->GPIO_Mode == GPIO_Mode_Output) { + GPIO_AS_OUTPUT(gpio_pin_mask); + } + + do { + if ((gpio_pin_mask >> io_num) & 0x1) { + io_reg = GPIO_PIN_REG(io_num); + + if ((0x1 << io_num) & (GPIO_Pin_0 | GPIO_Pin_2 | GPIO_Pin_4 | GPIO_Pin_5)) { + PIN_FUNC_SELECT(io_reg, 0); + } else { + PIN_FUNC_SELECT(io_reg, 3); + } + + if (pGPIOConfig->GPIO_Pullup) { + PIN_PULLUP_EN(io_reg); + } else { + PIN_PULLUP_DIS(io_reg); + } + + if (pGPIOConfig->GPIO_Mode == GPIO_Mode_Out_OD) { + portENTER_CRITICAL(); + + pin_reg = GPIO_REG_READ(GPIO_PIN_ADDR(io_num)); + pin_reg &= (~GPIO_PIN_DRIVER_MASK); + pin_reg |= (GPIO_PAD_DRIVER_ENABLE << GPIO_PIN_DRIVER_LSB); + GPIO_REG_WRITE(GPIO_PIN_ADDR(io_num), pin_reg); + + portEXIT_CRITICAL(); + } else if (pGPIOConfig->GPIO_Mode == GPIO_Mode_Sigma_Delta) { + portENTER_CRITICAL(); + + pin_reg = GPIO_REG_READ(GPIO_PIN_ADDR(io_num)); + pin_reg &= (~GPIO_PIN_SOURCE_MASK); + pin_reg |= (0x1 << GPIO_PIN_SOURCE_LSB); + GPIO_REG_WRITE(GPIO_PIN_ADDR(io_num), pin_reg); + GPIO_REG_WRITE(GPIO_SIGMA_DELTA_ADDRESS, SIGMA_DELTA_ENABLE); + + portEXIT_CRITICAL(); + } + + gpio_pin_intr_state_set(io_num, pGPIOConfig->GPIO_IntrType); + } + + io_num++; + } while (io_num < 16); +} + + +/* + * Change GPIO pin output by setting, clearing, or disabling pins. + * In general, it is expected that a bit will be set in at most one + * of these masks. If a bit is clear in all masks, the output state + * remains unchanged. + * + * There is no particular ordering guaranteed; so if the order of + * writes is significant, calling code should divide a single call + * into multiple calls. + */ +void ICACHE_FLASH_ATTR +gpio_output_conf(uint32 set_mask, uint32 clear_mask, uint32 enable_mask, uint32 disable_mask) +{ + GPIO_REG_WRITE(GPIO_OUT_W1TS_ADDRESS, set_mask); + GPIO_REG_WRITE(GPIO_OUT_W1TC_ADDRESS, clear_mask); + GPIO_REG_WRITE(GPIO_ENABLE_W1TS_ADDRESS, enable_mask); + GPIO_REG_WRITE(GPIO_ENABLE_W1TC_ADDRESS, disable_mask); +} + +/* + * Sample the value of GPIO input pins and returns a bitmask. + */ +uint32 ICACHE_FLASH_ATTR +gpio_input_get(void) +{ + return GPIO_REG_READ(GPIO_IN_ADDRESS); +} + +/* + * Register an application-specific interrupt handler for GPIO pin + * interrupts. Once the interrupt handler is called, it will not + * be called again until after a call to gpio_intr_ack. Any GPIO + * interrupts that occur during the interim are masked. + * + * The application-specific handler is called with a mask of + * pending GPIO interrupts. After processing pin interrupts, the + * application-specific handler may wish to use gpio_intr_pending + * to check for any additional pending interrupts before it returns. + */ +void ICACHE_FLASH_ATTR +gpio_intr_handler_register(void *fn) +{ + _xt_isr_attach(ETS_GPIO_INUM, fn); +} + +/* + only highlevel and lowlevel intr can use for wakeup +*/ +void ICACHE_FLASH_ATTR +gpio_pin_wakeup_enable(uint32 i, GPIO_INT_TYPE intr_state) +{ + uint32 pin_reg; + + if ((intr_state == GPIO_PIN_INTR_LOLEVEL) || (intr_state == GPIO_PIN_INTR_HILEVEL)) { + portENTER_CRITICAL(); + + pin_reg = GPIO_REG_READ(GPIO_PIN_ADDR(i)); + pin_reg &= (~GPIO_PIN_INT_TYPE_MASK); + pin_reg |= (intr_state << GPIO_PIN_INT_TYPE_LSB); + pin_reg |= GPIO_PIN_WAKEUP_ENABLE_SET(GPIO_WAKEUP_ENABLE); + GPIO_REG_WRITE(GPIO_PIN_ADDR(i), pin_reg); + + portEXIT_CRITICAL(); + } +} + +void ICACHE_FLASH_ATTR +gpio_pin_wakeup_disable(void) +{ + uint8 i; + uint32 pin_reg; + + for (i = 0; i < GPIO_PIN_COUNT; i++) { + pin_reg = GPIO_REG_READ(GPIO_PIN_ADDR(i)); + + if (pin_reg & GPIO_PIN_WAKEUP_ENABLE_MASK) { + pin_reg &= (~GPIO_PIN_INT_TYPE_MASK); + pin_reg |= (GPIO_PIN_INTR_DISABLE << GPIO_PIN_INT_TYPE_LSB); + pin_reg &= ~(GPIO_PIN_WAKEUP_ENABLE_SET(GPIO_WAKEUP_ENABLE)); + GPIO_REG_WRITE(GPIO_PIN_ADDR(i), pin_reg); + } + } +} + +void ICACHE_FLASH_ATTR +gpio_pin_intr_state_set(uint32 i, GPIO_INT_TYPE intr_state) +{ + uint32 pin_reg; + + portENTER_CRITICAL(); + + pin_reg = GPIO_REG_READ(GPIO_PIN_ADDR(i)); + pin_reg &= (~GPIO_PIN_INT_TYPE_MASK); + pin_reg |= (intr_state << GPIO_PIN_INT_TYPE_LSB); + GPIO_REG_WRITE(GPIO_PIN_ADDR(i), pin_reg); + + portEXIT_CRITICAL(); +} + +void ICACHE_FLASH_ATTR +gpio16_output_conf(void) +{ + WRITE_PERI_REG(PAD_XPD_DCDC_CONF, + (READ_PERI_REG(PAD_XPD_DCDC_CONF) & 0xffffffbc) | (uint32)0x1); // mux configuration for XPD_DCDC to output rtc_gpio0 + + WRITE_PERI_REG(RTC_GPIO_CONF, + (READ_PERI_REG(RTC_GPIO_CONF) & (uint32)0xfffffffe) | (uint32)0x0); //mux configuration for out enable + + WRITE_PERI_REG(RTC_GPIO_ENABLE, + (READ_PERI_REG(RTC_GPIO_ENABLE) & (uint32)0xfffffffe) | (uint32)0x1); //out enable +} + +void ICACHE_FLASH_ATTR +gpio16_output_set(uint8 value) +{ + WRITE_PERI_REG(RTC_GPIO_OUT, + (READ_PERI_REG(RTC_GPIO_OUT) & (uint32)0xfffffffe) | (uint32)(value & 1)); +} + +void ICACHE_FLASH_ATTR +gpio16_input_conf(void) +{ + WRITE_PERI_REG(PAD_XPD_DCDC_CONF, + (READ_PERI_REG(PAD_XPD_DCDC_CONF) & 0xffffffbc) | (uint32)0x1); // mux configuration for XPD_DCDC and rtc_gpio0 connection + + WRITE_PERI_REG(RTC_GPIO_CONF, + (READ_PERI_REG(RTC_GPIO_CONF) & (uint32)0xfffffffe) | (uint32)0x0); //mux configuration for out enable + + WRITE_PERI_REG(RTC_GPIO_ENABLE, + READ_PERI_REG(RTC_GPIO_ENABLE) & (uint32)0xfffffffe); //out disable +} + +uint8 ICACHE_FLASH_ATTR +gpio16_input_get(void) +{ + return (uint8)(READ_PERI_REG(RTC_GPIO_IN_DATA) & 1); +} + diff --git a/examples/dirver_lib/include/gpio.h b/examples/dirver_lib/include/gpio.h new file mode 100644 index 00000000..e611eb4a --- /dev/null +++ b/examples/dirver_lib/include/gpio.h @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2014 -2016 Espressif System + * + */ + +#ifndef __GPIO_H__ +#define __GPIO_H__ + +#define GPIO_Pin_0 (BIT(0)) /* Pin 0 selected */ +#define GPIO_Pin_1 (BIT(1)) /* Pin 1 selected */ +#define GPIO_Pin_2 (BIT(2)) /* Pin 2 selected */ +#define GPIO_Pin_3 (BIT(3)) /* Pin 3 selected */ +#define GPIO_Pin_4 (BIT(4)) /* Pin 4 selected */ +#define GPIO_Pin_5 (BIT(5)) /* Pin 5 selected */ +#define GPIO_Pin_6 (BIT(6)) /* Pin 6 selected */ +#define GPIO_Pin_7 (BIT(7)) /* Pin 7 selected */ +#define GPIO_Pin_8 (BIT(8)) /* Pin 8 selected */ +#define GPIO_Pin_9 (BIT(9)) /* Pin 9 selected */ +#define GPIO_Pin_10 (BIT(10)) /* Pin 10 selected */ +#define GPIO_Pin_11 (BIT(11)) /* Pin 11 selected */ +#define GPIO_Pin_12 (BIT(12)) /* Pin 12 selected */ +#define GPIO_Pin_13 (BIT(13)) /* Pin 13 selected */ +#define GPIO_Pin_14 (BIT(14)) /* Pin 14 selected */ +#define GPIO_Pin_15 (BIT(15)) /* Pin 15 selected */ +#define GPIO_Pin_All (0xFFFF) /* All pins selected */ + +#define GPIO_PIN_REG_0 PERIPHS_IO_MUX_GPIO0_U +#define GPIO_PIN_REG_1 PERIPHS_IO_MUX_U0TXD_U +#define GPIO_PIN_REG_2 PERIPHS_IO_MUX_GPIO2_U +#define GPIO_PIN_REG_3 PERIPHS_IO_MUX_U0RXD_U +#define GPIO_PIN_REG_4 PERIPHS_IO_MUX_GPIO4_U +#define GPIO_PIN_REG_5 PERIPHS_IO_MUX_GPIO5_U +#define GPIO_PIN_REG_6 PERIPHS_IO_MUX_SD_CLK_U +#define GPIO_PIN_REG_7 PERIPHS_IO_MUX_SD_DATA0_U +#define GPIO_PIN_REG_8 PERIPHS_IO_MUX_SD_DATA1_U +#define GPIO_PIN_REG_9 PERIPHS_IO_MUX_SD_DATA2_U +#define GPIO_PIN_REG_10 PERIPHS_IO_MUX_SD_DATA3_U +#define GPIO_PIN_REG_11 PERIPHS_IO_MUX_SD_CMD_U +#define GPIO_PIN_REG_12 PERIPHS_IO_MUX_MTDI_U +#define GPIO_PIN_REG_13 PERIPHS_IO_MUX_MTCK_U +#define GPIO_PIN_REG_14 PERIPHS_IO_MUX_MTMS_U +#define GPIO_PIN_REG_15 PERIPHS_IO_MUX_MTDO_U + +#define GPIO_PIN_REG(i) \ + (i==0) ? GPIO_PIN_REG_0: \ + (i==1) ? GPIO_PIN_REG_1: \ + (i==2) ? GPIO_PIN_REG_2: \ + (i==3) ? GPIO_PIN_REG_3: \ + (i==4) ? GPIO_PIN_REG_4: \ + (i==5) ? GPIO_PIN_REG_5: \ + (i==6) ? GPIO_PIN_REG_6: \ + (i==7) ? GPIO_PIN_REG_7: \ + (i==8) ? GPIO_PIN_REG_8: \ + (i==9) ? GPIO_PIN_REG_9: \ + (i==10)? GPIO_PIN_REG_10: \ + (i==11)? GPIO_PIN_REG_11: \ + (i==12)? GPIO_PIN_REG_12: \ + (i==13)? GPIO_PIN_REG_13: \ + (i==14)? GPIO_PIN_REG_14: \ + GPIO_PIN_REG_15 + +#define GPIO_PIN_ADDR(i) (GPIO_PIN0_ADDRESS + i*4) + +#define GPIO_ID_IS_PIN_REGISTER(reg_id) \ + ((reg_id >= GPIO_ID_PIN0) && (reg_id <= GPIO_ID_PIN(GPIO_PIN_COUNT-1))) + +#define GPIO_REGID_TO_PINIDX(reg_id) ((reg_id) - GPIO_ID_PIN0) + +typedef enum { + GPIO_PIN_INTR_DISABLE = 0, + GPIO_PIN_INTR_POSEDGE = 1, + GPIO_PIN_INTR_NEGEDGE = 2, + GPIO_PIN_INTR_ANYEGDE = 3, + GPIO_PIN_INTR_LOLEVEL = 4, + GPIO_PIN_INTR_HILEVEL = 5 +} GPIO_INT_TYPE; + +typedef enum { + GPIO_Mode_Input = 0x0, + GPIO_Mode_Out_OD, + GPIO_Mode_Output , + GPIO_Mode_Sigma_Delta , +} GPIOMode_TypeDef; + +typedef enum { + GPIO_PullUp_DIS = 0x0, + GPIO_PullUp_EN = 0x1, +} GPIO_Pullup_IF; + +typedef struct { + uint16 GPIO_Pin; + GPIOMode_TypeDef GPIO_Mode; + GPIO_Pullup_IF GPIO_Pullup; + GPIO_INT_TYPE GPIO_IntrType; +} GPIO_ConfigTypeDef; + +#define GPIO_OUTPUT_SET(gpio_no, bit_value) \ + gpio_output_conf(bit_value<>gpio_no)&BIT0) + +void gpio16_output_conf(void); +void gpio16_output_set(uint8 value); +void gpio16_input_conf(void); +uint8 gpio16_input_get(void); + +void gpio_output_conf(uint32 set_mask, uint32 clear_mask, uint32 enable_mask, uint32 disable_mask); +void gpio_intr_handler_register(void *fn); +void gpio_pin_wakeup_enable(uint32 i, GPIO_INT_TYPE intr_state); +void gpio_pin_wakeup_disable(); +void gpio_pin_intr_state_set(uint32 i, GPIO_INT_TYPE intr_state); +uint32 gpio_input_get(void); + +#endif diff --git a/include/espressif/esp8266/uart.h b/examples/dirver_lib/include/uart.h similarity index 100% rename from include/espressif/esp8266/uart.h rename to examples/dirver_lib/include/uart.h diff --git a/include/espressif/esp8266/eagle_soc.h b/include/espressif/esp8266/eagle_soc.h index 53ac6177..80ad70c5 100644 --- a/include/espressif/esp8266/eagle_soc.h +++ b/include/espressif/esp8266/eagle_soc.h @@ -1,255 +1,107 @@ -/* - * Copyright (c) Espressif System 2010 - 2012 - * - */ - -#ifndef _EAGLE_SOC_H_ -#define _EAGLE_SOC_H_ - -//Register Bits{{ -#define BIT31 0x80000000 -#define BIT30 0x40000000 -#define BIT29 0x20000000 -#define BIT28 0x10000000 -#define BIT27 0x08000000 -#define BIT26 0x04000000 -#define BIT25 0x02000000 -#define BIT24 0x01000000 -#define BIT23 0x00800000 -#define BIT22 0x00400000 -#define BIT21 0x00200000 -#define BIT20 0x00100000 -#define BIT19 0x00080000 -#define BIT18 0x00040000 -#define BIT17 0x00020000 -#define BIT16 0x00010000 -#define BIT15 0x00008000 -#define BIT14 0x00004000 -#define BIT13 0x00002000 -#define BIT12 0x00001000 -#define BIT11 0x00000800 -#define BIT10 0x00000400 -#define BIT9 0x00000200 -#define BIT8 0x00000100 -#define BIT7 0x00000080 -#define BIT6 0x00000040 -#define BIT5 0x00000020 -#define BIT4 0x00000010 -#define BIT3 0x00000008 -#define BIT2 0x00000004 -#define BIT1 0x00000002 -#define BIT0 0x00000001 -//}} - -//Registers Operation {{ -#define ETS_UNCACHED_ADDR(addr) (addr) -#define ETS_CACHED_ADDR(addr) (addr) - - -#define READ_PERI_REG(addr) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) -#define WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val) -#define CLEAR_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))) -#define SET_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))) -#define GET_PERI_REG_BITS(reg, hipos,lowpos) ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)) -#define SET_PERI_REG_BITS(reg,bit_map,value,shift) (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|((value)<<(shift)) )) -//}} - -//Periheral Clock {{ -#define CPU_CLK_FREQ 80*1000000 //unit: Hz -#define APB_CLK_FREQ CPU_CLK_FREQ -#define UART_CLK_FREQ APB_CLK_FREQ -#define TIMER_CLK_FREQ (APB_CLK_FREQ>>8) //divided by 256 -//}} - -//Peripheral device base address define{{ -#define PERIPHS_DPORT_BASEADDR 0x3ff00000 -#define PERIPHS_GPIO_BASEADDR 0x60000300 -#define PERIPHS_TIMER_BASEDDR 0x60000600 -#define PERIPHS_RTC_BASEADDR 0x60000700 -#define PERIPHS_IO_MUX 0x60000800 -//}} - -//Interrupt remap control registers define{{ -#define EDGE_INT_ENABLE_REG (PERIPHS_DPORT_BASEADDR+0x04) -#define TM1_EDGE_INT_ENABLE() SET_PERI_REG_MASK(EDGE_INT_ENABLE_REG, BIT1) -#define TM1_EDGE_INT_DISABLE() CLEAR_PERI_REG_MASK(EDGE_INT_ENABLE_REG, BIT1) -//}} - -//GPIO reg {{ -#define GPIO_REG_READ(reg) READ_PERI_REG(PERIPHS_GPIO_BASEADDR + reg) -#define GPIO_REG_WRITE(reg, val) WRITE_PERI_REG(PERIPHS_GPIO_BASEADDR + reg, val) -#define GPIO_OUT_ADDRESS 0x00 -#define GPIO_OUT_W1TS_ADDRESS 0x04 -#define GPIO_OUT_W1TC_ADDRESS 0x08 - -#define GPIO_ENABLE_ADDRESS 0x0c -#define GPIO_ENABLE_W1TS_ADDRESS 0x10 -#define GPIO_ENABLE_W1TC_ADDRESS 0x14 -#define GPIO_OUT_W1TC_DATA_MASK 0x0000ffff - -#define GPIO_IN_ADDRESS 0x18 - -#define GPIO_STATUS_ADDRESS 0x1c -#define GPIO_STATUS_W1TS_ADDRESS 0x20 -#define GPIO_STATUS_W1TC_ADDRESS 0x24 -#define GPIO_STATUS_INTERRUPT_MASK 0x0000ffff - -#define GPIO_RTC_CALIB_SYNC PERIPHS_GPIO_BASEADDR+0x6c -#define RTC_CALIB_START BIT31 //first write to zero, then to one to start -#define RTC_PERIOD_NUM_MASK 0x3ff //max 8ms -#define GPIO_RTC_CALIB_VALUE PERIPHS_GPIO_BASEADDR+0x70 -#define RTC_CALIB_RDY_S 31 //after measure, flag to one, when start from zero to one, turn to zero -#define RTC_CALIB_VALUE_MASK 0xfffff - -#define GPIO_PIN0_ADDRESS 0x28 - -#define GPIO_ID_PIN0 0 -#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n)) -#define GPIO_LAST_REGISTER_ID GPIO_ID_PIN(15) -#define GPIO_ID_NONE 0xffffffff - -#define GPIO_PIN_COUNT 16 - -#define GPIO_PIN_CONFIG_MSB 12 -#define GPIO_PIN_CONFIG_LSB 11 -#define GPIO_PIN_CONFIG_MASK 0x00001800 -#define GPIO_PIN_CONFIG_GET(x) (((x) & GPIO_PIN_CONFIG_MASK) >> GPIO_PIN_CONFIG_LSB) -#define GPIO_PIN_CONFIG_SET(x) (((x) << GPIO_PIN_CONFIG_LSB) & GPIO_PIN_CONFIG_MASK) - -#define GPIO_WAKEUP_ENABLE 1 -#define GPIO_WAKEUP_DISABLE (~GPIO_WAKEUP_ENABLE) -#define GPIO_PIN_WAKEUP_ENABLE_MSB 10 -#define GPIO_PIN_WAKEUP_ENABLE_LSB 10 -#define GPIO_PIN_WAKEUP_ENABLE_MASK 0x00000400 -#define GPIO_PIN_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN_WAKEUP_ENABLE_MASK) >> GPIO_PIN_WAKEUP_ENABLE_LSB) -#define GPIO_PIN_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN_WAKEUP_ENABLE_LSB) & GPIO_PIN_WAKEUP_ENABLE_MASK) - -#define GPIO_PIN_INT_TYPE_MASK 0x380 -#define GPIO_PIN_INT_TYPE_MSB 9 -#define GPIO_PIN_INT_TYPE_LSB 7 -#define GPIO_PIN_INT_TYPE_GET(x) (((x) & GPIO_PIN_INT_TYPE_MASK) >> GPIO_PIN_INT_TYPE_LSB) -#define GPIO_PIN_INT_TYPE_SET(x) (((x) << GPIO_PIN_INT_TYPE_LSB) & GPIO_PIN_INT_TYPE_MASK) - -#define GPIO_PAD_DRIVER_ENABLE 1 -#define GPIO_PAD_DRIVER_DISABLE (~GPIO_PAD_DRIVER_ENABLE) -#define GPIO_PIN_PAD_DRIVER_MSB 2 -#define GPIO_PIN_PAD_DRIVER_LSB 2 -#define GPIO_PIN_PAD_DRIVER_MASK 0x00000004 -#define GPIO_PIN_PAD_DRIVER_GET(x) (((x) & GPIO_PIN_PAD_DRIVER_MASK) >> GPIO_PIN_PAD_DRIVER_LSB) -#define GPIO_PIN_PAD_DRIVER_SET(x) (((x) << GPIO_PIN_PAD_DRIVER_LSB) & GPIO_PIN_PAD_DRIVER_MASK) - -#define GPIO_AS_PIN_SOURCE 0 -#define SIGMA_AS_PIN_SOURCE (~GPIO_AS_PIN_SOURCE) -#define GPIO_PIN_SOURCE_MSB 0 -#define GPIO_PIN_SOURCE_LSB 0 -#define GPIO_PIN_SOURCE_MASK 0x00000001 -#define GPIO_PIN_SOURCE_GET(x) (((x) & GPIO_PIN_SOURCE_MASK) >> GPIO_PIN_SOURCE_LSB) -#define GPIO_PIN_SOURCE_SET(x) (((x) << GPIO_PIN_SOURCE_LSB) & GPIO_PIN_SOURCE_MASK) -// }} - -// TIMER reg {{ -#define RTC_REG_READ(addr) READ_PERI_REG(PERIPHS_TIMER_BASEDDR + addr) -#define RTC_REG_WRITE(addr, val) WRITE_PERI_REG(PERIPHS_TIMER_BASEDDR + addr, val) -#define RTC_CLR_REG_MASK(reg, mask) CLEAR_PERI_REG_MASK(PERIPHS_TIMER_BASEDDR +reg, mask) -/* Returns the current time according to the timer timer. */ -#define NOW() RTC_REG_READ(FRC2_COUNT_ADDRESS) - -//load initial_value to timer1 -#define FRC1_LOAD_ADDRESS 0x00 - -//timer1's counter value(count from initial_value to 0) -#define FRC1_COUNT_ADDRESS 0x04 - -#define FRC1_CTRL_ADDRESS 0x08 - -//clear timer1's interrupt when write this address -#define FRC1_INT_ADDRESS 0x0c -#define FRC1_INT_CLR_MASK 0x00000001 - -//timer2's counter value(count from initial_value to 0) -#define FRC2_COUNT_ADDRESS 0x24 -// }} - -//RTC reg {{ -#define REG_RTC_BASE PERIPHS_RTC_BASEADDR - -#define RTC_GPIO_OUT (REG_RTC_BASE + 0x068) -#define RTC_GPIO_ENABLE (REG_RTC_BASE + 0x074) -#define RTC_GPIO_IN_DATA (REG_RTC_BASE + 0x08C) -#define RTC_GPIO_CONF (REG_RTC_BASE + 0x090) -#define PAD_XPD_DCDC_CONF (REG_RTC_BASE + 0x0A0) -//}} - -//PIN Mux reg {{ -#define PERIPHS_IO_MUX_FUNC 0x13 -#define PERIPHS_IO_MUX_FUNC_S 4 -#define PERIPHS_IO_MUX_PULLUP BIT7 -#define PERIPHS_IO_MUX_PULLDWN BIT6 -#define PERIPHS_IO_MUX_SLEEP_PULLUP BIT3 -#define PERIPHS_IO_MUX_SLEEP_PULLDWN BIT2 -#define PERIPHS_IO_MUX_SLEEP_OE BIT1 -#define PERIPHS_IO_MUX_OE BIT0 - -#define PERIPHS_IO_MUX_CONF_U (PERIPHS_IO_MUX + 0x00) -#define SPI0_CLK_EQU_SYS_CLK BIT8 -#define SPI1_CLK_EQU_SYS_CLK BIT9 -#define PERIPHS_IO_MUX_MTDI_U (PERIPHS_IO_MUX + 0x04) -#define FUNC_GPIO12 3 -#define PERIPHS_IO_MUX_MTCK_U (PERIPHS_IO_MUX + 0x08) -#define FUNC_GPIO13 3 -#define PERIPHS_IO_MUX_MTMS_U (PERIPHS_IO_MUX + 0x0C) -#define FUNC_GPIO14 3 -#define PERIPHS_IO_MUX_MTDO_U (PERIPHS_IO_MUX + 0x10) -#define FUNC_GPIO15 3 -#define FUNC_U0RTS 4 -#define PERIPHS_IO_MUX_U0RXD_U (PERIPHS_IO_MUX + 0x14) -#define FUNC_GPIO3 3 -#define PERIPHS_IO_MUX_U0TXD_U (PERIPHS_IO_MUX + 0x18) -#define FUNC_U0TXD 0 -#define FUNC_GPIO1 3 -#define PERIPHS_IO_MUX_SD_CLK_U (PERIPHS_IO_MUX + 0x1c) -#define FUNC_SDCLK 0 -#define FUNC_SPICLK 1 -#define PERIPHS_IO_MUX_SD_DATA0_U (PERIPHS_IO_MUX + 0x20) -#define FUNC_SDDATA0 0 -#define FUNC_SPIQ 1 -#define FUNC_U1TXD 4 -#define PERIPHS_IO_MUX_SD_DATA1_U (PERIPHS_IO_MUX + 0x24) -#define FUNC_SDDATA1 0 -#define FUNC_SPID 1 -#define FUNC_U1RXD 4 -#define FUNC_SDDATA1_U1RXD 7 -#define PERIPHS_IO_MUX_SD_DATA2_U (PERIPHS_IO_MUX + 0x28) -#define FUNC_SDDATA2 0 -#define FUNC_SPIHD 1 -#define FUNC_GPIO9 3 -#define PERIPHS_IO_MUX_SD_DATA3_U (PERIPHS_IO_MUX + 0x2c) -#define FUNC_SDDATA3 0 -#define FUNC_SPIWP 1 -#define FUNC_GPIO10 3 -#define PERIPHS_IO_MUX_SD_CMD_U (PERIPHS_IO_MUX + 0x30) -#define FUNC_SDCMD 0 -#define FUNC_SPICS0 1 -#define PERIPHS_IO_MUX_GPIO0_U (PERIPHS_IO_MUX + 0x34) -#define FUNC_GPIO0 0 -#define PERIPHS_IO_MUX_GPIO2_U (PERIPHS_IO_MUX + 0x38) -#define FUNC_GPIO2 0 -#define FUNC_U1TXD_BK 2 -#define FUNC_U0TXD_BK 4 -#define PERIPHS_IO_MUX_GPIO4_U (PERIPHS_IO_MUX + 0x3C) -#define FUNC_GPIO4 0 -#define PERIPHS_IO_MUX_GPIO5_U (PERIPHS_IO_MUX + 0x40) -#define FUNC_GPIO5 0 - -#define PIN_PULLUP_DIS(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME, PERIPHS_IO_MUX_PULLUP) -#define PIN_PULLUP_EN(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME, PERIPHS_IO_MUX_PULLUP) -#define PIN_PULLDWN_DIS(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME, PERIPHS_IO_MUX_PULLDWN) -#define PIN_PULLDWN_EN(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME, PERIPHS_IO_MUX_PULLDWN) -#define PIN_FUNC_SELECT(PIN_NAME, FUNC) do { \ - CLEAR_PERI_REG_MASK(PIN_NAME, (PERIPHS_IO_MUX_FUNC<>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)) +#define SET_PERI_REG_BITS(reg,bit_map,value,shift) (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|((value)<<(shift)) )) +//}} + +//Periheral Clock {{ +#define CPU_CLK_FREQ 80*1000000 // unit: Hz +#define APB_CLK_FREQ CPU_CLK_FREQ +#define UART_CLK_FREQ APB_CLK_FREQ +#define TIMER_CLK_FREQ (APB_CLK_FREQ>>8) // divided by 256 +//}} + +//Peripheral device base address define{{ +#define PERIPHS_DPORT_BASEADDR 0x3ff00000 +#define PERIPHS_RTC_BASEADDR 0x60000700 +//}} + +//DPORT{{ +#define HOST_INF_SEL (0x28) +#define DPORT_LINK_DEVICE_SEL 0x000000FF +#define DPORT_LINK_DEVICE_SEL_S 8 +#define DPORT_PERI_IO_SWAP 0x000000FF +#define DPORT_PERI_IO_SWAP_S 0 +#define PERI_IO_CSPI_OVERLAP (BIT(7)) // two spi masters on cspi +#define PERI_IO_HSPI_OVERLAP (BIT(6)) // two spi masters on hspi +#define PERI_IO_HSPI_PRIO (BIT(5)) // hspi is with the higher prior +#define PERI_IO_UART1_PIN_SWAP (BIT(3)) // swap uart1 pins (u1rxd <-> u1cts), (u1txd <-> u1rts) +#define PERI_IO_UART0_PIN_SWAP (BIT(2)) // swap uart0 pins (u0rxd <-> u0cts), (u0txd <-> u0rts) +#define PERI_IO_SPI_PORT_SWAP (BIT(1)) // swap two spi +#define PERI_IO_UART_PORT_SWAP (BIT(0)) // swap two uart +//}} + +//Interrupt remap control registers define{{ +#define EDGE_INT_ENABLE_REG (PERIPHS_DPORT_BASEADDR+0x04) +#define TM1_EDGE_INT_ENABLE() SET_PERI_REG_MASK(EDGE_INT_ENABLE_REG, BIT1) +#define TM1_EDGE_INT_DISABLE() CLEAR_PERI_REG_MASK(EDGE_INT_ENABLE_REG, BIT1) +//}} + +//RTC reg {{ +#define REG_RTC_BASE PERIPHS_RTC_BASEADDR + +#define RTC_SLP_VAL (REG_RTC_BASE + 0x004) // the target value of RTC_COUNTER for wakeup from light-sleep/deep-sleep +#define RTC_SLP_CNT_VAL (REG_RTC_BASE + 0x01C) // the current value of RTC_COUNTER + +#define RTC_SCRATCH0 (REG_RTC_BASE + 0x030) // the register for software to save some values for watchdog reset +#define RTC_SCRATCH1 (REG_RTC_BASE + 0x034) // the register for software to save some values for watchdog reset +#define RTC_SCRATCH2 (REG_RTC_BASE + 0x038) // the register for software to save some values for watchdog reset +#define RTC_SCRATCH3 (REG_RTC_BASE + 0x03C) // the register for software to save some values for watchdog reset + +#define RTC_GPIO_OUT (REG_RTC_BASE + 0x068) // used by gpio16 +#define RTC_GPIO_ENABLE (REG_RTC_BASE + 0x074) +#define RTC_GPIO_IN_DATA (REG_RTC_BASE + 0x08C) +#define RTC_GPIO_CONF (REG_RTC_BASE + 0x090) +#define PAD_XPD_DCDC_CONF (REG_RTC_BASE + 0x0A0) +//}} + +#endif //_EAGLE_SOC_H_ diff --git a/include/espressif/esp8266/esp8266.h b/include/espressif/esp8266/esp8266.h new file mode 100644 index 00000000..1c7a6d26 --- /dev/null +++ b/include/espressif/esp8266/esp8266.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2014 - 2016 Espressif System + * + */ + +#ifndef __ESP8266_H__ +#define __ESP8266_H__ + +#include "ets_sys.h" +#include "eagle_soc.h" +#include "gpio_register.h" +#include "pin_mux_register.h" +#include "spi_register.h" +#include "timer_register.h" +#include "uart_register.h" + +#endif + diff --git a/include/espressif/esp8266/ets_sys.h b/include/espressif/esp8266/ets_sys.h index 77f8a15c..55e04352 100644 --- a/include/espressif/esp8266/ets_sys.h +++ b/include/espressif/esp8266/ets_sys.h @@ -9,11 +9,12 @@ #define __ETS_SYS_H__ /* interrupt related */ +#define ETS_SPI_INUM 2 #define ETS_GPIO_INUM 4 #define ETS_UART_INUM 5 #define ETS_MAX_INUM 6 -#define ETS_SOFT_INUM 7 //software isr. -#define ETS_WDT_INUM 8 /* use edge*/ -#define ETS_FRC_TIMER1_INUM 9 /* use edge*/ +#define ETS_SOFT_INUM 7 +#define ETS_WDT_INUM 8 +#define ETS_FRC_TIMER1_INUM 9 #endif /* _ETS_SYS_H */ diff --git a/include/espressif/esp8266/gpio_register.h b/include/espressif/esp8266/gpio_register.h new file mode 100644 index 00000000..9e8d7c45 --- /dev/null +++ b/include/espressif/esp8266/gpio_register.h @@ -0,0 +1,319 @@ +/* + * copyright (c) Espressif System 2014 + * + */ + +#ifndef _GPIO_REGISTER_H_ +#define _GPIO_REGISTER_H_ + +#define PERIPHS_GPIO_BASEADDR 0x60000300 + +#define GPIO_OUT_ADDRESS 0x00 +#define GPIO_BT_SEL 0x0000ffff +#define GPIO_BT_SEL_S 16 +#define GPIO_OUT_DATA 0x0000ffff +#define GPIO_OUT_DATA_S 0 + +#define GPIO_OUT_W1TS_ADDRESS 0x04 +#define GPIO_OUT_DATA_W1TS 0x0000ffff +#define GPIO_OUT_DATA_W1TS_S 0 + +#define GPIO_OUT_W1TC_ADDRESS 0x08 +#define GPIO_OUT_DATA_W1TC 0x0000ffff +#define GPIO_OUT_DATA_W1TC_S 0 +#define GPIO_OUT_DATA_MASK 0x0000ffff + +#define GPIO_ENABLE_ADDRESS 0x0c +#define GPIO_SDIO_SEL 0x0000003f +#define GPIO_SDIO_SEL_S 16 +#define GPIO_ENABLE_DATA 0x0000ffff +#define GPIO_ENABLE_DATA_S 0 + +#define GPIO_ENABLE_W1TS_ADDRESS 0x10 +#define GPIO_ENABLE_DATA_W1TS 0x0000ffff +#define GPIO_ENABLE_DATA_W1TS_s 0 + +#define GPIO_ENABLE_W1TC_ADDRESS 0x14 +#define GPIO_ENABLE_DATA_W1TC 0x0000ffff +#define GPIO_ENABLE_DATA_W1TC_S 0 +#define GPIO_ENABLE_DATA_DATA_MASK 0x0000ffff + +#define GPIO_IN_ADDRESS 0x18 +#define GPIO_STRAPPING 0x0000ffff +#define GPIO_STRAPPING_S 16 +#define GPIO_IN_DATA 0x0000ffff +#define GPIO_IN_DATA_S 0 + +#define GPIO_STATUS_ADDRESS 0x1c +#define GPIO_STATUS_INTERRUPT 0x0000ffff +#define GPIO_STATUS_INTERRUPT_S 0 + +#define GPIO_STATUS_W1TS_ADDRESS 0x20 +#define GPIO_STATUS_INTERRUPT_W1TS 0x0000ffff +#define GPIO_STATUS_INTERRUPT_W1TS_S 0 + +#define GPIO_STATUS_W1TC_ADDRESS 0x24 +#define GPIO_STATUS_INTERRUPT_W1TC 0x0000ffff +#define GPIO_STATUS_INTERRUPT_W1TC_S 0 +#define GPIO_STATUS_INTERRUPT_DATA_MASK 0x0000ffff + +//Region1: used for gpio config for GPIO_PIN0_ADDRESS~GPIO_PIN15_ADDRESS +#define GPIO_ID_PIN0 0 +#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n)) +#define GPIO_LAST_REGISTER_ID GPIO_ID_PIN(15) +#define GPIO_ID_NONE 0xffffffff +#define GPIO_PIN_COUNT 16 + +#define GPIO_PIN_CONFIG_MSB 12 +#define GPIO_PIN_CONFIG_LSB 11 +#define GPIO_PIN_CONFIG_MASK (0x00000003<> GPIO_PIN_CONFIG_LSB) +#define GPIO_PIN_CONFIG_SET(x) (((x) << GPIO_PIN_CONFIG_LSB) & GPIO_PIN_CONFIG_MASK) + +#define GPIO_WAKEUP_ENABLE 1 +#define GPIO_WAKEUP_DISABLE (~GPIO_WAKEUP_ENABLE) +#define GPIO_PIN_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN_WAKEUP_ENABLE_MASK (0x00000001<> GPIO_PIN_CONFIG_LSB) +#define GPIO_PIN_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN_WAKEUP_ENABLE_LSB) & GPIO_PIN_WAKEUP_ENABLE_MASK) + +#define GPIO_PIN_INT_TYPE_MSB 9 +#define GPIO_PIN_INT_TYPE_LSB 7 +#define GPIO_PIN_INT_TYPE_MASK (0x00000007<> GPIO_PIN_INT_TYPE_LSB) +#define GPIO_PIN_INT_TYPE_SET(x) (((x) << GPIO_PIN_INT_TYPE_LSB) & GPIO_PIN_INT_TYPE_MASK) + +#define GPIO_PAD_DRIVER_ENABLE 1 +#define GPIO_PAD_DRIVER_DISABLE (~GPIO_PAD_DRIVER_ENABLE) +#define GPIO_PIN_DRIVER_MSB 2 +#define GPIO_PIN_DRIVER_LSB 2 +#define GPIO_PIN_DRIVER_MASK (0x00000001<> GPIO_PIN_INT_TYPE_LSB) +#define GPIO_PIN_PAD_DRIVER_SET(x) (((x) << GPIO_PIN_DRIVER_LSB) & GPIO_PIN_DRIVER_MASK) + +#define GPIO_PIN_SOURCE_MSB 0 +#define GPIO_PIN_SOURCE_LSB 0 +#define GPIO_PIN_SOURCE_MASK (0x00000001<> GPIO_PIN_INT_TYPE_LSB) +#define GPIO_PIN_SOURCE_SET(x) (((x) << GPIO_PIN_SOURCE_LSB) & GPIO_PIN_SOURCE_MASK) +//end of region1 + +#define GPIO_PIN0_ADDRESS 0x28 +#define GPIO_PIN0_CONFIG 0x00000003 +#define GPIO_PIN0_CONFIG_S 11 +#define GPIO_PIN0_WAKEUP_ENABLE BIT10 +#define GPIO_PIN0_WAKEUP_ENABLE_S 10 +#define GPIO_PIN0_INT_TYPE 0x00000007 +#define GPIO_PIN0_INT_TYPE_S 7 +#define GPIO_PIN0_DRIVER BIT2 +#define GPIO_PIN0_DRIVER_S 2 +#define GPIO_PIN0_SOURCE BIT0 +#define GPIO_PIN0_SOURCE_S 0 + +#define GPIO_PIN1_ADDRESS 0x2c +#define GPIO_PIN1_CONFIG 0x00000003 +#define GPIO_PIN1_CONFIG_S 11 +#define GPIO_PIN1_WAKEUP_ENABLE BIT10 +#define GPIO_PIN1_WAKEUP_ENABLE_S 10 +#define GPIO_PIN1_INT_TYPE 0x00000007 +#define GPIO_PIN1_INT_TYPE_S 7 +#define GPIO_PIN1_DRIVER BIT2 +#define GPIO_PIN1_DRIVER_S 2 +#define GPIO_PIN1_SOURCE BIT0 +#define GPIO_PIN1_SOURCE_S 0 + +#define GPIO_PIN2_ADDRESS 0x30 +#define GPIO_PIN2_CONFIG 0x00000003 +#define GPIO_PIN2_CONFIG_S 11 +#define GPIO_PIN2_WAKEUP_ENABLE BIT10 +#define GPIO_PIN2_WAKEUP_ENABLE_S 10 +#define GPIO_PIN2_INT_TYPE 0x00000007 +#define GPIO_PIN2_INT_TYPE_S 7 +#define GPIO_PIN2_DRIVER BIT2 +#define GPIO_PIN2_DRIVER_S 2 +#define GPIO_PIN2_SOURCE BIT0 +#define GPIO_PIN2_SOURCE_S 0 + +#define GPIO_PIN3_ADDRESS 0x34 +#define GPIO_PIN3_CONFIG 0x00000003 +#define GPIO_PIN3_CONFIG_S 11 +#define GPIO_PIN3_WAKEUP_ENABLE BIT10 +#define GPIO_PIN3_WAKEUP_ENABLE_S 10 +#define GPIO_PIN3_INT_TYPE 0x00000007 +#define GPIO_PIN3_INT_TYPE_S 7 +#define GPIO_PIN3_DRIVER BIT2 +#define GPIO_PIN3_DRIVER_S 2 +#define GPIO_PIN3_SOURCE BIT0 +#define GPIO_PIN3_SOURCE_S 0 + +#define GPIO_PIN4_ADDRESS 0x38 +#define GPIO_PIN4_CONFIG 0x00000003 +#define GPIO_PIN4_CONFIG_S 11 +#define GPIO_PIN4_WAKEUP_ENABLE BIT10 +#define GPIO_PIN4_WAKEUP_ENABLE_S 10 +#define GPIO_PIN4_INT_TYPE 0x00000007 +#define GPIO_PIN4_INT_TYPE_S 7 +#define GPIO_PIN4_DRIVER BIT2 +#define GPIO_PIN4_DRIVER_S 2 +#define GPIO_PIN4_SOURCE BIT0 +#define GPIO_PIN4_SOURCE_S 0 + +#define GPIO_PIN5_ADDRESS 0x3c +#define GPIO_PIN5_CONFIG 0x00000003 +#define GPIO_PIN5_CONFIG_S 11 +#define GPIO_PIN5_WAKEUP_ENABLE BIT10 +#define GPIO_PIN5_WAKEUP_ENABLE_S 10 +#define GPIO_PIN5_INT_TYPE 0x00000007 +#define GPIO_PIN5_INT_TYPE_S 7 +#define GPIO_PIN5_DRIVER BIT2 +#define GPIO_PIN5_DRIVER_S 2 +#define GPIO_PIN5_SOURCE BIT0 +#define GPIO_PIN5_SOURCE_S 0 + +#define GPIO_PIN6_ADDRESS 0x40 +#define GPIO_PIN6_CONFIG 0x00000003 +#define GPIO_PIN6_CONFIG_S 11 +#define GPIO_PIN6_WAKEUP_ENABLE BIT10 +#define GPIO_PIN6_WAKEUP_ENABLE_S 10 +#define GPIO_PIN6_INT_TYPE 0x00000007 +#define GPIO_PIN6_INT_TYPE_S 7 +#define GPIO_PIN6_DRIVER BIT2 +#define GPIO_PIN6_DRIVER_S 2 +#define GPIO_PIN6_SOURCE BIT0 +#define GPIO_PIN6_SOURCE_S 0 + +#define GPIO_PIN7_ADDRESS 0x44 +#define GPIO_PIN7_CONFIG 0x00000003 +#define GPIO_PIN7_CONFIG_S 11 +#define GPIO_PIN7_WAKEUP_ENABLE BIT10 +#define GPIO_PIN7_WAKEUP_ENABLE_S 10 +#define GPIO_PIN7_INT_TYPE 0x00000007 +#define GPIO_PIN7_INT_TYPE_S 7 +#define GPIO_PIN7_DRIVER BIT2 +#define GPIO_PIN7_DRIVER_S 2 +#define GPIO_PIN7_SOURCE BIT0 +#define GPIO_PIN7_SOURCE_S 0 + +#define GPIO_PIN8_ADDRESS 0x48 +#define GPIO_PIN8_CONFIG 0x00000003 +#define GPIO_PIN8_CONFIG_S 11 +#define GPIO_PIN8_WAKEUP_ENABLE BIT10 +#define GPIO_PIN8_WAKEUP_ENABLE_S 10 +#define GPIO_PIN8_INT_TYPE 0x00000007 +#define GPIO_PIN8_INT_TYPE_S 7 +#define GPIO_PIN8_DRIVER BIT2 +#define GPIO_PIN8_DRIVER_S 2 +#define GPIO_PIN8_SOURCE BIT0 +#define GPIO_PIN8_SOURCE_S 0 + +#define GPIO_PIN9_ADDRESS 0x4c +#define GPIO_PIN9_CONFIG 0x00000003 +#define GPIO_PIN9_CONFIG_S 11 +#define GPIO_PIN9_WAKEUP_ENABLE BIT10 +#define GPIO_PIN9_WAKEUP_ENABLE_S 10 +#define GPIO_PIN9_INT_TYPE 0x00000007 +#define GPIO_PIN9_INT_TYPE_S 7 +#define GPIO_PIN9_DRIVER BIT2 +#define GPIO_PIN9_DRIVER_S 2 +#define GPIO_PIN9_SOURCE BIT0 +#define GPIO_PIN9_SOURCE_S 0 + +#define GPIO_PIN10_ADDRESS 0x50 +#define GPIO_PIN10_CONFIG 0x00000003 +#define GPIO_PIN10_CONFIG_S 11 +#define GPIO_PIN10_WAKEUP_ENABLE BIT10 +#define GPIO_PIN10_WAKEUP_ENABLE_S 10 +#define GPIO_PIN10_INT_TYPE 0x00000007 +#define GPIO_PIN10_INT_TYPE_S 7 +#define GPIO_PIN10_DRIVER BIT2 +#define GPIO_PIN10_DRIVER_S 2 +#define GPIO_PIN10_SOURCE BIT0 +#define GPIO_PIN10_SOURCE_S 0 + +#define GPIO_PIN11_ADDRESS 0x54 +#define GPIO_PIN11_CONFIG 0x00000003 +#define GPIO_PIN11_CONFIG_S 11 +#define GPIO_PIN11_WAKEUP_ENABLE BIT10 +#define GPIO_PIN11_WAKEUP_ENABLE_S 10 +#define GPIO_PIN11_INT_TYPE 0x00000007 +#define GPIO_PIN11_INT_TYPE_S 7 +#define GPIO_PIN11_DRIVER BIT2 +#define GPIO_PIN11_DRIVER_S 2 +#define GPIO_PIN11_SOURCE BIT0 +#define GPIO_PIN11_SOURCE_S 0 + +#define GPIO_PIN12_ADDRESS 0x58 +#define GPIO_PIN12_CONFIG 0x00000003 +#define GPIO_PIN12_CONFIG_S 11 +#define GPIO_PIN12_WAKEUP_ENABLE BIT10 +#define GPIO_PIN12_WAKEUP_ENABLE_S 10 +#define GPIO_PIN12_INT_TYPE 0x00000007 +#define GPIO_PIN12_INT_TYPE_S 7 +#define GPIO_PIN12_DRIVER BIT2 +#define GPIO_PIN12_DRIVER_S 2 +#define GPIO_PIN12_SOURCE BIT0 +#define GPIO_PIN12_SOURCE_S 0 + +#define GPIO_PIN13_ADDRESS 0x5c +#define GPIO_PIN13_CONFIG 0x00000003 +#define GPIO_PIN13_CONFIG_S 11 +#define GPIO_PIN13_WAKEUP_ENABLE BIT10 +#define GPIO_PIN13_WAKEUP_ENABLE_S 10 +#define GPIO_PIN13_INT_TYPE 0x00000007 +#define GPIO_PIN13_INT_TYPE_S 7 +#define GPIO_PIN13_DRIVER BIT2 +#define GPIO_PIN13_DRIVER_S 2 +#define GPIO_PIN13_SOURCE BIT0 +#define GPIO_PIN13_SOURCE_S 0 + +#define GPIO_PIN14_ADDRESS 0x60 +#define GPIO_PIN14_CONFIG 0x00000003 +#define GPIO_PIN14_CONFIG_S 11 +#define GPIO_PIN14_WAKEUP_ENABLE BIT10 +#define GPIO_PIN14_WAKEUP_ENABLE_S 10 +#define GPIO_PIN14_INT_TYPE 0x00000007 +#define GPIO_PIN14_INT_TYPE_S 7 +#define GPIO_PIN14_DRIVER BIT2 +#define GPIO_PIN14_DRIVER_S 2 +#define GPIO_PIN14_SOURCE BIT0 +#define GPIO_PIN14_SOURCE_S 0 + +#define GPIO_PIN15_ADDRESS 0x64 +#define GPIO_PIN15_CONFIG 0x00000003 +#define GPIO_PIN15_CONFIG_S 11 +#define GPIO_PIN15_WAKEUP_ENABLE BIT10 +#define GPIO_PIN15_WAKEUP_ENABLE_S 10 +#define GPIO_PIN15_INT_TYPE 0x00000007 +#define GPIO_PIN15_INT_TYPE_S 7 +#define GPIO_PIN15_DRIVER BIT2 +#define GPIO_PIN15_DRIVER_S 2 +#define GPIO_PIN15_SOURCE BIT0 +#define GPIO_PIN15_SOURCE_S 0 + +#define GPIO_SIGMA_DELTA_ADDRESS 0x68 +#define SIGMA_DELTA_ENABLE BIT16 +#define SIGMA_DELTA_ENABLE_S 16 +#define SIGMA_DELTA_PRESCALAR 0x000000ff +#define SIGMA_DELTA_PRESCALAR_S 8 +#define SIGMA_DELTA_TARGET 0x000000ff +#define SIGMA_DELTA_TARGET_S 0 + +#define GPIO_RTC_CALIB_SYNC_ADDRESS 0x6c +#define RTC_CALIB_START BIT31 +#define RTC_CALIB_START_S 31 +#define RTC_PERIOD_NUM 0x000003ff +#define RTC_PERIOD_NUM_S 0 + +#define GPIO_RTC_CALIB_VALUE_ADDRESS 0x70 +#define RTC_CALIB_RDY BIT31 +#define RTC_CALIB_RDY_S 31 +#define RTC_CALIB_RDY_REAL BIT30 +#define RTC_CALIB_RDY_REAL_S 30 +#define RTC_CALIB_VALUE 0x000fffff +#define RTC_CALIB_VALUE_S 0 + +#define GPIO_REG_READ(reg) READ_PERI_REG(PERIPHS_GPIO_BASEADDR + reg) +#define GPIO_REG_WRITE(reg, val) WRITE_PERI_REG(PERIPHS_GPIO_BASEADDR + reg, val) + +#endif diff --git a/include/espressif/esp8266/pin_mux_register.h b/include/espressif/esp8266/pin_mux_register.h new file mode 100644 index 00000000..08dd40a6 --- /dev/null +++ b/include/espressif/esp8266/pin_mux_register.h @@ -0,0 +1,133 @@ +/* + * Copyright (c) Espressif System 2010 - 2012 + * + */ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#define PERIPHS_IO_MUX 0x60000800 + +#define PERIPHS_IO_MUX_FUNC 0x13 +#define PERIPHS_IO_MUX_FUNC_S 4 +#define PERIPHS_IO_MUX_PULLUP BIT7 +#define PERIPHS_IO_MUX_PULLDWN BIT6 +#define PERIPHS_IO_MUX_SLEEP_PULLUP BIT3 +#define PERIPHS_IO_MUX_SLEEP_PULLDWN BIT2 +#define PERIPHS_IO_MUX_SLEEP_OE BIT1 +#define PERIPHS_IO_MUX_OE BIT0 + +#define PERIPHS_IO_MUX_CONF_U (PERIPHS_IO_MUX + 0x00) +#define SPI0_CLK_EQU_SYS_CLK BIT8 +#define SPI1_CLK_EQU_SYS_CLK BIT9 + +#define PERIPHS_IO_MUX_MTDI_U (PERIPHS_IO_MUX + 0x04) +#define FUNC_MTDI 0 +#define FUNC_I2SI_DATA 1 +#define FUNC_HSPIQ_MISO 2 +#define FUNC_GPIO12 3 +#define FUNC_UART0_DTR 4 + +#define PERIPHS_IO_MUX_MTCK_U (PERIPHS_IO_MUX + 0x08) +#define FUNC_MTCK 0 +#define FUNC_I2SI_BCK 1 +#define FUNC_HSPID_MOSI 2 +#define FUNC_GPIO13 3 +#define FUNC_UART0_CTS 4 + +#define PERIPHS_IO_MUX_MTMS_U (PERIPHS_IO_MUX + 0x0C) +#define FUNC_MTMS 0 +#define FUNC_I2SI_WS 1 +#define FUNC_HSPI_CLK 2 +#define FUNC_GPIO14 3 +#define FUNC_UART0_DSR 4 + +#define PERIPHS_IO_MUX_MTDO_U (PERIPHS_IO_MUX + 0x10) +#define FUNC_MTDO 0 +#define FUNC_I2SO_BCK 1 +#define FUNC_HSPI_CS0 2 +#define FUNC_GPIO15 3 +#define FUNC_U0RTS 4 +#define FUNC_UART0_RTS 4 + +#define PERIPHS_IO_MUX_U0RXD_U (PERIPHS_IO_MUX + 0x14) +#define FUNC_U0RXD 0 +#define FUNC_I2SO_DATA 1 +#define FUNC_GPIO3 3 +#define FUNC_CLK_XTAL_BK 4 + +#define PERIPHS_IO_MUX_U0TXD_U (PERIPHS_IO_MUX + 0x18) +#define FUNC_U0TXD 0 +#define FUNC_SPICS1 1 +#define FUNC_GPIO1 3 +#define FUNC_CLK_RTC_BK 4 + +#define PERIPHS_IO_MUX_SD_CLK_U (PERIPHS_IO_MUX + 0x1c) +#define FUNC_SDCLK 0 +#define FUNC_SPICLK 1 +#define FUNC_GPIO6 3 +#define UART1_CTS 4 + +#define PERIPHS_IO_MUX_SD_DATA0_U (PERIPHS_IO_MUX + 0x20) +#define FUNC_SDDATA0 0 +#define FUNC_SPIQ_MISO 1 +#define FUNC_GPIO7 3 +#define FUNC_U1TXD 4 +#define FUNC_UART1_TXD 4 + +#define PERIPHS_IO_MUX_SD_DATA1_U (PERIPHS_IO_MUX + 0x24) +#define FUNC_SDDATA1 0 +#define FUNC_SPID_MOSI 1 +#define FUNC_GPIO8 3 +#define FUNC_U1RXD 4 +#define FUNC_UART1_RXD 4 + +#define PERIPHS_IO_MUX_SD_DATA2_U (PERIPHS_IO_MUX + 0x28) +#define FUNC_SDDATA2 0 +#define FUNC_SPIHD 1 +#define FUNC_GPIO9 3 +#define UFNC_HSPIHD 4 + +#define PERIPHS_IO_MUX_SD_DATA3_U (PERIPHS_IO_MUX + 0x2c) +#define FUNC_SDDATA3 0 +#define FUNC_SPIWP 1 +#define FUNC_GPIO10 3 +#define FUNC_HSPIWP 4 + +#define PERIPHS_IO_MUX_SD_CMD_U (PERIPHS_IO_MUX + 0x30) +#define FUNC_SDCMD 0 +#define FUNC_SPICS0 1 +#define FUNC_GPIO11 3 +#define U1RTS 4 +#define UART1_RTS 4 + +#define PERIPHS_IO_MUX_GPIO0_U (PERIPHS_IO_MUX + 0x34) +#define FUNC_GPIO0 0 +#define FUNC_SPICS2 1 +#define FUNC_CLK_OUT 4 + +#define PERIPHS_IO_MUX_GPIO2_U (PERIPHS_IO_MUX + 0x38) +#define FUNC_GPIO2 0 +#define FUNC_I2SO_WS 1 +#define FUNC_U1TXD_BK 2 +#define FUNC_UART1_TXD_BK 2 +#define FUNC_U0TXD_BK 4 +#define FUNC_UART0_TXD_BK 4 + +#define PERIPHS_IO_MUX_GPIO4_U (PERIPHS_IO_MUX + 0x3C) +#define FUNC_GPIO4 0 +#define FUNC_CLK_XTAL 1 + +#define PERIPHS_IO_MUX_GPIO5_U (PERIPHS_IO_MUX + 0x40) +#define FUNC_GPIO5 0 +#define FUNC_CLK_RTC 1 + +#define PIN_PULLUP_DIS(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME, PERIPHS_IO_MUX_PULLUP) +#define PIN_PULLUP_EN(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME, PERIPHS_IO_MUX_PULLUP) + +#define PIN_FUNC_SELECT(PIN_NAME, FUNC) do { \ + CLEAR_PERI_REG_MASK(PIN_NAME, (PERIPHS_IO_MUX_FUNC<