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update README.md.

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alainchen
2021-01-24 17:36:32 +08:00
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@ -36,7 +36,12 @@ wire a; reg b; reg c;
另外要注意：当端口的数据长度定义为i（正整数）时，相应的在上述 **第二段、第三段** 代码中要有所改变，在端口名前加[i-1:0]
例如：![输入图片说明](https://images.gitee.com/uploads/images/2021/0123/234717_374091e7_8607408.png "QQ截图20210123234621.png")用户定义了p0为3位
![输入图片说明](https://images.gitee.com/uploads/images/2021/0123/234922_d18c6d0d_8607408.png "QQ截图20210123234626.png") ![输入图片说明](https://images.gitee.com/uploads/images/2021/0123/234930_6490091b_8607408.png "QQ截图20210123234630.png")
则p0前面加[2:0]
则p0前面加[2:0]
### ------------003------------
应有“保存模块”和“生成代码”两个按钮。其中：
保存模块：做到将此次用户新建的模块里的所有内容打包保存 下次用户双击时可以直接在软件里打开
生成代码：将软件生成的代码 让用户选择位置保存。保存为verilog目录 目录下应有此模块及其内部子模块所有的verilog代码文件 扩展名为.v