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Merge remote branch 'qatar/master'
* qatar/master: (23 commits) ac3enc: correct the flipped sign in the ac3_fixed encoder Eliminate pointless '#if 1' statements without matching '#else'. Add AVX FFT implementation. Increase alignment of av_malloc() as needed by AVX ASM. Update x86inc.asm from x264 to allow AVX emulation using SSE and MMX. mjpeg: Detect overreads in mjpeg_decode_scan() and error out. documentation: extend documentation for ffmpeg -aspect option APIChanges: update commit hashes for recent additions. lavc: deprecate FF_*_TYPE macros in favor of AV_PICTURE_TYPE_* enums aac: add headers needed for log2f() lavc: remove FF_API_MB_Q cruft lavc: remove FF_API_RATE_EMU cruft lavc: remove FF_API_HURRY_UP cruft pad: make the filter parametric vsrc_movie: add key_frame and pict_type. vsrc_movie: fix leak in request_frame() lavfi: add key_frame and pict_type to AVFilterBufferRefVideo. vsrc_buffer: add sample_aspect_ratio fields to arguments. lavfi: add fieldorder filter scale: make the filter parametric ... Conflicts: Changelog doc/filters.texi ffmpeg.c libavcodec/ac3dec.h libavcodec/dsputil.c libavfilter/avfilter.h libavfilter/vf_scale.c libavfilter/vf_yadif.c libavfilter/vsrc_buffer.c Merged-by: Michael Niedermayer <michaelni@gmx.at>
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@ -69,21 +69,21 @@ void *av_malloc(size_t size)
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#endif
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/* let's disallow possible ambiguous cases */
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if(size > (INT_MAX-16) )
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if(size > (INT_MAX-32) )
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return NULL;
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#if CONFIG_MEMALIGN_HACK
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ptr = malloc(size+16);
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ptr = malloc(size+32);
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if(!ptr)
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return ptr;
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diff= ((-(long)ptr - 1)&15) + 1;
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diff= ((-(long)ptr - 1)&31) + 1;
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ptr = (char*)ptr + diff;
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((char*)ptr)[-1]= diff;
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#elif HAVE_POSIX_MEMALIGN
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if (posix_memalign(&ptr,16,size))
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if (posix_memalign(&ptr,32,size))
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ptr = NULL;
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#elif HAVE_MEMALIGN
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ptr = memalign(16,size);
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ptr = memalign(32,size);
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/* Why 64?
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Indeed, we should align it:
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on 4 for 386
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@ -93,10 +93,8 @@ void *av_malloc(size_t size)
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Because L1 and L2 caches are aligned on those values.
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But I don't want to code such logic here!
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*/
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/* Why 16?
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Because some CPUs need alignment, for example SSE2 on P4, & most RISC CPUs
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it will just trigger an exception and the unaligned load will be done in the
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exception handler or it will just segfault (SSE2 on P4).
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/* Why 32?
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For AVX ASM. SSE / NEON needs only 16.
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Why not larger? Because I did not see a difference in benchmarks ...
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*/
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/* benchmarks with P3
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