mirror of
https://github.com/go-delve/delve.git
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4c9a72e486
The repository is being switched from the personal account github.com/derekparker/delve to the organization account github.com/go-delve/delve. This patch updates imports and docs, while preserving things which should not be changed such as my name in the CHANGELOG and in TODO comments.
398 lines
9.6 KiB
Go
398 lines
9.6 KiB
Go
package linutil
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import (
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"bytes"
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"encoding/binary"
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"fmt"
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"golang.org/x/arch/x86/x86asm"
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"github.com/go-delve/delve/pkg/proc"
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)
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// AMD64Registers implements the proc.Registers interface for the native/linux
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// backend and core/linux backends, on AMD64.
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type AMD64Registers struct {
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Regs *AMD64PtraceRegs
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Fpregs []proc.Register
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Fpregset *AMD64Xstate
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}
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// AMD64PtraceRegs is the struct used by the linux kernel to return the
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// general purpose registers for AMD64 CPUs.
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type AMD64PtraceRegs struct {
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R15 uint64
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R14 uint64
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R13 uint64
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R12 uint64
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Rbp uint64
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Rbx uint64
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R11 uint64
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R10 uint64
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R9 uint64
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R8 uint64
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Rax uint64
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Rcx uint64
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Rdx uint64
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Rsi uint64
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Rdi uint64
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Orig_rax uint64
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Rip uint64
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Cs uint64
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Eflags uint64
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Rsp uint64
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Ss uint64
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Fs_base uint64
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Gs_base uint64
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Ds uint64
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Es uint64
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Fs uint64
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Gs uint64
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}
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// Slice returns the registers as a list of (name, value) pairs.
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func (r *AMD64Registers) Slice() []proc.Register {
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var regs = []struct {
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k string
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v uint64
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}{
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{"Rip", r.Regs.Rip},
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{"Rsp", r.Regs.Rsp},
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{"Rax", r.Regs.Rax},
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{"Rbx", r.Regs.Rbx},
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{"Rcx", r.Regs.Rcx},
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{"Rdx", r.Regs.Rdx},
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{"Rdi", r.Regs.Rdi},
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{"Rsi", r.Regs.Rsi},
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{"Rbp", r.Regs.Rbp},
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{"R8", r.Regs.R8},
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{"R9", r.Regs.R9},
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{"R10", r.Regs.R10},
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{"R11", r.Regs.R11},
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{"R12", r.Regs.R12},
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{"R13", r.Regs.R13},
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{"R14", r.Regs.R14},
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{"R15", r.Regs.R15},
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{"Orig_rax", r.Regs.Orig_rax},
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{"Cs", r.Regs.Cs},
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{"Eflags", r.Regs.Eflags},
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{"Ss", r.Regs.Ss},
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{"Fs_base", r.Regs.Fs_base},
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{"Gs_base", r.Regs.Gs_base},
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{"Ds", r.Regs.Ds},
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{"Es", r.Regs.Es},
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{"Fs", r.Regs.Fs},
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{"Gs", r.Regs.Gs},
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}
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out := make([]proc.Register, 0, len(regs)+len(r.Fpregs))
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for _, reg := range regs {
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if reg.k == "Eflags" {
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out = proc.AppendEflagReg(out, reg.k, reg.v)
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} else {
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out = proc.AppendQwordReg(out, reg.k, reg.v)
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}
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}
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out = append(out, r.Fpregs...)
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return out
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}
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// PC returns the value of RIP register.
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func (r *AMD64Registers) PC() uint64 {
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return r.Regs.Rip
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}
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// SP returns the value of RSP register.
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func (r *AMD64Registers) SP() uint64 {
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return r.Regs.Rsp
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}
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func (r *AMD64Registers) BP() uint64 {
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return r.Regs.Rbp
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}
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// CX returns the value of RCX register.
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func (r *AMD64Registers) CX() uint64 {
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return r.Regs.Rcx
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}
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// TLS returns the address of the thread local storage memory segment.
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func (r *AMD64Registers) TLS() uint64 {
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return r.Regs.Fs_base
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}
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// GAddr returns the address of the G variable if it is known, 0 and false
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// otherwise.
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func (r *AMD64Registers) GAddr() (uint64, bool) {
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return 0, false
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}
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// Get returns the value of the n-th register (in x86asm order).
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func (r *AMD64Registers) Get(n int) (uint64, error) {
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reg := x86asm.Reg(n)
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const (
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mask8 = 0x000f
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mask16 = 0x00ff
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mask32 = 0xffff
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)
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switch reg {
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// 8-bit
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case x86asm.AL:
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return r.Regs.Rax & mask8, nil
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case x86asm.CL:
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return r.Regs.Rcx & mask8, nil
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case x86asm.DL:
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return r.Regs.Rdx & mask8, nil
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case x86asm.BL:
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return r.Regs.Rbx & mask8, nil
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case x86asm.AH:
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return (r.Regs.Rax >> 8) & mask8, nil
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case x86asm.CH:
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return (r.Regs.Rcx >> 8) & mask8, nil
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case x86asm.DH:
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return (r.Regs.Rdx >> 8) & mask8, nil
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case x86asm.BH:
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return (r.Regs.Rbx >> 8) & mask8, nil
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case x86asm.SPB:
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return r.Regs.Rsp & mask8, nil
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case x86asm.BPB:
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return r.Regs.Rbp & mask8, nil
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case x86asm.SIB:
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return r.Regs.Rsi & mask8, nil
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case x86asm.DIB:
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return r.Regs.Rdi & mask8, nil
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case x86asm.R8B:
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return r.Regs.R8 & mask8, nil
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case x86asm.R9B:
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return r.Regs.R9 & mask8, nil
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case x86asm.R10B:
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return r.Regs.R10 & mask8, nil
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case x86asm.R11B:
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return r.Regs.R11 & mask8, nil
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case x86asm.R12B:
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return r.Regs.R12 & mask8, nil
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case x86asm.R13B:
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return r.Regs.R13 & mask8, nil
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case x86asm.R14B:
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return r.Regs.R14 & mask8, nil
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case x86asm.R15B:
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return r.Regs.R15 & mask8, nil
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// 16-bit
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case x86asm.AX:
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return r.Regs.Rax & mask16, nil
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case x86asm.CX:
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return r.Regs.Rcx & mask16, nil
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case x86asm.DX:
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return r.Regs.Rdx & mask16, nil
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case x86asm.BX:
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return r.Regs.Rbx & mask16, nil
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case x86asm.SP:
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return r.Regs.Rsp & mask16, nil
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case x86asm.BP:
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return r.Regs.Rbp & mask16, nil
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case x86asm.SI:
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return r.Regs.Rsi & mask16, nil
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case x86asm.DI:
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return r.Regs.Rdi & mask16, nil
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case x86asm.R8W:
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return r.Regs.R8 & mask16, nil
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case x86asm.R9W:
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return r.Regs.R9 & mask16, nil
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case x86asm.R10W:
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return r.Regs.R10 & mask16, nil
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case x86asm.R11W:
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return r.Regs.R11 & mask16, nil
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case x86asm.R12W:
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return r.Regs.R12 & mask16, nil
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case x86asm.R13W:
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return r.Regs.R13 & mask16, nil
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case x86asm.R14W:
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return r.Regs.R14 & mask16, nil
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case x86asm.R15W:
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return r.Regs.R15 & mask16, nil
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// 32-bit
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case x86asm.EAX:
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return r.Regs.Rax & mask32, nil
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case x86asm.ECX:
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return r.Regs.Rcx & mask32, nil
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case x86asm.EDX:
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return r.Regs.Rdx & mask32, nil
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case x86asm.EBX:
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return r.Regs.Rbx & mask32, nil
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case x86asm.ESP:
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return r.Regs.Rsp & mask32, nil
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case x86asm.EBP:
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return r.Regs.Rbp & mask32, nil
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case x86asm.ESI:
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return r.Regs.Rsi & mask32, nil
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case x86asm.EDI:
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return r.Regs.Rdi & mask32, nil
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case x86asm.R8L:
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return r.Regs.R8 & mask32, nil
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case x86asm.R9L:
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return r.Regs.R9 & mask32, nil
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case x86asm.R10L:
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return r.Regs.R10 & mask32, nil
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case x86asm.R11L:
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return r.Regs.R11 & mask32, nil
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case x86asm.R12L:
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return r.Regs.R12 & mask32, nil
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case x86asm.R13L:
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return r.Regs.R13 & mask32, nil
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case x86asm.R14L:
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return r.Regs.R14 & mask32, nil
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case x86asm.R15L:
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return r.Regs.R15 & mask32, nil
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// 64-bit
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case x86asm.RAX:
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return r.Regs.Rax, nil
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case x86asm.RCX:
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return r.Regs.Rcx, nil
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case x86asm.RDX:
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return r.Regs.Rdx, nil
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case x86asm.RBX:
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return r.Regs.Rbx, nil
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case x86asm.RSP:
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return r.Regs.Rsp, nil
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case x86asm.RBP:
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return r.Regs.Rbp, nil
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case x86asm.RSI:
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return r.Regs.Rsi, nil
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case x86asm.RDI:
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return r.Regs.Rdi, nil
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case x86asm.R8:
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return r.Regs.R8, nil
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case x86asm.R9:
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return r.Regs.R9, nil
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case x86asm.R10:
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return r.Regs.R10, nil
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case x86asm.R11:
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return r.Regs.R11, nil
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case x86asm.R12:
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return r.Regs.R12, nil
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case x86asm.R13:
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return r.Regs.R13, nil
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case x86asm.R14:
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return r.Regs.R14, nil
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case x86asm.R15:
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return r.Regs.R15, nil
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}
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return 0, proc.ErrUnknownRegister
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}
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// Copy returns a copy of these registers that is guarenteed not to change.
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func (r *AMD64Registers) Copy() proc.Registers {
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var rr AMD64Registers
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rr.Regs = &AMD64PtraceRegs{}
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rr.Fpregset = &AMD64Xstate{}
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*(rr.Regs) = *(r.Regs)
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if r.Fpregset != nil {
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*(rr.Fpregset) = *(r.Fpregset)
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}
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if r.Fpregs != nil {
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rr.Fpregs = make([]proc.Register, len(r.Fpregs))
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copy(rr.Fpregs, r.Fpregs)
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}
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return &rr
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}
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// AMD64PtraceFpRegs tracks user_fpregs_struct in /usr/include/x86_64-linux-gnu/sys/user.h
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type AMD64PtraceFpRegs struct {
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Cwd uint16
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Swd uint16
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Ftw uint16
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Fop uint16
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Rip uint64
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Rdp uint64
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Mxcsr uint32
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MxcrMask uint32
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StSpace [32]uint32
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XmmSpace [256]byte
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Padding [24]uint32
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}
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// AMD64Xstate represents amd64 XSAVE area. See Section 13.1 (and
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// following) of Intel® 64 and IA-32 Architectures Software Developer’s
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// Manual, Volume 1: Basic Architecture.
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type AMD64Xstate struct {
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AMD64PtraceFpRegs
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Xsave []byte // raw xsave area
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AvxState bool // contains AVX state
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YmmSpace [256]byte
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}
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// Decode decodes an XSAVE area to a list of name/value pairs of registers.
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func (xsave *AMD64Xstate) Decode() (regs []proc.Register) {
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// x87 registers
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regs = proc.AppendWordReg(regs, "CW", xsave.Cwd)
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regs = proc.AppendWordReg(regs, "SW", xsave.Swd)
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regs = proc.AppendWordReg(regs, "TW", xsave.Ftw)
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regs = proc.AppendWordReg(regs, "FOP", xsave.Fop)
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regs = proc.AppendQwordReg(regs, "FIP", xsave.Rip)
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regs = proc.AppendQwordReg(regs, "FDP", xsave.Rdp)
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for i := 0; i < len(xsave.StSpace); i += 4 {
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regs = proc.AppendX87Reg(regs, i/4, uint16(xsave.StSpace[i+2]), uint64(xsave.StSpace[i+1])<<32|uint64(xsave.StSpace[i]))
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}
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// SSE registers
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regs = proc.AppendMxcsrReg(regs, "MXCSR", uint64(xsave.Mxcsr))
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regs = proc.AppendDwordReg(regs, "MXCSR_MASK", xsave.MxcrMask)
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for i := 0; i < len(xsave.XmmSpace); i += 16 {
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regs = proc.AppendSSEReg(regs, fmt.Sprintf("XMM%d", i/16), xsave.XmmSpace[i:i+16])
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if xsave.AvxState {
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regs = proc.AppendSSEReg(regs, fmt.Sprintf("YMM%d", i/16), xsave.YmmSpace[i:i+16])
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}
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}
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return
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}
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const (
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_XSAVE_HEADER_START = 512
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_XSAVE_HEADER_LEN = 64
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_XSAVE_EXTENDED_REGION_START = 576
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_XSAVE_SSE_REGION_LEN = 416
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)
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// LinuxX86XstateRead reads a byte array containing an XSAVE area into regset.
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// If readLegacy is true regset.PtraceFpRegs will be filled with the
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// contents of the legacy region of the XSAVE area.
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// See Section 13.1 (and following) of Intel® 64 and IA-32 Architectures
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// Software Developer’s Manual, Volume 1: Basic Architecture.
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func AMD64XstateRead(xstateargs []byte, readLegacy bool, regset *AMD64Xstate) error {
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if _XSAVE_HEADER_START+_XSAVE_HEADER_LEN >= len(xstateargs) {
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return nil
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}
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if readLegacy {
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rdr := bytes.NewReader(xstateargs[:_XSAVE_HEADER_START])
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if err := binary.Read(rdr, binary.LittleEndian, ®set.AMD64PtraceFpRegs); err != nil {
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return err
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}
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}
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xsaveheader := xstateargs[_XSAVE_HEADER_START : _XSAVE_HEADER_START+_XSAVE_HEADER_LEN]
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xstate_bv := binary.LittleEndian.Uint64(xsaveheader[0:8])
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xcomp_bv := binary.LittleEndian.Uint64(xsaveheader[8:16])
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if xcomp_bv&(1<<63) != 0 {
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// compact format not supported
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return nil
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}
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if xstate_bv&(1<<2) == 0 {
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// AVX state not present
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return nil
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}
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avxstate := xstateargs[_XSAVE_EXTENDED_REGION_START:]
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regset.AvxState = true
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copy(regset.YmmSpace[:], avxstate[:len(regset.YmmSpace)])
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return nil
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}
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