espressif/esp32-camera
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Add experimental double FPS mode for OV2640

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Allows for 52fps@CIF, 26fps@SVGA and 6.5fps@UXGA (unchanged) when XCLK is set to 10MHz
This commit is contained in:
me-no-dev
2019-01-26 21:33:23 +01:00
parent 165a47fe6a
commit 10b3d3c2a9
6 changed files with 17 additions and 2 deletions
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3
README.md
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@ -44,6 +44,7 @@ This repository hosts ESP32 compatible driver for OV2640 image sensors. Addition
#define CAM_PIN_PCLK 22 #define CAM_PIN_PCLK 22
static camera_config_t camera_config = { static camera_config_t camera_config = {
.pin_pwdn = CAM_PIN_PWDN,
.pin_reset = CAM_PIN_RESET, .pin_reset = CAM_PIN_RESET,
.pin_xclk = CAM_PIN_XCLK, .pin_xclk = CAM_PIN_XCLK,
.pin_sscb_sda = CAM_PIN_SIOD, .pin_sscb_sda = CAM_PIN_SIOD,
@ -61,7 +62,7 @@ static camera_config_t camera_config = {
.pin_href = CAM_PIN_HREF, .pin_href = CAM_PIN_HREF,
.pin_pclk = CAM_PIN_PCLK, .pin_pclk = CAM_PIN_PCLK,
//XCLK 20MHz or 10MHz //XCLK 20MHz or 10MHz for OV2640 double FPS (Experimental)
.xclk_freq_hz = 20000000, .xclk_freq_hz = 20000000,
.ledc_timer = LEDC_TIMER_0, .ledc_timer = LEDC_TIMER_0,
.ledc_channel = LEDC_CHANNEL_0, .ledc_channel = LEDC_CHANNEL_0,

1
driver/camera.c
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@ -884,6 +884,7 @@ esp_err_t camera_probe(const camera_config_t* config, camera_model_t* out_camera
return ESP_ERR_CAMERA_NOT_DETECTED; return ESP_ERR_CAMERA_NOT_DETECTED;
} }
s_state->sensor.slv_addr = slv_addr; s_state->sensor.slv_addr = slv_addr;
s_state->sensor.xclk_freq_hz = config->xclk_freq_hz;
//s_state->sensor.slv_addr = 0x30; //s_state->sensor.slv_addr = 0x30;
ESP_LOGD(TAG, "Detected camera at address=0x%02x", s_state->sensor.slv_addr); ESP_LOGD(TAG, "Detected camera at address=0x%02x", s_state->sensor.slv_addr);

2
driver/include/esp_camera.h
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@ -94,7 +94,7 @@ typedef struct {
int pin_href; /*!< GPIO pin for camera HREF line */ int pin_href; /*!< GPIO pin for camera HREF line */
int pin_pclk; /*!< GPIO pin for camera PCLK line */ int pin_pclk; /*!< GPIO pin for camera PCLK line */
int xclk_freq_hz; /*!< Frequency of XCLK signal, in Hz. Either 10KHz or 20KHz */ int xclk_freq_hz; /*!< Frequency of XCLK signal, in Hz. Either 20KHz or 10KHz for OV2640 double FPS (Experimental) */
ledc_timer_t ledc_timer; /*!< LEDC timer to be used for generating XCLK */ ledc_timer_t ledc_timer; /*!< LEDC timer to be used for generating XCLK */
ledc_channel_t ledc_channel; /*!< LEDC channel to be used for generating XCLK */ ledc_channel_t ledc_channel; /*!< LEDC channel to be used for generating XCLK */

1
driver/include/sensor.h
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@ -86,6 +86,7 @@ typedef struct _sensor {
uint8_t slv_addr; // Sensor I2C slave address. uint8_t slv_addr; // Sensor I2C slave address.
pixformat_t pixformat; pixformat_t pixformat;
camera_status_t status; camera_status_t status;
int xclk_freq_hz;
// Sensor function pointers // Sensor function pointers
int (*init_status) (sensor_t *sensor); int (*init_status) (sensor_t *sensor);

9
sensors/ov2640.c
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@ -241,6 +241,15 @@ static int set_framesize(sensor_t *sensor, framesize_t framesize)
WRITE_REG_OR_RETURN(BANK_DSP, R_BYPASS, R_BYPASS_DSP_BYPAS); WRITE_REG_OR_RETURN(BANK_DSP, R_BYPASS, R_BYPASS_DSP_BYPAS);
WRITE_REGS_OR_RETURN(regs); WRITE_REGS_OR_RETURN(regs);
if (sensor->xclk_freq_hz == 10000000) {
if (framesize <= FRAMESIZE_CIF) {
WRITE_REG_OR_RETURN(BANK_SENSOR, CLKRC, CLKRC_2X_CIF);
} else if (framesize <= FRAMESIZE_SVGA) {
WRITE_REG_OR_RETURN(BANK_SENSOR, CLKRC, CLKRC_2X_SVGA);
} else {
WRITE_REG_OR_RETURN(BANK_SENSOR, CLKRC, CLKRC_2X_UXGA);
}
}
WRITE_REG_OR_RETURN(BANK_DSP, ZMOW, (w>>2)&0xFF); // OUTW[7:0] (real/4) WRITE_REG_OR_RETURN(BANK_DSP, ZMOW, (w>>2)&0xFF); // OUTW[7:0] (real/4)
WRITE_REG_OR_RETURN(BANK_DSP, ZMOH, (h>>2)&0xFF); // OUTH[7:0] (real/4) WRITE_REG_OR_RETURN(BANK_DSP, ZMOH, (h>>2)&0xFF); // OUTH[7:0] (real/4)
WRITE_REG_OR_RETURN(BANK_DSP, ZMHH, ((h>>8)&0x04)|((w>>10)&0x03)); // OUTH[8]/OUTW[9:8] WRITE_REG_OR_RETURN(BANK_DSP, ZMHH, ((h>>8)&0x04)|((w>>10)&0x03)); // OUTH[8]/OUTW[9:8]

3
sensors/private_include/ov2640_regs.h
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@ -209,5 +209,8 @@ typedef enum {
#define REG32_CIF 0x89 #define REG32_CIF 0x89
#define CLKRC_2X 0x80 #define CLKRC_2X 0x80
#define CLKRC_2X_UXGA (0x01 | CLKRC_2X)
#define CLKRC_2X_SVGA CLKRC_2X
#define CLKRC_2X_CIF CLKRC_2X
#endif //__REG_REGS_H__ #endif //__REG_REGS_H__