Andrew Waterman f98d33be3a Add SFENCE.VMA instruction ...

include/ChangeLog:

2017-02-14  Andrew Waterman  <andrew@sifive.com>

        * opcode/riscv-opc.h (MATCH_SFENCE_VMA): New define.
        (MASK_SFENCE_VMA): Likewise.
        (sfence_vma): Declare instruction.

opcodes/ChangeLog:

2017-02-14  Andrew Waterman  <andrew@sifive.com>

        * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
        pseudoinstructions.

2017-02-15 10:35:00 -08:00

..

aarch64.h

[AArch64] Add separate feature flag for weaker release consistent load insns

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alpha.h

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arc-func.h

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arc.h

[ARC] Provide an interface to decode ARC instructions.

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arm.h

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avr.h

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bfin.h

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cgen.h

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ChangeLog-0415

binutils ChangeLog rotation

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ChangeLog-9103

Add copyright notices

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convex.h

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cr16.h

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cris.h

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crx.h

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d10v.h

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d30v.h

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dlx.h

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ft32.h

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h8300.h

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hppa.h

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i370.h

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i386.h

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i860.h

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i960.h

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ia64.h

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m68hc11.h

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m68k.h

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m88k.h

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metag.h

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mips.h

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mmix.h

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mn10200.h

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mn10300.h

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moxie.h

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msp430-decode.h

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msp430.h

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nds32.h

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nios2.h

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nios2r1.h

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nios2r2.h

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np1.h

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ns32k.h

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pdp11.h

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pj.h

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pn.h

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ppc.h

PowerPC register expression checks

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pru.h

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pyr.h

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riscv-opc.h

Add SFENCE.VMA instruction

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riscv.h

Add support for the Q extension to the RISCV ISA.

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rl78.h

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rx.h

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s390.h

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score-datadep.h

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score-inst.h

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sparc.h

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spu-insns.h

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spu.h

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tahoe.h

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tic4x.h

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tic6x-control-registers.h

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tic6x-insn-formats.h

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tic6x-opcode-table.h

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tic6x.h

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tic30.h

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tic54x.h

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tic80.h

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tilegx.h

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tilepro.h

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v850.h

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vax.h

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visium.h

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xgate.h

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