Files
binutils-gdb/sim/testsuite/riscv/jalr.s
Jaydeep Patil 3224e32fb8 sim: riscv: Add support for compressed integer instructions
Added support for simulation of compressed integer instruction set ("c").
Added test file sim/testsuite/riscv/c-ext.s to test compressed instructions.
The compressed instructions are available for models implementing C extension.
Such as RV32IC, RV64IC, RV32GC, RV64GC etc.

Approved-By: Andrew Burgess <aburgess@redhat.com>
2024-02-13 11:04:04 +00:00

23 lines
348 B
ArmAsm

# Basic jalr tests.
# mach: riscv32 riscv64
.include "testutils.inc"
start
# Load desination into register a0.
la a0, good_dest
# Jump to the destination in a0.
jalr a0, a0, 0
# If we write destination into a0 before reading it in order
# to jump, we might end up here.
bad_dest:
fail
# We should end up here.
good_dest:
pass
fail