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75d74ccace
On the MIPS target DSP ASE registers can only be accessed with the
PTRACE_PEEKUSR and PTRACE_POKEUSR `ptrace' requests. With the n32 ABI
these requests only pass 32-bit data quantities, which are narrower than
the width of DSP accumulator registers, which are 64-bit.
Generic code is prepared to transfer registers wider than the `ptrace'
data type by offsetting into the USR address space, by the data width
transferred. That however does not work with the MIPS target, because
of how the API has been defined, where USR register addresses are
actually indices rather than offsets. Consequently given address `a'
using `a + 4' accesses the fourth next register rather than the upper
half of the original register.
With native debugging this causes clobbered register contents, as well
as access failures as locations beyond the available USR space are
addressed:
(gdb) info registers
zero at v0 v1
R0 0000000000000000 0000000000000001 0000000000000001 0000000000000000
a0 a1 a2 a3
R4 0000000010019158 0000000000000000 0000000000000011 0000000010019160
a4 a5 a6 a7
R8 0000000010019160 fffffffffff00000 fffffffffffffff8 0000000000000000
t0 t1 t2 t3
R12 0000000010019150 0000000000000001 0000000000000001 000000000000000f
s0 s1 s2 s3
R16 0000000077ee6f20 0000000010007bb0 0000000000000000 0000000000000000
s4 s5 s6 s7
R20 000000000052e668 000000000052f008 0000000000000000 0000000000000000
t8 t9 k0 k1
R24 0000000000000001 0000000010019010 0000000000000000 0000000000000000
gp sp s8 ra
R28 0000000010020280 000000007fff4c10 000000007fff4c10 0000000010004f48
status lo hi badvaddr
0000000000109cf3 0000000000943efe 000000000000000e 000000001001900c
cause pc
0000000000800024 0000000010004f48
fcsr fir hi1 lo1
0e800000 00f30000 0000000004040404 0101010105050505
hi2 lo2 hi3 lo3
0202020255aa33cc Couldn't read register (#75): Input/output error.
(gdb)
With `gdbserver' this makes debugging impossible due to a fatal failure:
(gdb) target remote :2346
Remote debugging using :2346
Reading symbols from .../sysroot/mips-r2-hard/lib32/ld.so.1...done.
0x77fc3d50 in __start () from .../sysroot/mips-r2-hard/lib32/ld.so.1
(gdb) continue
Continuing.
warning: Remote failure reply: E01
Remote communication error. Target disconnected.: Connection reset by peer.
(gdb)
Correct the problem by marking any register in the MIPS backend whose
width exceeds the width of the `ptrace' data type unavailable for the
purpose of PTRACE_PEEKUSR and PTRACE_POKEUSR requests:
(gdb) info registers
zero at v0 v1
R0 0000000000000000 0000000000000001 0000000000000001 0000000000000000
a0 a1 a2 a3
R4 0000000010019158 0000000000000000 0000000000000011 0000000010019160
a4 a5 a6 a7
R8 0000000010019160 fffffffffff00000 fffffffffffffff8 0000000000000000
t0 t1 t2 t3
R12 0000000010019150 0000000000000001 0000000000000001 000000000000000f
s0 s1 s2 s3
R16 0000000077ee6f20 0000000010007bb0 0000000000000000 0000000000000000
s4 s5 s6 s7
R20 000000000052e5c8 000000000052f008 0000000000000000 0000000000000000
t8 t9 k0 k1
R24 0000000000000001 0000000010019010 0000000000000000 0000000000000000
gp sp s8 ra
R28 0000000010020280 000000007fff4be0 000000007fff4be0 0000000010004f48
status lo hi badvaddr
0000000000109cf3 0000000000943efe 000000000000000e 000000001001900c
cause pc
0000000000800024 0000000010004f48
fcsr fir hi1 lo1
0e800000 00f30000 <unavailable> <unavailable>
hi2 lo2 hi3 lo3
<unavailable> <unavailable> <unavailable> <unavailable>
dspctl restart
55aa33cc 0000000000000000
(gdb)
as there is no way to access full contents of these registers with the
limited API available anyway.
This obviously does not affect general-purpose registers (which use the
PTRACE_GETREGS and PTRACE_SETREGS requests for access) or floating-point
general registers (which use PTRACE_GETFPREGS and PTRACE_SETFPREGS).
And $dspctl, being 32-bit, remains accessible too, which is important
for BPOSGE32 branch decoding in single-stepping.
For DSP accumulator access with the n32 ABI a new `ptrace' API is required
on the kernel side.
gdb/
* mips-linux-nat.c (mips64_linux_register_addr): Return -1 if
the width of the requested register exceeds the width of the
`ptrace' data type.
gdb/gdbserver/
* linux-mips-low.c (mips_cannot_fetch_register): Return 1 if the
width of the requested register exceeds the width of the
`ptrace' data type.
(mips_cannot_store_register): Likewise.
818 lines
23 KiB
C
818 lines
23 KiB
C
/* Native-dependent code for GNU/Linux on MIPS processors.
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Copyright (C) 2001-2018 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "defs.h"
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#include "command.h"
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#include "gdbcmd.h"
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#include "inferior.h"
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#include "mips-tdep.h"
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#include "target.h"
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#include "regcache.h"
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#include "linux-nat-trad.h"
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#include "mips-linux-tdep.h"
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#include "target-descriptions.h"
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#include "gdb_proc_service.h"
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#include "gregset.h"
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#include <sgidefs.h>
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#include "nat/gdb_ptrace.h"
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#include <asm/ptrace.h>
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#include "inf-ptrace.h"
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#include "nat/mips-linux-watch.h"
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#ifndef PTRACE_GET_THREAD_AREA
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#define PTRACE_GET_THREAD_AREA 25
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#endif
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class mips_linux_nat_target final : public linux_nat_trad_target
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{
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public:
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/* Add our register access methods. */
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void fetch_registers (struct regcache *, int) override;
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void store_registers (struct regcache *, int) override;
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void close () override;
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int can_use_hw_breakpoint (enum bptype, int, int) override;
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int remove_watchpoint (CORE_ADDR, int, enum target_hw_bp_type,
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struct expression *) override;
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int insert_watchpoint (CORE_ADDR, int, enum target_hw_bp_type,
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struct expression *) override;
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bool stopped_by_watchpoint () override;
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bool stopped_data_address (CORE_ADDR *) override;
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int region_ok_for_hw_watchpoint (CORE_ADDR, int) override;
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const struct target_desc *read_description () override;
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protected:
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/* Override linux_nat_trad_target methods. */
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CORE_ADDR register_u_offset (struct gdbarch *gdbarch,
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int regno, int store_p) override;
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/* Override linux_nat_target low methods. */
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void low_new_thread (struct lwp_info *lp) override;
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private:
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/* Helpers. See definitions. */
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void mips64_regsets_store_registers (struct regcache *regcache,
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int regno);
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void mips64_regsets_fetch_registers (struct regcache *regcache,
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int regno);
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};
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static mips_linux_nat_target the_mips_linux_nat_target;
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/* Assume that we have PTRACE_GETREGS et al. support. If we do not,
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we'll clear this and use PTRACE_PEEKUSER instead. */
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static int have_ptrace_regsets = 1;
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/* Map gdb internal register number to ptrace ``address''.
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These ``addresses'' are normally defined in <asm/ptrace.h>.
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ptrace does not provide a way to read (or set) MIPS_PS_REGNUM,
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and there's no point in reading or setting MIPS_ZERO_REGNUM.
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We also can not set BADVADDR, CAUSE, or FCRIR via ptrace(). */
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static CORE_ADDR
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mips_linux_register_addr (struct gdbarch *gdbarch, int regno, int store)
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{
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CORE_ADDR regaddr;
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if (regno < 0 || regno >= gdbarch_num_regs (gdbarch))
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error (_("Bogon register number %d."), regno);
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if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32)
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regaddr = regno;
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else if ((regno >= mips_regnum (gdbarch)->fp0)
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&& (regno < mips_regnum (gdbarch)->fp0 + 32))
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regaddr = FPR_BASE + (regno - mips_regnum (gdbarch)->fp0);
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else if (regno == mips_regnum (gdbarch)->pc)
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regaddr = PC;
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else if (regno == mips_regnum (gdbarch)->cause)
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regaddr = store? (CORE_ADDR) -1 : CAUSE;
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else if (regno == mips_regnum (gdbarch)->badvaddr)
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regaddr = store? (CORE_ADDR) -1 : BADVADDR;
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else if (regno == mips_regnum (gdbarch)->lo)
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regaddr = MMLO;
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else if (regno == mips_regnum (gdbarch)->hi)
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regaddr = MMHI;
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else if (regno == mips_regnum (gdbarch)->fp_control_status)
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regaddr = FPC_CSR;
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else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
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regaddr = store? (CORE_ADDR) -1 : FPC_EIR;
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else if (mips_regnum (gdbarch)->dspacc != -1
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&& regno >= mips_regnum (gdbarch)->dspacc
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&& regno < mips_regnum (gdbarch)->dspacc + 6)
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regaddr = DSP_BASE + (regno - mips_regnum (gdbarch)->dspacc);
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else if (regno == mips_regnum (gdbarch)->dspctl)
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regaddr = DSP_CONTROL;
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else if (mips_linux_restart_reg_p (gdbarch) && regno == MIPS_RESTART_REGNUM)
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regaddr = 0;
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else
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regaddr = (CORE_ADDR) -1;
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return regaddr;
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}
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static CORE_ADDR
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mips64_linux_register_addr (struct gdbarch *gdbarch, int regno, int store)
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{
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CORE_ADDR regaddr;
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if (regno < 0 || regno >= gdbarch_num_regs (gdbarch))
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error (_("Bogon register number %d."), regno);
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/* On n32 we can't access 64-bit registers via PTRACE_PEEKUSR
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or PTRACE_POKEUSR. */
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if (register_size (gdbarch, regno) > sizeof (PTRACE_TYPE_RET))
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return (CORE_ADDR) -1;
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if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32)
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regaddr = regno;
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else if ((regno >= mips_regnum (gdbarch)->fp0)
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&& (regno < mips_regnum (gdbarch)->fp0 + 32))
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regaddr = MIPS64_FPR_BASE + (regno - gdbarch_fp0_regnum (gdbarch));
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else if (regno == mips_regnum (gdbarch)->pc)
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regaddr = MIPS64_PC;
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else if (regno == mips_regnum (gdbarch)->cause)
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regaddr = store? (CORE_ADDR) -1 : MIPS64_CAUSE;
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else if (regno == mips_regnum (gdbarch)->badvaddr)
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regaddr = store? (CORE_ADDR) -1 : MIPS64_BADVADDR;
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else if (regno == mips_regnum (gdbarch)->lo)
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regaddr = MIPS64_MMLO;
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else if (regno == mips_regnum (gdbarch)->hi)
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regaddr = MIPS64_MMHI;
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else if (regno == mips_regnum (gdbarch)->fp_control_status)
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regaddr = MIPS64_FPC_CSR;
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else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
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regaddr = store? (CORE_ADDR) -1 : MIPS64_FPC_EIR;
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else if (mips_regnum (gdbarch)->dspacc != -1
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&& regno >= mips_regnum (gdbarch)->dspacc
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&& regno < mips_regnum (gdbarch)->dspacc + 6)
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regaddr = DSP_BASE + (regno - mips_regnum (gdbarch)->dspacc);
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else if (regno == mips_regnum (gdbarch)->dspctl)
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regaddr = DSP_CONTROL;
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else if (mips_linux_restart_reg_p (gdbarch) && regno == MIPS_RESTART_REGNUM)
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regaddr = 0;
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else
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regaddr = (CORE_ADDR) -1;
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return regaddr;
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}
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/* Fetch the thread-local storage pointer for libthread_db. */
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ps_err_e
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ps_get_thread_area (struct ps_prochandle *ph,
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lwpid_t lwpid, int idx, void **base)
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{
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if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0)
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return PS_ERR;
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/* IDX is the bias from the thread pointer to the beginning of the
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thread descriptor. It has to be subtracted due to implementation
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quirks in libthread_db. */
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*base = (void *) ((char *)*base - idx);
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return PS_OK;
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}
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/* Wrapper functions. These are only used by libthread_db. */
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void
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supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp)
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{
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if (mips_isa_regsize (regcache->arch ()) == 4)
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mips_supply_gregset (regcache, (const mips_elf_gregset_t *) gregsetp);
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else
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mips64_supply_gregset (regcache, (const mips64_elf_gregset_t *) gregsetp);
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}
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void
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fill_gregset (const struct regcache *regcache,
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gdb_gregset_t *gregsetp, int regno)
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{
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if (mips_isa_regsize (regcache->arch ()) == 4)
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mips_fill_gregset (regcache, (mips_elf_gregset_t *) gregsetp, regno);
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else
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mips64_fill_gregset (regcache, (mips64_elf_gregset_t *) gregsetp, regno);
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}
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void
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supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp)
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{
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if (mips_isa_regsize (regcache->arch ()) == 4)
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mips_supply_fpregset (regcache, (const mips_elf_fpregset_t *) fpregsetp);
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else
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mips64_supply_fpregset (regcache,
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(const mips64_elf_fpregset_t *) fpregsetp);
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}
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void
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fill_fpregset (const struct regcache *regcache,
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gdb_fpregset_t *fpregsetp, int regno)
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{
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if (mips_isa_regsize (regcache->arch ()) == 4)
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mips_fill_fpregset (regcache, (mips_elf_fpregset_t *) fpregsetp, regno);
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else
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mips64_fill_fpregset (regcache,
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(mips64_elf_fpregset_t *) fpregsetp, regno);
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}
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/* Fetch REGNO (or all registers if REGNO == -1) from the target
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using PTRACE_GETREGS et al. */
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void
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mips_linux_nat_target::mips64_regsets_fetch_registers
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(struct regcache *regcache, int regno)
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{
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struct gdbarch *gdbarch = regcache->arch ();
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int is_fp, is_dsp;
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int have_dsp;
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int regi;
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int tid;
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if (regno >= mips_regnum (gdbarch)->fp0
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&& regno <= mips_regnum (gdbarch)->fp0 + 32)
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is_fp = 1;
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else if (regno == mips_regnum (gdbarch)->fp_control_status)
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is_fp = 1;
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else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
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is_fp = 1;
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else
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is_fp = 0;
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/* DSP registers are optional and not a part of any set. */
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have_dsp = mips_regnum (gdbarch)->dspctl != -1;
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if (!have_dsp)
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is_dsp = 0;
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else if (regno >= mips_regnum (gdbarch)->dspacc
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&& regno < mips_regnum (gdbarch)->dspacc + 6)
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is_dsp = 1;
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else if (regno == mips_regnum (gdbarch)->dspctl)
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is_dsp = 1;
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else
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is_dsp = 0;
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tid = get_ptrace_pid (regcache_get_ptid (regcache));
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if (regno == -1 || (!is_fp && !is_dsp))
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{
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mips64_elf_gregset_t regs;
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if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1)
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{
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if (errno == EIO)
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{
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have_ptrace_regsets = 0;
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return;
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}
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perror_with_name (_("Couldn't get registers"));
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}
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mips64_supply_gregset (regcache,
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(const mips64_elf_gregset_t *) ®s);
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}
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if (regno == -1 || is_fp)
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{
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mips64_elf_fpregset_t fp_regs;
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if (ptrace (PTRACE_GETFPREGS, tid, 0L,
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(PTRACE_TYPE_ARG3) &fp_regs) == -1)
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{
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if (errno == EIO)
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{
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have_ptrace_regsets = 0;
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return;
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}
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perror_with_name (_("Couldn't get FP registers"));
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}
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mips64_supply_fpregset (regcache,
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(const mips64_elf_fpregset_t *) &fp_regs);
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}
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if (is_dsp)
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linux_nat_trad_target::fetch_registers (regcache, regno);
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else if (regno == -1 && have_dsp)
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{
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for (regi = mips_regnum (gdbarch)->dspacc;
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regi < mips_regnum (gdbarch)->dspacc + 6;
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regi++)
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linux_nat_trad_target::fetch_registers (regcache, regi);
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linux_nat_trad_target::fetch_registers (regcache,
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mips_regnum (gdbarch)->dspctl);
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}
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}
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/* Store REGNO (or all registers if REGNO == -1) to the target
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using PTRACE_SETREGS et al. */
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void
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mips_linux_nat_target::mips64_regsets_store_registers
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(struct regcache *regcache, int regno)
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{
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struct gdbarch *gdbarch = regcache->arch ();
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int is_fp, is_dsp;
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int have_dsp;
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int regi;
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int tid;
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if (regno >= mips_regnum (gdbarch)->fp0
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&& regno <= mips_regnum (gdbarch)->fp0 + 32)
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is_fp = 1;
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else if (regno == mips_regnum (gdbarch)->fp_control_status)
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is_fp = 1;
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else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
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is_fp = 1;
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else
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is_fp = 0;
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/* DSP registers are optional and not a part of any set. */
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have_dsp = mips_regnum (gdbarch)->dspctl != -1;
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if (!have_dsp)
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is_dsp = 0;
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else if (regno >= mips_regnum (gdbarch)->dspacc
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&& regno < mips_regnum (gdbarch)->dspacc + 6)
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is_dsp = 1;
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else if (regno == mips_regnum (gdbarch)->dspctl)
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is_dsp = 1;
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else
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is_dsp = 0;
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tid = get_ptrace_pid (regcache_get_ptid (regcache));
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if (regno == -1 || (!is_fp && !is_dsp))
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{
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mips64_elf_gregset_t regs;
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if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1)
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perror_with_name (_("Couldn't get registers"));
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mips64_fill_gregset (regcache, ®s, regno);
|
|
|
|
if (ptrace (PTRACE_SETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1)
|
|
perror_with_name (_("Couldn't set registers"));
|
|
}
|
|
|
|
if (regno == -1 || is_fp)
|
|
{
|
|
mips64_elf_fpregset_t fp_regs;
|
|
|
|
if (ptrace (PTRACE_GETFPREGS, tid, 0L,
|
|
(PTRACE_TYPE_ARG3) &fp_regs) == -1)
|
|
perror_with_name (_("Couldn't get FP registers"));
|
|
|
|
mips64_fill_fpregset (regcache, &fp_regs, regno);
|
|
|
|
if (ptrace (PTRACE_SETFPREGS, tid, 0L,
|
|
(PTRACE_TYPE_ARG3) &fp_regs) == -1)
|
|
perror_with_name (_("Couldn't set FP registers"));
|
|
}
|
|
|
|
if (is_dsp)
|
|
linux_nat_trad_target::store_registers (regcache, regno);
|
|
else if (regno == -1 && have_dsp)
|
|
{
|
|
for (regi = mips_regnum (gdbarch)->dspacc;
|
|
regi < mips_regnum (gdbarch)->dspacc + 6;
|
|
regi++)
|
|
linux_nat_trad_target::store_registers (regcache, regi);
|
|
linux_nat_trad_target::store_registers (regcache,
|
|
mips_regnum (gdbarch)->dspctl);
|
|
}
|
|
}
|
|
|
|
/* Fetch REGNO (or all registers if REGNO == -1) from the target
|
|
using any working method. */
|
|
|
|
void
|
|
mips_linux_nat_target::fetch_registers (struct regcache *regcache, int regnum)
|
|
{
|
|
/* Unless we already know that PTRACE_GETREGS does not work, try it. */
|
|
if (have_ptrace_regsets)
|
|
mips64_regsets_fetch_registers (regcache, regnum);
|
|
|
|
/* If we know, or just found out, that PTRACE_GETREGS does not work, fall
|
|
back to PTRACE_PEEKUSER. */
|
|
if (!have_ptrace_regsets)
|
|
{
|
|
linux_nat_trad_target::fetch_registers (regcache, regnum);
|
|
|
|
/* Fill the inaccessible zero register with zero. */
|
|
if (regnum == MIPS_ZERO_REGNUM || regnum == -1)
|
|
regcache->raw_supply_zeroed (MIPS_ZERO_REGNUM);
|
|
}
|
|
}
|
|
|
|
/* Store REGNO (or all registers if REGNO == -1) to the target
|
|
using any working method. */
|
|
|
|
void
|
|
mips_linux_nat_target::store_registers (struct regcache *regcache, int regnum)
|
|
{
|
|
/* Unless we already know that PTRACE_GETREGS does not work, try it. */
|
|
if (have_ptrace_regsets)
|
|
mips64_regsets_store_registers (regcache, regnum);
|
|
|
|
/* If we know, or just found out, that PTRACE_GETREGS does not work, fall
|
|
back to PTRACE_PEEKUSER. */
|
|
if (!have_ptrace_regsets)
|
|
linux_nat_trad_target::store_registers (regcache, regnum);
|
|
}
|
|
|
|
/* Return the address in the core dump or inferior of register
|
|
REGNO. */
|
|
|
|
CORE_ADDR
|
|
mips_linux_nat_target::register_u_offset (struct gdbarch *gdbarch,
|
|
int regno, int store_p)
|
|
{
|
|
if (mips_abi_regsize (gdbarch) == 8)
|
|
return mips64_linux_register_addr (gdbarch, regno, store_p);
|
|
else
|
|
return mips_linux_register_addr (gdbarch, regno, store_p);
|
|
}
|
|
|
|
const struct target_desc *
|
|
mips_linux_nat_target::read_description ()
|
|
{
|
|
static int have_dsp = -1;
|
|
|
|
if (have_dsp < 0)
|
|
{
|
|
int tid;
|
|
|
|
tid = ptid_get_lwp (inferior_ptid);
|
|
if (tid == 0)
|
|
tid = ptid_get_pid (inferior_ptid);
|
|
|
|
errno = 0;
|
|
ptrace (PTRACE_PEEKUSER, tid, DSP_CONTROL, 0);
|
|
switch (errno)
|
|
{
|
|
case 0:
|
|
have_dsp = 1;
|
|
break;
|
|
case EIO:
|
|
have_dsp = 0;
|
|
break;
|
|
default:
|
|
perror_with_name (_("Couldn't check DSP support"));
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* Report that target registers are a size we know for sure
|
|
that we can get from ptrace. */
|
|
if (_MIPS_SIM == _ABIO32)
|
|
return have_dsp ? tdesc_mips_dsp_linux : tdesc_mips_linux;
|
|
else
|
|
return have_dsp ? tdesc_mips64_dsp_linux : tdesc_mips64_linux;
|
|
}
|
|
|
|
/* -1 if the kernel and/or CPU do not support watch registers.
|
|
1 if watch_readback is valid and we can read style, num_valid
|
|
and the masks.
|
|
0 if we need to read the watch_readback. */
|
|
|
|
static int watch_readback_valid;
|
|
|
|
/* Cached watch register read values. */
|
|
|
|
static struct pt_watch_regs watch_readback;
|
|
|
|
static struct mips_watchpoint *current_watches;
|
|
|
|
/* The current set of watch register values for writing the
|
|
registers. */
|
|
|
|
static struct pt_watch_regs watch_mirror;
|
|
|
|
static void
|
|
mips_show_dr (const char *func, CORE_ADDR addr,
|
|
int len, enum target_hw_bp_type type)
|
|
{
|
|
int i;
|
|
|
|
puts_unfiltered (func);
|
|
if (addr || len)
|
|
printf_unfiltered (" (addr=%s, len=%d, type=%s)",
|
|
paddress (target_gdbarch (), addr), len,
|
|
type == hw_write ? "data-write"
|
|
: (type == hw_read ? "data-read"
|
|
: (type == hw_access ? "data-read/write"
|
|
: (type == hw_execute ? "instruction-execute"
|
|
: "??unknown??"))));
|
|
puts_unfiltered (":\n");
|
|
|
|
for (i = 0; i < MAX_DEBUG_REGISTER; i++)
|
|
printf_unfiltered ("\tDR%d: lo=%s, hi=%s\n", i,
|
|
paddress (target_gdbarch (),
|
|
mips_linux_watch_get_watchlo (&watch_mirror,
|
|
i)),
|
|
paddress (target_gdbarch (),
|
|
mips_linux_watch_get_watchhi (&watch_mirror,
|
|
i)));
|
|
}
|
|
|
|
/* Target to_can_use_hw_breakpoint implementation. Return 1 if we can
|
|
handle the specified watch type. */
|
|
|
|
int
|
|
mips_linux_nat_target::can_use_hw_breakpoint (enum bptype type,
|
|
int cnt, int ot)
|
|
{
|
|
int i;
|
|
uint32_t wanted_mask, irw_mask;
|
|
|
|
if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid),
|
|
&watch_readback,
|
|
&watch_readback_valid, 0))
|
|
return 0;
|
|
|
|
switch (type)
|
|
{
|
|
case bp_hardware_watchpoint:
|
|
wanted_mask = W_MASK;
|
|
break;
|
|
case bp_read_watchpoint:
|
|
wanted_mask = R_MASK;
|
|
break;
|
|
case bp_access_watchpoint:
|
|
wanted_mask = R_MASK | W_MASK;
|
|
break;
|
|
default:
|
|
return 0;
|
|
}
|
|
|
|
for (i = 0;
|
|
i < mips_linux_watch_get_num_valid (&watch_readback) && cnt;
|
|
i++)
|
|
{
|
|
irw_mask = mips_linux_watch_get_irw_mask (&watch_readback, i);
|
|
if ((irw_mask & wanted_mask) == wanted_mask)
|
|
cnt--;
|
|
}
|
|
return (cnt == 0) ? 1 : 0;
|
|
}
|
|
|
|
/* Target to_stopped_by_watchpoint implementation. Return 1 if
|
|
stopped by watchpoint. The watchhi R and W bits indicate the watch
|
|
register triggered. */
|
|
|
|
bool
|
|
mips_linux_nat_target::stopped_by_watchpoint ()
|
|
{
|
|
int n;
|
|
int num_valid;
|
|
|
|
if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid),
|
|
&watch_readback,
|
|
&watch_readback_valid, 1))
|
|
return false;
|
|
|
|
num_valid = mips_linux_watch_get_num_valid (&watch_readback);
|
|
|
|
for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++)
|
|
if (mips_linux_watch_get_watchhi (&watch_readback, n) & (R_MASK | W_MASK))
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
/* Target to_stopped_data_address implementation. Set the address
|
|
where the watch triggered (if known). Return 1 if the address was
|
|
known. */
|
|
|
|
bool
|
|
mips_linux_nat_target::stopped_data_address (CORE_ADDR *paddr)
|
|
{
|
|
/* On mips we don't know the low order 3 bits of the data address,
|
|
so we must return false. */
|
|
return false;
|
|
}
|
|
|
|
/* Target to_region_ok_for_hw_watchpoint implementation. Return 1 if
|
|
the specified region can be covered by the watch registers. */
|
|
|
|
int
|
|
mips_linux_nat_target::region_ok_for_hw_watchpoint (CORE_ADDR addr, int len)
|
|
{
|
|
struct pt_watch_regs dummy_regs;
|
|
int i;
|
|
|
|
if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid),
|
|
&watch_readback,
|
|
&watch_readback_valid, 0))
|
|
return 0;
|
|
|
|
dummy_regs = watch_readback;
|
|
/* Clear them out. */
|
|
for (i = 0; i < mips_linux_watch_get_num_valid (&dummy_regs); i++)
|
|
mips_linux_watch_set_watchlo (&dummy_regs, i, 0);
|
|
return mips_linux_watch_try_one_watch (&dummy_regs, addr, len, 0);
|
|
}
|
|
|
|
/* Write the mirrored watch register values for each thread. */
|
|
|
|
static int
|
|
write_watchpoint_regs (void)
|
|
{
|
|
struct lwp_info *lp;
|
|
int tid;
|
|
|
|
ALL_LWPS (lp)
|
|
{
|
|
tid = ptid_get_lwp (lp->ptid);
|
|
if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror, NULL) == -1)
|
|
perror_with_name (_("Couldn't write debug register"));
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/* linux_nat_target::low_new_thread implementation. Write the
|
|
mirrored watch register values for the new thread. */
|
|
|
|
void
|
|
mips_linux_nat_target::low_new_thread (struct lwp_info *lp)
|
|
{
|
|
long tid = lp->ptid.lwp ();
|
|
|
|
if (!mips_linux_read_watch_registers (tid,
|
|
&watch_readback,
|
|
&watch_readback_valid, 0))
|
|
return;
|
|
|
|
if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror, NULL) == -1)
|
|
perror_with_name (_("Couldn't write debug register"));
|
|
}
|
|
|
|
/* Target to_insert_watchpoint implementation. Try to insert a new
|
|
watch. Return zero on success. */
|
|
|
|
int
|
|
mips_linux_nat_target::insert_watchpoint (CORE_ADDR addr, int len,
|
|
enum target_hw_bp_type type,
|
|
struct expression *cond)
|
|
{
|
|
struct pt_watch_regs regs;
|
|
struct mips_watchpoint *new_watch;
|
|
struct mips_watchpoint **pw;
|
|
|
|
int i;
|
|
int retval;
|
|
|
|
if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid),
|
|
&watch_readback,
|
|
&watch_readback_valid, 0))
|
|
return -1;
|
|
|
|
if (len <= 0)
|
|
return -1;
|
|
|
|
regs = watch_readback;
|
|
/* Add the current watches. */
|
|
mips_linux_watch_populate_regs (current_watches, ®s);
|
|
|
|
/* Now try to add the new watch. */
|
|
if (!mips_linux_watch_try_one_watch (®s, addr, len,
|
|
mips_linux_watch_type_to_irw (type)))
|
|
return -1;
|
|
|
|
/* It fit. Stick it on the end of the list. */
|
|
new_watch = XNEW (struct mips_watchpoint);
|
|
new_watch->addr = addr;
|
|
new_watch->len = len;
|
|
new_watch->type = type;
|
|
new_watch->next = NULL;
|
|
|
|
pw = ¤t_watches;
|
|
while (*pw != NULL)
|
|
pw = &(*pw)->next;
|
|
*pw = new_watch;
|
|
|
|
watch_mirror = regs;
|
|
retval = write_watchpoint_regs ();
|
|
|
|
if (show_debug_regs)
|
|
mips_show_dr ("insert_watchpoint", addr, len, type);
|
|
|
|
return retval;
|
|
}
|
|
|
|
/* Target to_remove_watchpoint implementation. Try to remove a watch.
|
|
Return zero on success. */
|
|
|
|
int
|
|
mips_linux_nat_target::remove_watchpoint (CORE_ADDR addr, int len,
|
|
enum target_hw_bp_type type,
|
|
struct expression *cond)
|
|
{
|
|
int retval;
|
|
int deleted_one;
|
|
|
|
struct mips_watchpoint **pw;
|
|
struct mips_watchpoint *w;
|
|
|
|
/* Search for a known watch that matches. Then unlink and free
|
|
it. */
|
|
deleted_one = 0;
|
|
pw = ¤t_watches;
|
|
while ((w = *pw))
|
|
{
|
|
if (w->addr == addr && w->len == len && w->type == type)
|
|
{
|
|
*pw = w->next;
|
|
xfree (w);
|
|
deleted_one = 1;
|
|
break;
|
|
}
|
|
pw = &(w->next);
|
|
}
|
|
|
|
if (!deleted_one)
|
|
return -1; /* We don't know about it, fail doing nothing. */
|
|
|
|
/* At this point watch_readback is known to be valid because we
|
|
could not have added the watch without reading it. */
|
|
gdb_assert (watch_readback_valid == 1);
|
|
|
|
watch_mirror = watch_readback;
|
|
mips_linux_watch_populate_regs (current_watches, &watch_mirror);
|
|
|
|
retval = write_watchpoint_regs ();
|
|
|
|
if (show_debug_regs)
|
|
mips_show_dr ("remove_watchpoint", addr, len, type);
|
|
|
|
return retval;
|
|
}
|
|
|
|
/* Target to_close implementation. Free any watches and call the
|
|
super implementation. */
|
|
|
|
void
|
|
mips_linux_nat_target::close ()
|
|
{
|
|
struct mips_watchpoint *w;
|
|
struct mips_watchpoint *nw;
|
|
|
|
/* Clean out the current_watches list. */
|
|
w = current_watches;
|
|
while (w)
|
|
{
|
|
nw = w->next;
|
|
xfree (w);
|
|
w = nw;
|
|
}
|
|
current_watches = NULL;
|
|
|
|
linux_nat_trad_target::close ();
|
|
}
|
|
|
|
void
|
|
_initialize_mips_linux_nat (void)
|
|
{
|
|
add_setshow_boolean_cmd ("show-debug-regs", class_maintenance,
|
|
&show_debug_regs, _("\
|
|
Set whether to show variables that mirror the mips debug registers."), _("\
|
|
Show whether to show variables that mirror the mips debug registers."), _("\
|
|
Use \"on\" to enable, \"off\" to disable.\n\
|
|
If enabled, the debug registers values are shown when GDB inserts\n\
|
|
or removes a hardware breakpoint or watchpoint, and when the inferior\n\
|
|
triggers a breakpoint or watchpoint."),
|
|
NULL,
|
|
NULL,
|
|
&maintenance_set_cmdlist,
|
|
&maintenance_show_cmdlist);
|
|
|
|
linux_target = &the_mips_linux_nat_target;
|
|
add_inf_child_target (&the_mips_linux_nat_target);
|
|
}
|