Xiao Zeng a61beb42b0 RISC-V: Eliminate redundant instruction macro ...

include/ChangeLog:

	* opcode/riscv.h: Eliminate redundant instruction macro M_j.

Signed-off-by: Xiao Zeng <zengxiao@eswincomputing.com>

2025-01-06 11:04:40 +08:00

..

aarch64.h

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alpha.h

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arc-attrs.h

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arc-func.h

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arc.h

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arm.h

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avr.h

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bfin.h

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bpf.h

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cgen.h

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ChangeLog-0415

binutils ChangeLog rotation

2016-01-01 22:59:17 +10:30

ChangeLog-9103

Add copyright notices

2012-12-10 12:48:03 +00:00

convex.h

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cr16.h

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cris.h

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crx.h

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csky.h

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d10v.h

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d30v.h

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dlx.h

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ft32.h

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h8300.h

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hppa.h

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i386.h

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ia64.h

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kvx.h

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loongarch.h

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m68hc11.h

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m68k.h

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metag.h

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mips.h

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mmix.h

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mn10200.h

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mn10300.h

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moxie.h

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msp430-decode.h

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msp430.h

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nds32.h

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nfp.h

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np1.h

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ns32k.h

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pdp11.h

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pj.h

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pn.h

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ppc.h

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pru.h

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pyr.h

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riscv-opc.h

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riscv.h

RISC-V: Eliminate redundant instruction macro

2025-01-06 11:04:40 +08:00

rl78.h

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rx.h

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s12z.h

Enable building the s12z target on Solaris hosts where REG_Y is defined in system header files.

2020-01-02 12:04:40 +00:00

s390.h

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score-datadep.h

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score-inst.h

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sparc.h

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spu-insns.h

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spu.h

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tic4x.h

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tic6x-control-registers.h

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tic6x-insn-formats.h

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tic6x-opcode-table.h

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tic6x.h

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tic30.h

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tic54x.h

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tilegx.h

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tilepro.h

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v850.h

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vax.h

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visium.h

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wasm.h

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xgate.h

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