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9b9b1092f0
Similar to ARM/AARCH64, we add mapping symbols in the symbol table, to mark the start addresses of data and instructions. The $d means data, and the $x means instruction. Then the disassembler uses these symbols to decide whether we should dump data or instruction. Consider the mapping-04 test case, $ cat tmp.s .text .option norelax .option norvc .fill 2, 4, 0x1001 .byte 1 .word 0 .balign 8 add a0, a0, a0 .fill 5, 2, 0x2002 add a1, a1, a1 .data .word 0x1 # No need to add mapping symbols. .word 0x2 $ riscv64-unknown-elf-as tmp.s -o tmp.o $ riscv64-unknown-elf-objdump -d tmp.o Disassembly of section .text: 0000000000000000 <.text>: 0: 00001001 .word 0x00001001 # Marked $d, .fill directive. 4: 00001001 .word 0x00001001 8: 00000001 .word 0x00000001 # .byte + part of .word. c: 00 .byte 0x00 # remaining .word. d: 00 .byte 0x00 # Marked $d, odd byte of alignment. e: 0001 nop # Marked $x, nops for alignment. 10: 00a50533 add a0,a0,a0 14: 20022002 .word 0x20022002 # Marked $d, .fill directive. 18: 20022002 .word 0x20022002 1c: 2002 .short 0x2002 1e: 00b585b3 add a1,a1,a1 # Marked $x. 22: 0001 nop # Section tail alignment. 24: 00000013 nop * Use $d and $x to mark the distribution of data and instructions. Alignments of code are recognized as instructions, since we usually fill nops for them. * If the alignment have odd bytes, then we cannot just fill the nops into the spaces. We always fill an odd byte 0x00 at the start of the spaces. Therefore, add a $d mapping symbol for the odd byte, to tell disassembler that it isn't an instruction. The behavior is same as Arm and Aarch64. The elf/linux toolchain regressions all passed. Besides, I also disable the mapping symbols internally, but use the new objudmp, the regressions passed, too. Therefore, the new objudmp should dump the objects corretly, even if they don't have any mapping symbols. bfd/ pr 27916 * cpu-riscv.c (riscv_elf_is_mapping_symbols): Define mapping symbols. * cpu-riscv.h: extern riscv_elf_is_mapping_symbols. * elfnn-riscv.c (riscv_maybe_function_sym): Do not choose mapping symbols as a function name. (riscv_elf_is_target_special_symbol): Add mapping symbols. binutils/ pr 27916 * testsuite/binutils-all/readelf.s: Updated. * testsuite/binutils-all/readelf.s-64: Likewise. * testsuite/binutils-all/readelf.s-64-unused: Likewise. * testsuite/binutils-all/readelf.ss: Likewise. * testsuite/binutils-all/readelf.ss-64: Likewise. * testsuite/binutils-all/readelf.ss-64-unused: Likewise. gas/ pr 27916 * config/tc-riscv.c (make_mapping_symbol): Create a new mapping symbol. (riscv_mapping_state): Decide whether to create mapping symbol for frag_now. Only add the mapping symbols to text sections. (riscv_add_odd_padding_symbol): Add the mapping symbols for the riscv_handle_align, which have odd bytes spaces. (riscv_check_mapping_symbols): Remove any excess mapping symbols. (md_assemble): Marked as MAP_INSN. (riscv_frag_align_code): Marked as MAP_INSN. (riscv_init_frag): Add mapping symbols for frag, it usually called by frag_var. Marked as MAP_DATA for rs_align and rs_fill, and marked as MAP_INSN for rs_align_code. (s_riscv_insn): Marked as MAP_INSN. (riscv_adjust_symtab): Call riscv_check_mapping_symbols. * config/tc-riscv.h (md_cons_align): Defined to riscv_mapping_state with MAP_DATA. (TC_SEGMENT_INFO_TYPE): Record mapping state for each segment. (TC_FRAG_TYPE): Record the first and last mapping symbols for the fragments. The first mapping symbol must be placed at the start of the fragment. (TC_FRAG_INIT): Defined to riscv_init_frag. * testsuite/gas/riscv/mapping-01.s: New testcase. * testsuite/gas/riscv/mapping-01a.d: Likewise. * testsuite/gas/riscv/mapping-01b.d: Likewise. * testsuite/gas/riscv/mapping-02.s: Likewise. * testsuite/gas/riscv/mapping-02a.d: Likewise. * testsuite/gas/riscv/mapping-02b.d: Likewise. * testsuite/gas/riscv/mapping-03.s: Likewise. * testsuite/gas/riscv/mapping-03a.d: Likewise. * testsuite/gas/riscv/mapping-03b.d: Likewise. * testsuite/gas/riscv/mapping-04.s: Likewise. * testsuite/gas/riscv/mapping-04a.d: Likewise. * testsuite/gas/riscv/mapping-04b.d: Likewise. * testsuite/gas/riscv/mapping-norelax-04a.d: Likewise. * testsuite/gas/riscv/mapping-norelax-04b.d: Likewise. * testsuite/gas/riscv/no-relax-align.d: Updated. * testsuite/gas/riscv/no-relax-align-2.d: Likewise. include/ pr 27916 * opcode/riscv.h (enum riscv_seg_mstate): Added. opcodes/ pr 27916 * riscv-dis.c (last_map_symbol, last_stop_offset, last_map_state): Added to dump sections with mapping symbols. (riscv_get_map_state): Get the mapping state from the symbol. (riscv_search_mapping_symbol): Check the sorted symbol table, and then find the suitable mapping symbol. (riscv_data_length): Decide which data size we should print. (riscv_disassemble_data): Dump the data contents. (print_insn_riscv): Handle the mapping symbols. (riscv_symbol_is_valid): Marked mapping symbols as invalid.
445 lines
16 KiB
C
445 lines
16 KiB
C
/* riscv.h. RISC-V opcode list for GDB, the GNU debugger.
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Copyright (C) 2011-2021 Free Software Foundation, Inc.
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Contributed by Andrew Waterman
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This file is part of GDB, GAS, and the GNU binutils.
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GDB, GAS, and the GNU binutils are free software; you can redistribute
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them and/or modify them under the terms of the GNU General Public
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License as published by the Free Software Foundation; either version
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3, or (at your option) any later version.
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GDB, GAS, and the GNU binutils are distributed in the hope that they
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will be useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
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the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; see the file COPYING3. If not,
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see <http://www.gnu.org/licenses/>. */
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#ifndef _RISCV_H_
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#define _RISCV_H_
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#include "riscv-opc.h"
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#include <stdlib.h>
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#include <stdint.h>
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typedef uint64_t insn_t;
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static inline unsigned int riscv_insn_length (insn_t insn)
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{
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if ((insn & 0x3) != 0x3) /* RVC instructions. */
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return 2;
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if ((insn & 0x1f) != 0x1f) /* 32-bit instructions. */
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return 4;
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if ((insn & 0x3f) == 0x1f) /* 48-bit instructions. */
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return 6;
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if ((insn & 0x7f) == 0x3f) /* 64-bit instructions. */
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return 8;
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/* Longer instructions not supported at the moment. */
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return 2;
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}
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static const char * const riscv_rm[8] =
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{
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"rne", "rtz", "rdn", "rup", "rmm", 0, 0, "dyn"
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};
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static const char * const riscv_pred_succ[16] =
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{
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0, "w", "r", "rw", "o", "ow", "or", "orw",
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"i", "iw", "ir", "irw", "io", "iow", "ior", "iorw"
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};
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#define RVC_JUMP_BITS 11
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#define RVC_JUMP_REACH ((1ULL << RVC_JUMP_BITS) * RISCV_JUMP_ALIGN)
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#define RVC_BRANCH_BITS 8
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#define RVC_BRANCH_REACH ((1ULL << RVC_BRANCH_BITS) * RISCV_BRANCH_ALIGN)
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#define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1))
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#define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
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#define EXTRACT_ITYPE_IMM(x) \
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(RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12))
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#define EXTRACT_STYPE_IMM(x) \
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(RV_X(x, 7, 5) | (RV_X(x, 25, 7) << 5) | (RV_IMM_SIGN(x) << 12))
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#define EXTRACT_BTYPE_IMM(x) \
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((RV_X(x, 8, 4) << 1) | (RV_X(x, 25, 6) << 5) | (RV_X(x, 7, 1) << 11) | (RV_IMM_SIGN(x) << 12))
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#define EXTRACT_UTYPE_IMM(x) \
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((RV_X(x, 12, 20) << 12) | (RV_IMM_SIGN(x) << 32))
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#define EXTRACT_JTYPE_IMM(x) \
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((RV_X(x, 21, 10) << 1) | (RV_X(x, 20, 1) << 11) | (RV_X(x, 12, 8) << 12) | (RV_IMM_SIGN(x) << 20))
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#define EXTRACT_CITYPE_IMM(x) \
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(RV_X(x, 2, 5) | (-RV_X(x, 12, 1) << 5))
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#define EXTRACT_CITYPE_LUI_IMM(x) \
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(EXTRACT_CITYPE_IMM (x) << RISCV_IMM_BITS)
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#define EXTRACT_CITYPE_ADDI16SP_IMM(x) \
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((RV_X(x, 6, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 1) << 6) | (RV_X(x, 3, 2) << 7) | (-RV_X(x, 12, 1) << 9))
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#define EXTRACT_CITYPE_LWSP_IMM(x) \
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((RV_X(x, 4, 3) << 2) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 2) << 6))
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#define EXTRACT_CITYPE_LDSP_IMM(x) \
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((RV_X(x, 5, 2) << 3) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 3) << 6))
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#define EXTRACT_CSSTYPE_IMM(x) \
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(RV_X(x, 7, 6) << 0)
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#define EXTRACT_CSSTYPE_SWSP_IMM(x) \
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((RV_X(x, 9, 4) << 2) | (RV_X(x, 7, 2) << 6))
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#define EXTRACT_CSSTYPE_SDSP_IMM(x) \
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((RV_X(x, 10, 3) << 3) | (RV_X(x, 7, 3) << 6))
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#define EXTRACT_CIWTYPE_IMM(x) \
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(RV_X(x, 5, 8))
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#define EXTRACT_CIWTYPE_ADDI4SPN_IMM(x) \
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((RV_X(x, 6, 1) << 2) | (RV_X(x, 5, 1) << 3) | (RV_X(x, 11, 2) << 4) | (RV_X(x, 7, 4) << 6))
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#define EXTRACT_CLTYPE_IMM(x) \
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((RV_X(x, 5, 2) << 0) | (RV_X(x, 10, 3) << 2))
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#define EXTRACT_CLTYPE_LW_IMM(x) \
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((RV_X(x, 6, 1) << 2) | (RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 1) << 6))
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#define EXTRACT_CLTYPE_LD_IMM(x) \
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((RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 2) << 6))
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#define EXTRACT_CBTYPE_IMM(x) \
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((RV_X(x, 3, 2) << 1) | (RV_X(x, 10, 2) << 3) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 2) << 6) | (-RV_X(x, 12, 1) << 8))
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#define EXTRACT_CJTYPE_IMM(x) \
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((RV_X(x, 3, 3) << 1) | (RV_X(x, 11, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 9, 2) << 8) | (RV_X(x, 8, 1) << 10) | (-RV_X(x, 12, 1) << 11))
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#define ENCODE_ITYPE_IMM(x) \
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(RV_X(x, 0, 12) << 20)
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#define ENCODE_STYPE_IMM(x) \
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((RV_X(x, 0, 5) << 7) | (RV_X(x, 5, 7) << 25))
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#define ENCODE_BTYPE_IMM(x) \
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((RV_X(x, 1, 4) << 8) | (RV_X(x, 5, 6) << 25) | (RV_X(x, 11, 1) << 7) | (RV_X(x, 12, 1) << 31))
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#define ENCODE_UTYPE_IMM(x) \
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(RV_X(x, 12, 20) << 12)
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#define ENCODE_JTYPE_IMM(x) \
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((RV_X(x, 1, 10) << 21) | (RV_X(x, 11, 1) << 20) | (RV_X(x, 12, 8) << 12) | (RV_X(x, 20, 1) << 31))
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#define ENCODE_CITYPE_IMM(x) \
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((RV_X(x, 0, 5) << 2) | (RV_X(x, 5, 1) << 12))
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#define ENCODE_CITYPE_LUI_IMM(x) \
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ENCODE_CITYPE_IMM ((x) >> RISCV_IMM_BITS)
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#define ENCODE_CITYPE_ADDI16SP_IMM(x) \
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((RV_X(x, 4, 1) << 6) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 5) | (RV_X(x, 7, 2) << 3) | (RV_X(x, 9, 1) << 12))
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#define ENCODE_CITYPE_LWSP_IMM(x) \
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((RV_X(x, 2, 3) << 4) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 2) << 2))
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#define ENCODE_CITYPE_LDSP_IMM(x) \
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((RV_X(x, 3, 2) << 5) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 3) << 2))
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#define ENCODE_CSSTYPE_IMM(x) \
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(RV_X(x, 0, 6) << 7)
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#define ENCODE_CSSTYPE_SWSP_IMM(x) \
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((RV_X(x, 2, 4) << 9) | (RV_X(x, 6, 2) << 7))
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#define ENCODE_CSSTYPE_SDSP_IMM(x) \
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((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 3) << 7))
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#define ENCODE_CIWTYPE_IMM(x) \
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(RV_X(x, 0, 8) << 5)
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#define ENCODE_CIWTYPE_ADDI4SPN_IMM(x) \
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((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 1) << 5) | (RV_X(x, 4, 2) << 11) | (RV_X(x, 6, 4) << 7))
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#define ENCODE_CLTYPE_IMM(x) \
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((RV_X(x, 0, 2) << 5) | (RV_X(x, 2, 3) << 10))
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#define ENCODE_CLTYPE_LW_IMM(x) \
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((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 1) << 5))
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#define ENCODE_CLTYPE_LD_IMM(x) \
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((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 2) << 5))
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#define ENCODE_CBTYPE_IMM(x) \
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((RV_X(x, 1, 2) << 3) | (RV_X(x, 3, 2) << 10) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 2) << 5) | (RV_X(x, 8, 1) << 12))
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#define ENCODE_CJTYPE_IMM(x) \
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((RV_X(x, 1, 3) << 3) | (RV_X(x, 4, 1) << 11) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 8, 2) << 9) | (RV_X(x, 10, 1) << 8) | (RV_X(x, 11, 1) << 12))
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#define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
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#define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
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#define VALID_BTYPE_IMM(x) (EXTRACT_BTYPE_IMM(ENCODE_BTYPE_IMM(x)) == (x))
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#define VALID_UTYPE_IMM(x) (EXTRACT_UTYPE_IMM(ENCODE_UTYPE_IMM(x)) == (x))
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#define VALID_JTYPE_IMM(x) (EXTRACT_JTYPE_IMM(ENCODE_JTYPE_IMM(x)) == (x))
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#define VALID_CITYPE_IMM(x) (EXTRACT_CITYPE_IMM(ENCODE_CITYPE_IMM(x)) == (x))
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#define VALID_CITYPE_LUI_IMM(x) (ENCODE_CITYPE_LUI_IMM(x) != 0 \
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&& EXTRACT_CITYPE_LUI_IMM(ENCODE_CITYPE_LUI_IMM(x)) == (x))
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#define VALID_CITYPE_ADDI16SP_IMM(x) (ENCODE_CITYPE_ADDI16SP_IMM(x) != 0 \
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&& EXTRACT_CITYPE_ADDI16SP_IMM(ENCODE_CITYPE_ADDI16SP_IMM(x)) == (x))
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#define VALID_CITYPE_LWSP_IMM(x) (EXTRACT_CITYPE_LWSP_IMM(ENCODE_CITYPE_LWSP_IMM(x)) == (x))
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#define VALID_CITYPE_LDSP_IMM(x) (EXTRACT_CITYPE_LDSP_IMM(ENCODE_CITYPE_LDSP_IMM(x)) == (x))
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#define VALID_CSSTYPE_IMM(x) (EXTRACT_CSSTYPE_IMM(ENCODE_CSSTYPE_IMM(x)) == (x))
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#define VALID_CSSTYPE_SWSP_IMM(x) (EXTRACT_CSSTYPE_SWSP_IMM(ENCODE_CSSTYPE_SWSP_IMM(x)) == (x))
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#define VALID_CSSTYPE_SDSP_IMM(x) (EXTRACT_CSSTYPE_SDSP_IMM(ENCODE_CSSTYPE_SDSP_IMM(x)) == (x))
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#define VALID_CIWTYPE_IMM(x) (EXTRACT_CIWTYPE_IMM(ENCODE_CIWTYPE_IMM(x)) == (x))
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#define VALID_CIWTYPE_ADDI4SPN_IMM(x) (EXTRACT_CIWTYPE_ADDI4SPN_IMM(ENCODE_CIWTYPE_ADDI4SPN_IMM(x)) == (x))
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#define VALID_CLTYPE_IMM(x) (EXTRACT_CLTYPE_IMM(ENCODE_CLTYPE_IMM(x)) == (x))
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#define VALID_CLTYPE_LW_IMM(x) (EXTRACT_CLTYPE_LW_IMM(ENCODE_CLTYPE_LW_IMM(x)) == (x))
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#define VALID_CLTYPE_LD_IMM(x) (EXTRACT_CLTYPE_LD_IMM(ENCODE_CLTYPE_LD_IMM(x)) == (x))
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#define VALID_CBTYPE_IMM(x) (EXTRACT_CBTYPE_IMM(ENCODE_CBTYPE_IMM(x)) == (x))
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#define VALID_CJTYPE_IMM(x) (EXTRACT_CJTYPE_IMM(ENCODE_CJTYPE_IMM(x)) == (x))
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#define RISCV_RTYPE(insn, rd, rs1, rs2) \
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((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2))
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#define RISCV_ITYPE(insn, rd, rs1, imm) \
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((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ENCODE_ITYPE_IMM(imm))
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#define RISCV_STYPE(insn, rs1, rs2, imm) \
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((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_STYPE_IMM(imm))
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#define RISCV_BTYPE(insn, rs1, rs2, target) \
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((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_BTYPE_IMM(target))
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#define RISCV_UTYPE(insn, rd, bigimm) \
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((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UTYPE_IMM(bigimm))
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#define RISCV_JTYPE(insn, rd, target) \
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((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_JTYPE_IMM(target))
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#define RISCV_NOP RISCV_ITYPE(ADDI, 0, 0, 0)
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#define RVC_NOP MATCH_C_ADDI
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#define RISCV_CONST_HIGH_PART(VALUE) \
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(((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
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#define RISCV_CONST_LOW_PART(VALUE) ((VALUE) - RISCV_CONST_HIGH_PART (VALUE))
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#define RISCV_PCREL_HIGH_PART(VALUE, PC) RISCV_CONST_HIGH_PART((VALUE) - (PC))
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#define RISCV_PCREL_LOW_PART(VALUE, PC) RISCV_CONST_LOW_PART((VALUE) - (PC))
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#define RISCV_JUMP_BITS RISCV_BIGIMM_BITS
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#define RISCV_JUMP_ALIGN_BITS 1
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#define RISCV_JUMP_ALIGN (1 << RISCV_JUMP_ALIGN_BITS)
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#define RISCV_JUMP_REACH ((1ULL << RISCV_JUMP_BITS) * RISCV_JUMP_ALIGN)
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#define RISCV_IMM_BITS 12
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#define RISCV_BIGIMM_BITS (32 - RISCV_IMM_BITS)
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#define RISCV_IMM_REACH (1LL << RISCV_IMM_BITS)
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#define RISCV_BIGIMM_REACH (1LL << RISCV_BIGIMM_BITS)
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#define RISCV_RVC_IMM_REACH (1LL << 6)
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#define RISCV_BRANCH_BITS RISCV_IMM_BITS
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#define RISCV_BRANCH_ALIGN_BITS RISCV_JUMP_ALIGN_BITS
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#define RISCV_BRANCH_ALIGN (1 << RISCV_BRANCH_ALIGN_BITS)
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#define RISCV_BRANCH_REACH (RISCV_IMM_REACH * RISCV_BRANCH_ALIGN)
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/* RV fields. */
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#define OP_MASK_OP 0x7f
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#define OP_SH_OP 0
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#define OP_MASK_RS2 0x1f
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#define OP_SH_RS2 20
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#define OP_MASK_RS1 0x1f
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|
#define OP_SH_RS1 15
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|
#define OP_MASK_RS3 0x1fU
|
|
#define OP_SH_RS3 27
|
|
#define OP_MASK_RD 0x1f
|
|
#define OP_SH_RD 7
|
|
#define OP_MASK_SHAMT 0x3f
|
|
#define OP_SH_SHAMT 20
|
|
#define OP_MASK_SHAMTW 0x1f
|
|
#define OP_SH_SHAMTW 20
|
|
#define OP_MASK_RM 0x7
|
|
#define OP_SH_RM 12
|
|
#define OP_MASK_PRED 0xf
|
|
#define OP_SH_PRED 24
|
|
#define OP_MASK_SUCC 0xf
|
|
#define OP_SH_SUCC 20
|
|
#define OP_MASK_AQ 0x1
|
|
#define OP_SH_AQ 26
|
|
#define OP_MASK_RL 0x1
|
|
#define OP_SH_RL 25
|
|
|
|
#define OP_MASK_CSR 0xfffU
|
|
#define OP_SH_CSR 20
|
|
|
|
#define OP_MASK_FUNCT3 0x7
|
|
#define OP_SH_FUNCT3 12
|
|
#define OP_MASK_FUNCT7 0x7fU
|
|
#define OP_SH_FUNCT7 25
|
|
#define OP_MASK_FUNCT2 0x3
|
|
#define OP_SH_FUNCT2 25
|
|
|
|
/* RVC fields. */
|
|
|
|
#define OP_MASK_OP2 0x3
|
|
#define OP_SH_OP2 0
|
|
|
|
#define OP_MASK_CRS2 0x1f
|
|
#define OP_SH_CRS2 2
|
|
#define OP_MASK_CRS1S 0x7
|
|
#define OP_SH_CRS1S 7
|
|
#define OP_MASK_CRS2S 0x7
|
|
#define OP_SH_CRS2S 2
|
|
|
|
#define OP_MASK_CFUNCT6 0x3f
|
|
#define OP_SH_CFUNCT6 10
|
|
#define OP_MASK_CFUNCT4 0xf
|
|
#define OP_SH_CFUNCT4 12
|
|
#define OP_MASK_CFUNCT3 0x7
|
|
#define OP_SH_CFUNCT3 13
|
|
#define OP_MASK_CFUNCT2 0x3
|
|
#define OP_SH_CFUNCT2 5
|
|
|
|
/* ABI names for selected x-registers. */
|
|
|
|
#define X_RA 1
|
|
#define X_SP 2
|
|
#define X_GP 3
|
|
#define X_TP 4
|
|
#define X_T0 5
|
|
#define X_T1 6
|
|
#define X_T2 7
|
|
#define X_T3 28
|
|
|
|
#define NGPR 32
|
|
#define NFPR 32
|
|
|
|
/* These fake label defines are use by both the assembler, and
|
|
libopcodes. The assembler uses this when it needs to generate a fake
|
|
label, and libopcodes uses it to hide the fake labels in its output. */
|
|
#define RISCV_FAKE_LABEL_NAME ".L0 "
|
|
#define RISCV_FAKE_LABEL_CHAR ' '
|
|
|
|
/* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
|
|
VALUE << SHIFT. VALUE is evaluated exactly once. */
|
|
#define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
|
|
(STRUCT) = (((STRUCT) & ~((insn_t)(MASK) << (SHIFT))) \
|
|
| ((insn_t)((VALUE) & (MASK)) << (SHIFT)))
|
|
|
|
/* Extract bits MASK << SHIFT from STRUCT and shift them right
|
|
SHIFT places. */
|
|
#define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
|
|
(((STRUCT) >> (SHIFT)) & (MASK))
|
|
|
|
/* Extract the operand given by FIELD from integer INSN. */
|
|
#define EXTRACT_OPERAND(FIELD, INSN) \
|
|
EXTRACT_BITS ((INSN), OP_MASK_##FIELD, OP_SH_##FIELD)
|
|
|
|
/* The maximal number of subset can be required. */
|
|
#define MAX_SUBSET_NUM 4
|
|
|
|
/* All RISC-V instructions belong to at least one of these classes. */
|
|
enum riscv_insn_class
|
|
{
|
|
INSN_CLASS_NONE,
|
|
|
|
INSN_CLASS_I,
|
|
INSN_CLASS_C,
|
|
INSN_CLASS_A,
|
|
INSN_CLASS_M,
|
|
INSN_CLASS_F,
|
|
INSN_CLASS_D,
|
|
INSN_CLASS_Q,
|
|
INSN_CLASS_F_AND_C,
|
|
INSN_CLASS_D_AND_C,
|
|
INSN_CLASS_ZICSR,
|
|
INSN_CLASS_ZIFENCEI,
|
|
INSN_CLASS_ZIHINTPAUSE,
|
|
INSN_CLASS_ZBA,
|
|
INSN_CLASS_ZBB,
|
|
INSN_CLASS_ZBC,
|
|
};
|
|
|
|
/* This structure holds information for a particular instruction. */
|
|
struct riscv_opcode
|
|
{
|
|
/* The name of the instruction. */
|
|
const char *name;
|
|
|
|
/* The requirement of xlen for the instruction, 0 if no requirement. */
|
|
unsigned xlen_requirement;
|
|
|
|
/* Class to which this instruction belongs. Used to decide whether or
|
|
not this instruction is legal in the current -march context. */
|
|
enum riscv_insn_class insn_class;
|
|
|
|
/* A string describing the arguments for this instruction. */
|
|
const char *args;
|
|
|
|
/* The basic opcode for the instruction. When assembling, this
|
|
opcode is modified by the arguments to produce the actual opcode
|
|
that is used. If pinfo is INSN_MACRO, then this is 0. */
|
|
insn_t match;
|
|
|
|
/* If pinfo is not INSN_MACRO, then this is a bit mask for the
|
|
relevant portions of the opcode when disassembling. If the
|
|
actual opcode anded with the match field equals the opcode field,
|
|
then we have found the correct instruction. If pinfo is
|
|
INSN_MACRO, then this field is the macro identifier. */
|
|
insn_t mask;
|
|
|
|
/* A function to determine if a word corresponds to this instruction.
|
|
Usually, this computes ((word & mask) == match). */
|
|
int (*match_func) (const struct riscv_opcode *op, insn_t word);
|
|
|
|
/* For a macro, this is INSN_MACRO. Otherwise, it is a collection
|
|
of bits describing the instruction, notably any relevant hazard
|
|
information. */
|
|
unsigned long pinfo;
|
|
};
|
|
|
|
/* Instruction is a simple alias (e.g. "mv" for "addi"). */
|
|
#define INSN_ALIAS 0x00000001
|
|
|
|
/* These are for setting insn_info fields.
|
|
|
|
Nonbranch is the default. Noninsn is used only if there is no match.
|
|
There are no condjsr or dref2 instructions. So that leaves condbranch,
|
|
branch, jsr, and dref that we need to handle here, encoded in 3 bits. */
|
|
#define INSN_TYPE 0x0000000e
|
|
|
|
/* Instruction is an unconditional branch. */
|
|
#define INSN_BRANCH 0x00000002
|
|
/* Instruction is a conditional branch. */
|
|
#define INSN_CONDBRANCH 0x00000004
|
|
/* Instruction is a jump to subroutine. */
|
|
#define INSN_JSR 0x00000006
|
|
/* Instruction is a data reference. */
|
|
#define INSN_DREF 0x00000008
|
|
|
|
/* We have 5 data reference sizes, which we can encode in 3 bits. */
|
|
#define INSN_DATA_SIZE 0x00000070
|
|
#define INSN_DATA_SIZE_SHIFT 4
|
|
#define INSN_1_BYTE 0x00000010
|
|
#define INSN_2_BYTE 0x00000020
|
|
#define INSN_4_BYTE 0x00000030
|
|
#define INSN_8_BYTE 0x00000040
|
|
#define INSN_16_BYTE 0x00000050
|
|
|
|
/* Instruction is actually a macro. It should be ignored by the
|
|
disassembler, and requires special treatment by the assembler. */
|
|
#define INSN_MACRO 0xffffffff
|
|
|
|
/* This is a list of macro expanded instructions. */
|
|
enum
|
|
{
|
|
M_LA,
|
|
M_LLA,
|
|
M_LA_TLS_GD,
|
|
M_LA_TLS_IE,
|
|
M_LB,
|
|
M_LBU,
|
|
M_LH,
|
|
M_LHU,
|
|
M_LW,
|
|
M_LWU,
|
|
M_LD,
|
|
M_SB,
|
|
M_SH,
|
|
M_SW,
|
|
M_SD,
|
|
M_FLW,
|
|
M_FLD,
|
|
M_FLQ,
|
|
M_FSW,
|
|
M_FSD,
|
|
M_FSQ,
|
|
M_CALL,
|
|
M_J,
|
|
M_LI,
|
|
M_ZEXTH,
|
|
M_ZEXTW,
|
|
M_SEXTB,
|
|
M_SEXTH,
|
|
M_NUM_MACROS
|
|
};
|
|
|
|
/* The mapping symbol states. */
|
|
enum riscv_seg_mstate
|
|
{
|
|
MAP_NONE = 0, /* Must be zero, for seginfo in new sections. */
|
|
MAP_DATA, /* Data. */
|
|
MAP_INSN, /* Instructions. */
|
|
};
|
|
|
|
extern const char * const riscv_gpr_names_numeric[NGPR];
|
|
extern const char * const riscv_gpr_names_abi[NGPR];
|
|
extern const char * const riscv_fpr_names_numeric[NFPR];
|
|
extern const char * const riscv_fpr_names_abi[NFPR];
|
|
|
|
extern const struct riscv_opcode riscv_opcodes[];
|
|
extern const struct riscv_opcode riscv_insn_types[];
|
|
|
|
#endif /* _RISCV_H_ */
|