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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
186 lines
5.4 KiB
Plaintext
186 lines
5.4 KiB
Plaintext
# frv testcase to generate fp_exception
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# mach: fr550
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.include "testutils.inc"
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float_constants
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start
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load_float_constants
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.global align
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align:
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; clear the packing bit if the insn at 'pack:'. We can't simply use
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; '.p' because the assembler will catch the error.
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set_gr_mem pack,gr10
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and_gr_immed 0x7fffffff,gr10
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set_mem_gr gr10,pack
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set_gr_addr pack,gr10
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flush_data_cache gr10
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; Make the the source register number odd at badst. We can't simply
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; code an odd register number because the assembler will catch the
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; error.
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set_gr_mem badst,gr10
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or_gr_immed 0x02000000,gr10
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set_mem_gr gr10,badst
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set_gr_addr badst,gr10
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flush_data_cache gr10
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; Make the the dest register number odd at badld. We can't simply
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; code an odd register number because the assembler will catch the
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; error.
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set_gr_mem badld,gr10
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or_gr_immed 0x02000000,gr10
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set_mem_gr gr10,badld
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set_gr_addr badld,gr10
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flush_data_cache gr10
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and_spr_immed -4081,tbr ; clear tbr.tt
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set_gr_spr tbr,gr17
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inc_gr_immed 0x070,gr17 ; address of exception handler
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set_bctrlr_0_0 gr17
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inc_gr_immed 0x060,gr17 ; address of exception handler
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set_bctrlr_0_0 gr17
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set_spr_immed 128,lcr
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set_spr_addr ok1,lr
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set_psr_et 1
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inc_gr_immed -4,sp ; for alignment
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set_gr_immed 0,gr20 ; PC increment
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set_gr_immed 0,gr15
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set_spr_addr ok3,lr
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set_gr_immed 4,gr20 ; PC increment
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badst: stdfi fr0,@(sp,0) ; misaligned reg -- slot I0
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test_gr_immed 1,gr15
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set_spr_addr ok4,lr
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set_gr_immed 8,gr20 ; PC increment
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nop.p
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badld: lddfi @(sp,0),fr8 ; misaligned reg -- slot I1
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test_gr_immed 2,gr15
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set_spr_addr ok5,lr
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set_gr_immed 20,gr20 ; PC increment
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fnegs.p fr9,fr9
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fnegs.p fr9,fr10
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fnegs.p fr9,fr11
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pack: fnegs fr10,fr12
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fnegs fr10,fr13 ; packing violation
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test_gr_immed 3,gr15
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set_spr_addr ok1,lr
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set_gr_immed 4,gr20 ; PC increment
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bad: .word 0x83e502c4 ; fmadds fr16,fr4,fr1 (unimplemented)
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test_gr_immed 4,gr15
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and_spr_immed 0xfbffffff,fsr0 ; disable div/0 fp_exception
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set_fr_iimmed 0x7f7f,0xffff,fr0
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set_fr_iimmed 0x0000,0x0000,fr1
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fdivs fr0,fr1,fr2 ; div/0 -- no exception
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test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is never set
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test_spr_bits 0xfc00,10,0x4,fsr0 ; fsr0.aexc is still set
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test_spr_bits 0xe0000,17,0x0,fsr0 ; fsr0.ftt is clear
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set_spr_addr ok2,lr
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set_gr_immed 0,gr20 ; PC increment
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or_spr_immed 0x04000000,fsr0 ; enable div/0 fp_exception
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set_fr_iimmed 0xdead,0xbeef,fr2
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div0: fdivs fr0,fr1,fr2 ; fp_exception - div/0
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test_fr_iimmed 0xdeadbeef,fr2 ; fr2 not updated
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test_gr_immed 5,gr15
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and_spr_immed 0xfdffffff,fsr0 ; disable inexact fp_exception
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fsqrts fr32,fr2 ; inexact -- no exception
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test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is never set
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test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is set
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test_spr_bits 0xe0000,17,0x0,fsr0 ; fsr0.ftt is clear
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set_fr_fr fr2,fr3 ; sqrt 2
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set_fr_iimmed 0xdead,0xbeef,fr2
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set_spr_addr ok6,lr
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or_spr_immed 0x02000000,fsr0 ; enable inexact fp_exception
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inxt1: fsqrts fr32,fr2 ; fp_exception - inexact
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test_gr_immed 6,gr15 ; handler called
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test_fr_fr fr2,fr3 ; fr2 updated
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set_fr_iimmed 0xdead,0xbeef,fr2
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set_spr_addr ok7,lr
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inxt2: fsqrts fr32,fr2 ; fp_exception - inexact again
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test_gr_immed 7,gr15 ; handler called
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test_fr_fr fr2,fr3 ; fr2 updated
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pass
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; exception handler 1 -- illegal_instruction: bad insn
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ok1:
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test_spr_immed 1,esfr1 ; esr0 active
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test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set
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test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set
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bra ret
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; exception handler 2 - fp_exception: divide by 0
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ok2:
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test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is clear
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test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set
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test_spr_bits 0xfc00,10,0x4,fsr0 ; fsr0.aexc is still set
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test_spr_immed 4,esfr1 ; esr2 active
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test_spr_bits 0x3e,1,0xd,esr2 ; esr2.ec is set
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test_spr_bits 0x1,0,0x1,esr2 ; esr2.valid is set
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test_spr_addr div0,epcr2 ; epcr2 is set
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bra ret
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; exception handler 3 - illegal_instruction: register exception
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ok3:
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test_spr_immed 1,esfr1 ; esr0 active
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test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set
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test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set
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bra ret
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; exception handler 4 - illegal_instruction: register exception
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ok4:
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test_spr_immed 1,esfr1 ; esr0 active
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test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set
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test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set
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bra ret
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; exception handler 5 - illegal_instruction: sequence violation
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ok5:
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test_spr_immed 1,esfr1 ; esr0 active
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test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set
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test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set
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bra ret
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; exception handler 6 - fp_exception: inexact
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ok6:
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test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is clear
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test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set
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test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is still set
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test_spr_immed 4,esfr1 ; esr2 active
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test_spr_bits 0x3e,1,0xd,esr2 ; esr2.ec is set
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test_spr_bits 0x1,0,0x1,esr2 ; esr2.valid is set
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test_spr_addr inxt1,epcr2 ; epcr2 is set
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bra ret
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; exception handler 7 - fp_exception: inexact again
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ok7:
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test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is clear
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test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set
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test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is still set
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test_spr_immed 4,esfr1 ; esr2 active
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test_spr_bits 0x3e,1,0xd,esr2 ; esr2.ec is set
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test_spr_bits 0x1,0,0x1,esr2 ; esr2.valid is set
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test_spr_addr inxt2,epcr2 ; epcr2 is set
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bra ret
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ret:
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inc_gr_immed 1,gr15
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movsg pcsr,gr60
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add gr60,gr20,gr60
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movgs gr60,pcsr
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rett 0
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fail
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