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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
54 lines
1.2 KiB
Plaintext
54 lines
1.2 KiB
Plaintext
# frv testcase to generate interrupt for st $GRk,@($GRi,$GRj)
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# mach: fr500
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# sim(fr500): --memory-region 0xfeff0600,0x8000 --memory-region 0xfe800000,0x7f0010
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.include "testutils.inc"
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start
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.global dsr
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dsr:
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and_spr_immed -4081,tbr ; clear tbr.tt
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set_gr_spr tbr,gr17
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inc_gr_immed 0x140,gr17 ; address of exception handler
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set_bctrlr_0_0 gr17
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set_spr_immed 128,lcr
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set_psr_et 1
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set_spr_addr ok0,lr
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set_gr_immed 0,gr16
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set_gr_immed 0xdeadbeef,gr15
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set_gr_addr 0xfeff0600,gr17
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bad1: sti gr15,@(gr17,0) ; cause interrupt
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test_gr_immed 1,gr16
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set_gr_immed 0xbeefdead,gr15
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set_gr_addr 0xfeff7ffc,gr17
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bad2: sti gr15,@(gr17,0) ; cause interrupt
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test_gr_immed 2,gr16
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set_gr_immed 0xbeefbeef,gr15
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set_gr_addr 0xfe800000,gr17
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bad3: sti gr15,@(gr17,0) ; cause interrupt
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test_gr_immed 3,gr16
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set_gr_immed 0xdeaddead,gr15
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set_gr_addr 0xfefefffc,gr17
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bad4: sti gr15,@(gr17,0) ; cause interrupt
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test_gr_immed 4,gr16
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sti gr0,@(sp,0) ; no interrupt
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test_gr_immed 4,gr16
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pass
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ok0:
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; check interrupts
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test_spr_immed 0x4000,esfr1 ; esr14 is active
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test_spr_bits 0x0001,0,0x1,esr14 ; esr14 is valid
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test_spr_bits 0x003e,1,0x0,esr14 ; esr14.ec is set
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test_spr_bits 0x0800,11,0x0,esr14 ; esr14.eav is not set
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addi gr16,1,gr16
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rett 0
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fail
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