binutils-gdb

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Files

Nick Clifton 6ef35c04df Fix verilog output when the width is > 1.

PR 25202
bfd	* bfd.c (VerilogDataEndianness): New variable.
	(verilog_write_record): Use VerilogDataEndianness, if set, to
	choose the endianness of the output.
	(verilog_write_section): Adjust the address by the data width.

binutils* objcopy.c (copy_object): Set VerilogDataEndianness to the
	endianness of the input file.
	(copy_main): Verifiy the value set by the --verilog-data-width
	option.
	* testsuite/binutils-all/objcopy.exp: Add tests of the new behaviour.
	* testsuite/binutils-all/verilog-I4.hex: New file.

2022-12-01 13:09:26 +00:00

binutils-all

Fix verilog output when the width is > 1.

2022-12-01 13:09:26 +00:00

config

Binutils: Adding new testcase for addr2line.

2022-10-19 12:35:23 +05:30

lib

Add a linker warning when creating potentially dangerous executable segments. Add tests, options to disabke and configure switches to choose defaults.

2022-05-03 11:42:24 +01:00

ChangeLog-0411

Add copyright notices