Files
binutils-gdb/sim/testsuite/riscv/m-ext.s
Jaydeep Patil 3224e32fb8 sim: riscv: Add support for compressed integer instructions
Added support for simulation of compressed integer instruction set ("c").
Added test file sim/testsuite/riscv/c-ext.s to test compressed instructions.
The compressed instructions are available for models implementing C extension.
Such as RV32IC, RV64IC, RV32GC, RV64GC etc.

Approved-By: Andrew Burgess <aburgess@redhat.com>
2024-02-13 11:04:04 +00:00

19 lines
280 B
ArmAsm

# Check that the RV32M instructions run without any faults.
# mach: riscv32 riscv64
.include "testutils.inc"
start
.option arch, +m
mul x0, x1, x2
mulh x0, x1, x2
mulhu x0, x1, x2
mulhsu x0, x1, x2
div x0, x1, x2
divu x0, x1, x2
rem x0, x1, x2
remu x0, x1, x2
pass