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https://github.com/espressif/binutils-gdb.git
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316 lines
12 KiB
C
316 lines
12 KiB
C
#ifndef OPCODE__esp32ulp_esp32_H_
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#define OPCODE__esp32ulp_esp32_H_
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// ==================== I_ALUR ============================
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struct s_alu_reg {
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unsigned int dreg : 2; /*!< Destination register */
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unsigned int sreg : 2; /*!< Register with operand A */
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unsigned int treg : 2; /*!< Register with operand B */
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unsigned int unused : 15; /*!< Unused */
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unsigned int sel : 4; /*!< Operation to perform, one of ALU_SEL_xxx */
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unsigned int sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_ALU_REG) */
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unsigned int opcode : 4; /*!< Opcode (OPCODE_ALU) */
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}; /*!< Format of ALU instruction (both sources are registers) */
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typedef union {
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struct s_alu_reg s;
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unsigned int unsigned_int;
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} alu_reg;
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#define I_ALUR(reg_dest, reg_src1, reg_src2, op_sel) { ( alu_reg ) { .s = { \
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.dreg = reg_dest, \
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.sreg = reg_src1, \
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.treg = reg_src2, \
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.unused = 0, \
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.sel = op_sel, \
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.sub_opcode = SUB_OPCODE_ALU_REG, \
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.opcode = OPCODE_ALU } }.unsigned_int }
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// ==================== I_ALUI ============================
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struct s_alu_reg_i {
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unsigned int dreg : 2; /*!< Destination register */
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unsigned int sreg : 2; /*!< Register with operand A */
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unsigned int imm : 16; /*!< imm value */
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unsigned int unused : 1; /*!< Unused */
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unsigned int sel : 4; /*!< Operation to perform, one of ALU_SEL_xxx */
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unsigned int sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_ALU_REG) */
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unsigned int opcode : 4; /*!< Opcode (OPCODE_ALU) */
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}; /*!< Format of ALU instruction (both sources are registers) */
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typedef union {
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struct s_alu_reg_i s;
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unsigned int unsigned_int;
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} alu_reg_i;
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#define I_ALUI(reg_dest, reg_src1, imme, op_sel) { ( alu_reg_i ) { .s = { \
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.dreg = reg_dest, \
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.sreg = reg_src1, \
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.imm = imme, \
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.unused = 0, \
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.sel = op_sel, \
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.sub_opcode = SUB_OPCODE_ALU_IMM, \
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.opcode = OPCODE_ALU } }.unsigned_int }
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// ==================== I_ALUS ============================
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struct s_alu_reg_s {
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unsigned int unused1 : 4; /*!< Destination register */
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unsigned int imm : 8; /*!< imm value */
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unsigned int unused2 : 9; /*!< Unused */
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unsigned int sel : 4; /*!< Operation to perform, one of ALU_SEL_xxx */
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unsigned int sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_ALU_REG) */
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unsigned int opcode : 4; /*!< Opcode (OPCODE_ALU) */
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}; /*!< Format of ALU instruction (both sources are registers) */
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typedef union {
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struct s_alu_reg_s s;
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unsigned int unsigned_int;
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} alu_reg_s;
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#define I_ALUS(op_sel, imme) { ( alu_reg_s ) { .s = { \
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.unused1 = 0, \
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.imm = imme, \
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.unused2 = 0, \
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.sel = op_sel, \
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.sub_opcode = SUB_OPCODE_ALU_CNT, \
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.opcode = OPCODE_ALU } }.unsigned_int }
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// ------------------ Jump ------------------------
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struct s_jump_alu_ri {
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unsigned int dreg : 2; /*!< Register which contains target PC, expressed in words (used if .reg == 1) */
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unsigned int addr : 11; /*!< Target PC, expressed in words (used if .reg == 0) */
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unsigned int unused : 8; /*!< Unused */
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unsigned int reg : 1; /*!< Target PC in register (1) or immediate (0) */
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unsigned int type : 3; /*!< Jump condition (BX_JUMP_TYPE_xxx) */
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unsigned int sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_BX) */
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unsigned int opcode : 4; /*!< Opcode (OPCODE_BRANCH) */
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}; /*!< Format of ALU instruction (both sources are registers) */
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typedef union {
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struct s_jump_alu_ri s;
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unsigned int unsigned_int;
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} jump_alu_ri;
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#define OPCODE_BRANCH 8 /*!< Branch instructions */
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#define SUB_OPCODE_BX 0 /*!< Branch to absolute PC (immediate or in register) */
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#define SUB_OPCODE_BR 1 /*!< Branch to relative PC */
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#define SUB_OPCODE_BS 2 /*!< Branch to relative PC */
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#define I_JUMP_RI(reg_pc, imm_pc, cond, mode) { ( jump_alu_ri ) { .s = { \
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.dreg = reg_pc, \
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.addr = imm_pc, \
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.unused = 0, \
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.reg = mode,\
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.type = cond,\
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.sub_opcode = SUB_OPCODE_BX, \
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.opcode = OPCODE_BRANCH } }.unsigned_int }
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// ------------------ Jump relr ------------------------
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struct s_jump_alu_relr {
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unsigned int threshold : 16;
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unsigned int judge : 1;
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unsigned int step: 8;
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unsigned int sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_BX) */
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unsigned int opcode : 4; /*!< Opcode (OPCODE_BRANCH) */
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}; /*!< Format of ALU instruction */
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typedef union {
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struct s_jump_alu_relr s;
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unsigned int unsigned_int;
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} jump_alu_relr;
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#define I_JUMP_RELR(thresh, jud, stp) { ( jump_alu_relr ) { .s = { \
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.threshold = thresh, \
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.judge = jud, \
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.step = ((stp < 0) ? ((-stp) | (1 << 7)) : stp) , \
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.sub_opcode = SUB_OPCODE_BR, \
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.opcode = OPCODE_BRANCH } }.unsigned_int }
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// ------------------ Jump rels ------------------------
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struct s_jump_alu_rels {
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unsigned int threshold : 8;
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unsigned int unused : 7;
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unsigned int judge : 2;
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unsigned int step : 8;
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unsigned int sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_BX) */
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unsigned int opcode : 4; /*!< Opcode (OPCODE_BRANCH) */
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}; /*!< Format of ALU instruction */
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typedef union {
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struct s_jump_alu_rels s;
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unsigned int unsigned_int;
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} jump_alu_rels;
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#define I_JUMP_RELS(thresh, jud, stp) { ( jump_alu_rels ) { .s = { \
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.threshold = thresh, \
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.judge = jud, \
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.step = ((stp < 0) ? ((-stp) | (1 << 7)) : stp) , \
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.sub_opcode = SUB_OPCODE_BS, \
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.opcode = OPCODE_BRANCH } }.unsigned_int }
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// ------------------ wr_mem ------------------------
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#define OPCODE_ST 6 /*!< Instruction: store indirect to RTC memory */
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#define SUB_OPCODE_ST 4 /*!< Store 32 bits, 16 MSBs contain PC, 16 LSBs contain value from source register */
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struct s_wr_mem {
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unsigned int dreg : 2;
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unsigned int sreg : 2;
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unsigned int unused1 : 6;
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unsigned int offset : 11;
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unsigned int unused2 : 4;
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unsigned int sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_BX) */
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unsigned int opcode : 4; /*!< Opcode (OPCODE_BRANCH) */
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}; /*!< Format of ALU instruction */
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typedef union {
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struct s_wr_mem s;
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unsigned int unsigned_int;
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} wr_mem;
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#define WR_MEM(dest, src, offs) { ( wr_mem ) { .s = { \
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.dreg = dest, \
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.sreg = src, \
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.unused1 = 0, \
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.offset = offs, \
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.unused2 = 0, \
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.sub_opcode = SUB_OPCODE_ST, \
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.opcode = OPCODE_ST } }.unsigned_int }
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// ------------------ rd_mem ------------------------
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#define OPCODE_LD 13 /*!< Instruction: store indirect to RTC memory */
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#define SUB_OPCODE_LD 0 /*!< Store 32 bits, 16 MSBs contain PC, 16 LSBs contain value from source register */
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struct s_rd_mem {
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unsigned int dreg : 2;
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unsigned int sreg : 2;
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unsigned int unused1 : 6;
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unsigned int offset : 11;
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unsigned int unused2 : 4;
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unsigned int sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_BX) */
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unsigned int opcode : 4; /*!< Opcode (OPCODE_BRANCH) */
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}; /*!< Format of ALU instruction */
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typedef union {
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struct s_rd_mem s;
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unsigned int unsigned_int;
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} rd_mem;
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#define RD_MEM(dest, src, offs) { ( rd_mem ) { .s = { \
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.dreg = dest, \
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.sreg = src, \
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.unused1 = 0, \
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.offset = offs, \
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.unused2 = 0, \
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.sub_opcode = SUB_OPCODE_LD, \
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.opcode = OPCODE_LD } }.unsigned_int }
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// ------------------ SLEEP ------------------------
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#define SUB_OPCODE_SLEEP 1 /*!< Stop executing the program and run it again after selected interval */
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struct s_cmd_sleep {
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unsigned int cycle_sel : 4; /*!< Select which one of SARADC_ULP_CP_SLEEP_CYCx_REG to get the sleep duration from */
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unsigned int unused : 21; /*!< Unused */
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unsigned int sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_SLEEP) */
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unsigned int opcode : 4; /*!< Opcode (OPCODE_END) */
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}; /*!< Format of END instruction with wakeup */
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typedef union {
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struct s_cmd_sleep s;
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unsigned int unsigned_int;
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} cmd_sleep;
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#define OP_CMD_SLEEP(sleep) { ( cmd_sleep ) { .s = { \
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.cycle_sel = sleep, \
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.unused = 0,\
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.sub_opcode = SUB_OPCODE_SLEEP,\
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.opcode = OPCODE_EXIT } }.unsigned_int }
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// ------------------ RD/WR reg ------------------------
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#define OPCODE_WR_REG 1 /*!< Instruction: write peripheral register (RTC_CNTL/RTC_IO/SARADC) (not implemented yet) */
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#define OPCODE_RD_REG 2 /*!< Instruction: read peripheral register (RTC_CNTL/RTC_IO/SARADC) (not implemented yet) */
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struct s_cmd_wr_reg {
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unsigned int addr : 10; /*!< Address within either RTC_CNTL, RTC_IO, or SARADC */
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unsigned int data : 8; /*!< 8 bits of data to write */
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unsigned int low : 5; /*!< Low bit */
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unsigned int high : 5; /*!< High bit */
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unsigned int opcode : 4; /*!< Opcode (OPCODE_WR_REG) */
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}; /*!< Format of WR_REG instruction */
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typedef union {
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struct s_cmd_wr_reg s;
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unsigned int unsigned_int;
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} cmd_wr_reg;
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struct s_cmd_rd_reg {
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unsigned int addr : 10; /*!< Address within either RTC_CNTL, RTC_IO, or SARADC */
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unsigned int unused : 8; /*!< Unused */
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unsigned int low : 5; /*!< Low bit */
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unsigned int high : 5; /*!< High bit */
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unsigned int opcode : 4; /*!< Opcode (OPCODE_WR_REG) */
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}; /*!< Format of RD_REG instruction */
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typedef union {
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struct s_cmd_rd_reg s;
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unsigned int unsigned_int;
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} cmd_rd_reg;
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/**
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* Write literal value to a peripheral register
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*
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* reg[high_bit : low_bit] = val
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* This instruction can access RTC_CNTL_, RTC_IO_, and SENS_ peripheral registers.
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*/
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#define I_WR_REG(reg_addr, low_bit, high_bit, val) { ( cmd_wr_reg ) { .s = { \
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.addr = reg_addr, \
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.data = val, \
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.low = low_bit, \
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.high = high_bit, \
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.opcode = OPCODE_WR_REG } }.unsigned_int }
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/**
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* Read from peripheral register into R0
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*
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* R0 = reg[high_bit : low_bit]
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* This instruction can access RTC_CNTL_, RTC_IO_, and SENS_ peripheral registers.
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*/
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#define I_RD_REG(reg_addr, low_bit, high_bit) { ( cmd_rd_reg ) { .s = { \
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.addr = reg_addr, \
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.unused = 0, \
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.low = low_bit, \
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.high = high_bit, \
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.opcode = OPCODE_RD_REG } }.unsigned_int }
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// ------------------ RD/WR reg ------------------------
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#define OPCODE_I2C 3 /*!< Instruction: read/write I2C (not implemented yet) */
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#define OPCODE_I2C_RD 0
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#define OPCODE_I2C_WR 1
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struct s_cmd_i2c {
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unsigned int i2c_addr : 8; /*!< I2C slave address */
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unsigned int data : 8; /*!< Data to read or write */
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unsigned int low_bits : 3; /*!< TBD */
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unsigned int high_bits : 3; /*!< TBD */
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unsigned int i2c_sel : 4; /*!< TBD, select reg_i2c_slave_address[7:0] */
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unsigned int unused : 1; /*!< Unused */
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unsigned int rw_bit : 1; /*!< Write (1) or read (0) */
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unsigned int opcode : 4; /*!< Opcode (OPCODE_I2C) */
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}; /*!< Format of I2C instruction */
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typedef union {
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struct s_cmd_i2c s;
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unsigned int unsigned_int;
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} cmd_i2c;
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#define I_I2C_RW(addr, val, low, high, sel, rw) { ( cmd_i2c ) { .s = { \
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.i2c_addr = addr, \
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.data = val, \
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.low_bits = low, \
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.high_bits = high, \
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.i2c_sel = sel, \
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.unused = 0, \
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.rw_bit = rw, \
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.opcode = OPCODE_I2C } }.unsigned_int }
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// --------------------------------------------------------------------------
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#endif // OPCODE__esp32ulp_esp32_H_
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