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148 lines
5.8 KiB
C
Executable File
148 lines
5.8 KiB
C
Executable File
/* esp32ulp.h -- Header file for ESP32ULP opcode table
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Copyright (c) 2016-2017 Espressif Systems (Shanghai) PTE LTD.
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This file is part of GDB, GAS, and the GNU binutils.
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GDB, GAS, and the GNU binutils are free software; you can redistribute
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them and/or modify them under the terms of the GNU General Public
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License as published by the Free Software Foundation; either version 3,
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or (at your option) any later version.
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GDB, GAS, and the GNU binutils are distributed in the hope that they
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will be useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
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the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING3. If not, write to the Free
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Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#ifndef OPCODE_ESP32ULP_H
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#define OPCODE_ESP32ULP_H
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// ==================== I_ALUR ============================
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#define OPCODE_ALU 7 /*!< Arithmetic instructions */
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#define SUB_OPCODE_ALU_REG 0 /*!< Arithmetic instruction, both source values are in register */
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#define SUB_OPCODE_ALU_IMM 1 /*!< Arithmetic instruction, one source value is an immediate */
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#define SUB_OPCODE_ALU_CNT 2 /*!< Arithmetic instruction between counter register and an immediate (not implemented yet)*/
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#define ALU_SEL_ADD 0 /*!< Addition */
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#define ALU_SEL_SUB 1 /*!< Subtraction */
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#define ALU_SEL_AND 2 /*!< Logical AND */
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#define ALU_SEL_OR 3 /*!< Logical OR */
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#define ALU_SEL_MOV 4 /*!< Copy value (immediate to destination register or source register to destination register */
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#define ALU_SEL_LSH 5 /*!< Shift left by given number of bits */
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#define ALU_SEL_RSH 6 /*!< Shift right by given number of bits */
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#define ALU_SEL_SINC 0
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#define ALU_SEL_SDEC 1
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#define ALU_SEL_SRST 2
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// ------------------ halt ------------------------
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#define OPCODE_HALT 11 /*!< Instruction: store indirect to RTC memory */
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struct s_cmd_halt {
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unsigned int unused : 28;
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unsigned int opcode : 4; /*!< Opcode (OPCODE_BRANCH) */
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}; /*!< Format of ALU instruction */
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typedef union {
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struct s_cmd_halt s;
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unsigned int unsigned_int;
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} cmd_halt;
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#define OP_CMD_HALT() { ( cmd_halt ) { .s = { \
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.unused = 0, \
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.opcode = OPCODE_HALT } }.unsigned_int }
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// ------------------ WAKEUP ------------------------
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#define OPCODE_EXIT 9 /*!< Stop executing the program (not implemented yet) */
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#define SUB_OPCODE_WAKEUP 0 /*!< Stop executing the program and optionally wake up the chip */
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struct s_cmd_wakeup {
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unsigned int wakeup : 1; /*!< Set to 1 to wake up chip */
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unsigned int unused : 24; /*!< Unused */
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unsigned int sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_WAKEUP) */
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unsigned int opcode : 4; /*!< Opcode (OPCODE_END) */
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}; /*!< Format of END instruction with wakeup */
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typedef union {
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struct s_cmd_wakeup s;
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unsigned int unsigned_int;
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} cmd_wakeup;
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#define OP_CMD_WAKEUP(wake) { ( cmd_wakeup ) { .s = { \
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.wakeup = wake, \
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.unused = 0, \
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.sub_opcode = SUB_OPCODE_WAKEUP, \
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.opcode = OPCODE_EXIT } }.unsigned_int }
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// ------------------ WAIT ------------------------
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#define OPCODE_WAIT 4 /*!< Instruction: delay (nop) for a given number of cycles */
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struct s_cmd_wait {
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unsigned int wait : 16; /*!< Set to 1 to wake up chip */
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unsigned int unused : 12; /*!< Unused */
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unsigned int opcode : 4; /*!< Opcode (OPCODE_WAIT) */
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}; /*!< Format of END instruction with wakeup */
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typedef union {
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struct s_cmd_wait s;
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unsigned int unsigned_int;
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} cmd_wait;
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#define OP_CMD_WAIT(cyc) { ( cmd_wait ) { .s = { \
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.wait = cyc, \
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.unused = 0, \
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.opcode = OPCODE_WAIT } }.unsigned_int }
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// ------------------ TSENS ------------------------
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#define OPCODE_TSENS 10 /*!< Instruction: temperature sensor measurement (not implemented yet) */
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struct s_cmd_tsens {
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unsigned int dreg : 2; /*!< Register where to store temperature measurement result */
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unsigned int wait_delay : 14; /*!< Cycles to wait after measurement is done */
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unsigned int cycles : 12; /*!< Cycles used to perform measurement */
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unsigned int opcode : 4; /*!< Opcode (OPCODE_TSENS) */
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}; /*!< Format of TSENS instruction */
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typedef union {
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struct s_cmd_tsens s;
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unsigned int unsigned_int;
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} cmd_tsens;
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#define OP_CMD_TSENS(dreg, delay) { ( cmd_tsens ) { .s = { \
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.dreg = dreg, \
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.wait_delay = delay, \
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.cycles = 0, \
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.opcode = OPCODE_TSENS } }.unsigned_int }
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// ------------------ MEAS ------------------------
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#define OPCODE_ADC 5 /*!< Instruction: SAR ADC measurement (not implemented yet) */
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struct s_cmd_adc {
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unsigned int dreg : 2; /*!< Register where to store ADC result */
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unsigned int sar_mux : 4; /*!< Select SARADC pad (mux + 1) */
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unsigned int sar_sel : 1; /*!< Select SARADC0 (0) or SARADC1 (1) */
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unsigned int unused1 : 1; /*!< Unused */
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unsigned int cycles : 16; /*!< TBD, cycles used for measurement */
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unsigned int unused2 : 4; /*!< Unused */
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unsigned int opcode : 4; /*!< Opcode (OPCODE_ADC) */
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};
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typedef union {
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struct s_cmd_adc s;
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unsigned int unsigned_int;
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} cmd_adc;
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#define OP_CMD_ADC(d_reg, mux, sel) { ( cmd_adc ) { .s = { \
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.dreg = d_reg, \
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.sar_mux = mux, \
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.sar_sel = sel, \
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.unused1 = 0, \
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.cycles = 0, \
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.unused2 = 0, \
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.opcode = OPCODE_ADC } }.unsigned_int }
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#endif
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