mirror of
https://github.com/espressif/binutils-gdb.git
synced 2025-08-23 22:09:19 +08:00
fa8b7c2128
This adds the OpenRISC 32-bit sim target. The OpenRISC sim is a CGEN based sim so the bulk of the code is generated from the .cpu files by CGEN. The engine decode and execute logic in mloop uses scache with pseudo-basic-block extraction and supports both full and fast (switch) modes. The sim does not implement an mmu at the moment. The sim does implement fpu instructions via the common sim-fpu implementation. sim/ChangeLog: 2017-12-12 Stafford Horne <shorne@gmail.com> Peter Gavin <pgavin@gmail.com> * configure.tgt: Add or1k sim. * or1k/README: New file. * or1k/Makefile.in: New file. * or1k/configure.ac: New file. * or1k/mloop.in: New file. * or1k/or1k-sim.h: New file. * or1k/or1k.c: New file. * or1k/sim-if.c: New file. * or1k/sim-main.h: New file. * or1k/traps.c: New file.
18 lines
419 B
Plaintext
18 lines
419 B
Plaintext
dnl Process this file with autoconf to produce a configure script.
|
|
AC_PREREQ(2.64)dnl
|
|
AC_INIT(Makefile.in)
|
|
sinclude(../common/acinclude.m4)
|
|
|
|
SIM_AC_COMMON
|
|
|
|
SIM_AC_OPTION_ENDIAN(BIG)
|
|
SIM_AC_OPTION_ALIGNMENT(STRICT_ALIGNMENT)
|
|
SIM_AC_OPTION_BITSIZE([32], [31], [32])
|
|
SIM_AC_OPTION_SCACHE(16384)
|
|
SIM_AC_OPTION_DEFAULT_MODEL([or1200])
|
|
SIM_AC_OPTION_ENVIRONMENT
|
|
SIM_AC_OPTION_INLINE()
|
|
SIM_AC_OPTION_CGEN_MAINT
|
|
|
|
SIM_AC_OUTPUT
|