Commit Graph

18802 Commits

Author SHA1 Message Date
GDB Administrator
11788869e0 Automatic date update in version.in 2023-11-20 00:00:08 +00:00
GDB Administrator
1e62d51f29 Automatic date update in version.in 2023-11-19 00:00:11 +00:00
GDB Administrator
26c7a0ea38 Automatic date update in version.in 2023-11-18 00:00:08 +00:00
Joseph Myers
5070b0e66c Fix read_ranges for 32-bit long
bfd/dwarf2.c:read_ranges compares bfd_vma values against -1UL, which
doesn't work correctly when long is 32-bit and bfd_vma is 64-bit
(observed as "nm -l" being very slow for mingw64 host; probably causes
issues on 32-bit hosts as well as IL32LLP64 cases such as mingw64).
Fix by using (bfd_vma) -1 in place of -1UL, as done elsewhere.
2023-11-17 17:04:14 +00:00
mengqinggang
8338aecd23 LoongArch: Modify link_info.relax_pass from 3 to 2
The first pass handles R_LARCH_RELAX relocations, the second pass
handles R_LARCH_ALIGN relocations.
2023-11-17 16:38:55 +08:00
mengqinggang
4f2469d0cd LoongArch: Remove "elf_seg_map (info->output_bfd) == NULL" relaxation condition
Previously the condition prevented shared objects from being relaxed.
To remove the limitation, we need to update program header size and
.eh_frame_hdr size before relaxation.
2023-11-17 16:38:55 +08:00
mengqinggang
b130a0849a LoongArch: Multiple relax_trip in one relax_pass
If deleting instructions in one relax_trip, set again to true to start the
next relax_trip.
2023-11-17 16:38:54 +08:00
mengqinggang
4e94082d95 LoongArch: Directly delete relaxed instuctions in first relaxation pass
Directly delete relaxed instuctions in first relaxation pass, not use
R_LARCH_DELETE relocation. If not, the PC-relative offset may increase.
2023-11-17 16:38:53 +08:00
mengqinggang
363174776d LoongArch: Fix ld --no-relax bug
When calling ld with --no-relax, pcalau12i + ld.d still can be relaxed.
This patch fix this bug and pcalau12i + ld.d can be relaxed with --relax.
2023-11-17 16:38:53 +08:00
GDB Administrator
0da4f405f8 Automatic date update in version.in 2023-11-17 00:00:08 +00:00
GDB Administrator
5391e967b0 Automatic date update in version.in 2023-11-16 00:00:10 +00:00
Arsen Arsenovi?
862776f26a Finalized intl-update patches
* intl: Remove directory.  Replaced with out-of-tree GNU gettext.
  * .gitignore: Add '/gettext*'.
  * configure.ac (host_libs): Replace intl with gettext. (hbaseargs, bbaseargs, baseargs): Split baseargs into {h,b}baseargs. (skip_barg): New flag.  Skips appending current flag to bbaseargs. <library exemptions>: Exempt --with-libintl-{type,prefix} from target and build machine argument passing.
  * configure: Regenerate.
  * Makefile.def (host_modules): Replace intl module with gettext module. (configure-ld): Depend on configure-gettext.
  * Makefile.in: Regenerate.
  * src-release.sh: Remove references to the intl/ directory.
2023-11-15 12:53:04 +00:00
GDB Administrator
80f90d95e3 Automatic date update in version.in 2023-11-15 00:00:09 +00:00
GDB Administrator
319b460545 Automatic date update in version.in 2023-11-14 00:00:12 +00:00
GDB Administrator
df3926bb63 Automatic date update in version.in 2023-11-13 00:00:07 +00:00
GDB Administrator
328e015954 Automatic date update in version.in 2023-11-12 00:00:12 +00:00
GDB Administrator
943e09db60 Automatic date update in version.in 2023-11-11 00:00:08 +00:00
Simon Marchi
a7a0cb6c92 bfd, binutils: add gfx11 amdgpu architectures
Teach bfd and readelf about some recent gfx11 architectures.  This code
is taken from the rocgdb 5.7.x branch [1].

[1] https://github.com/rocm-Developer-Tools/rocgdb/tree/rocm-5.7.x

bfd/ChangeLog:

	* archures.c (bfd_mach_amdgcn_gfx1100, bfd_mach_amdgcn_gfx1101,
	bfd_mach_amdgcn_gfx1102): New.
	* bfd-in2.h (bfd_mach_amdgcn_gfx1100, bfd_mach_amdgcn_gfx1101,
	bfd_mach_amdgcn_gfx1102): New.
	* cpu-amdgcn.c (arch_info_struct): Add entries for
	bfd_mach_amdgcn_gfx1100, bfd_mach_amdgcn_gfx1101,
	bfd_mach_amdgcn_gfx1102.

binutils/ChangeLog:

	* readelf.c (decode_AMDGPU_machine_flags): Handle gfx1100,
	gfx1101, gfx1102.

include/ChangeLog:

	* elf/amdgpu.h (EF_AMDGPU_MACH_AMDGCN_GFX1100,
	EF_AMDGPU_MACH_AMDGCN_GFX1101,
	EF_AMDGPU_MACH_AMDGCN_GFX1102): New.

Change-Id: I95a8a62942e359781a1c9fa2079950fbcf2a78b8
Co-Authored-By: Laurent Morichetti <laurent.morichetti@amd.com>
Cc: Lancelot Six <lancelot.six@amd.com>
2023-11-10 13:20:22 -05:00
Michael J. Eager
364081efa5 Correct formatting errors in elf32-microblaze.c
Signed-off-by: Michael J. Eager <eager@eagercon.com>
2023-11-10 08:29:53 -08:00
Ying Huang
d173146d9b MIPS: Change all E_MIPS_* to EF_MIPS_* 2023-11-10 14:03:17 +00:00
Nick Clifton
e922d1eaa3 Add ability to change linker warning messages into errors when reporting executable stacks and/or executable segments.
include
  * bfdlink.h (struct bfd_link_info): Update descriptions of the 'execstack', 'noexecstack' and 'warn_execstack' fields. Add 'error_exectack' and 'warn_is_error_for_rwx_segments' fields.

  bfd
  * elf.c (assign_file_positions_except_relocs): Turn warnings about executable segments into errors if so requested.
  * elflink.c (bfd_elf_size_dynamic_sections): Turn warnings about executable stacks into errors if so requested.

  ld
  * ldlex.h (enum option_values): Add OPTION_ERROR_EXECSTACK, OPTION_NO_ERROR_EXECSTACK, OPTION_WARN_EXECSTACK_OBJECTS, OPTION_ERROR_RWX_SEGMENTS and OPTION_NO_ERROR_RWX_SEGMENTS. (struct ld_option): Add new long options. (parse_args): Parse new long options. (elf_static_list_options): Display the new options.
  * ld.texi: Document the new command line options.
  * configure.ac (error-execstack): New configuration option. (error-rwx-segments): New configuration option.
  * emultempl/elf.em (_before_parse): Initialse the new linkinfo fields.
  * NEWS: Mention the new features.
  * config.in: Regenerate.
  * configure: Regenerate.
  * testsuite/ld-elf/commonpage2.d: Disable errors for RWX segments and/or executable stacks.
  * testsuite/ld-elf/elf.exp: Likewise.
  * testsuite/ld-elf/header.d: Likewise.
  * testsuite/ld-elf/loadaddr1.d: Likewise.
  * testsuite/ld-elf/loadaddr2.d: Likewise.
  * testsuite/ld-elf/maxpage4.d: Likewise.
  * testsuite/ld-elf/nobits-1.d: Likewise.
  * testsuite/ld-elf/note-1.d: Likewise.
  * testsuite/ld-elf/orphan-10.d: Likewise.
  * testsuite/ld-elf/orphan-11.d: Likewise.
  * testsuite/ld-elf/orphan-12.d: Likewise.
  * testsuite/ld-elf/orphan-5.d: Likewise.
  * testsuite/ld-elf/orphan-7.d: Likewise.
  * testsuite/ld-elf/orphan-8.d: Likewise.
  * testsuite/ld-elf/orphan-9.d: Likewise.
  * testsuite/ld-elf/orphan-region.d: Likewise.
  * testsuite/ld-elf/orphan.d: Likewise.
  * testsuite/ld-elf/pr19539.d: Likewise.
  * testsuite/ld-elf/pr26256-1a.d: Likewise.
  * testsuite/ld-elf/pr26907.d: Likewise.
  * testsuite/ld-elf/pr28597.d: Likewise.
  * testsuite/ld-elf/retain2.d: Likewise.
  * testsuite/ld-elf/shared.exp: Likewise.
  * testsuite/ld-elf/size-1.d: Likewise.
  * testsuite/ld-elf/textaddr7.d: Likewise.
  * testsuite/ld-elf/warn1.d: Likewise.
  * testsuite/ld-elf/warn2.d: Likewise.
  * testsuite/ld-i386/discarded1.d: Likewise.
  * testsuite/ld-i386/pr19175.d: Likewise.
  * testsuite/ld-i386/pr19539.d: Likewise.
  * testsuite/ld-i386/pr23189.d: Likewise.
  * testsuite/ld-plugin/lto-3r.d: Likewise.
  * testsuite/ld-plugin/lto-5r.d: Likewise.
  * testsuite/ld-plugin/lto.exp: Likewise.
  * testsuite/ld-powerpc/ppc476-shared.d: Likewise.
  * testsuite/ld-powerpc/ppc476-shared2.d: Likewise.
  * testsuite/ld-powerpc/pr28827-2.d: Likewise.
  * testsuite/ld-s390/s390.exp: Likewise.
  * testsuite/ld-scripts/align2a.d: Likewise.
  * testsuite/ld-scripts/align2b.d: Likewise.
  * testsuite/ld-scripts/align5.d: Likewise.
  * testsuite/ld-scripts/alignof.exp: Likewise.
  * testsuite/ld-scripts/crossref.exp: Likewise.
  * testsuite/ld-scripts/defined2.d: Likewise.
  * testsuite/ld-scripts/defined3.d: Likewise.
  * testsuite/ld-scripts/defined5.d: Likewise.
  * testsuite/ld-scripts/pr14962.d: Likewise.
  * testsuite/ld-scripts/pr18963.d: Likewise.
  * testsuite/ld-scripts/pr20302.d: Likewise.
  * testsuite/ld-scripts/print-memory-usage.exp: Likewise.
  * testsuite/ld-scripts/rgn-at1.d: Likewise.
  * testsuite/ld-scripts/rgn-at10.d: Likewise.
  * testsuite/ld-scripts/rgn-at4.d: Likewise.
  * testsuite/ld-scripts/rgn-at6.d: Likewise.
  * testsuite/ld-scripts/rgn-at8.d: Likewise.
  * testsuite/ld-scripts/rgn-at9.d: Likewise.
  * testsuite/ld-scripts/rgn-over1.d: Likewise.
  * testsuite/ld-scripts/rgn-over2.d: Likewise.
  * testsuite/ld-scripts/rgn-over4.d: Likewise.
  * testsuite/ld-scripts/rgn-over5.d: Likewise.
  * testsuite/ld-scripts/rgn-over6.d: Likewise.
  * testsuite/ld-scripts/script.exp: Likewise.
  * testsuite/ld-scripts/sizeof.exp: Likewise.
  * testsuite/ld-scripts/sort-file.d: Likewise.
  * testsuite/ld-x86-64/discarded1.d: Likewise.
  * testsuite/ld-x86-64/pr19175.d: Likewise.
  * testsuite/ld-x86-64/pr19539a.d: Likewise.
  * testsuite/ld-x86-64/pr19539b.d: Likewise.
  * testsuite/ld-x86-64/pr23189.d: Likewise.
2023-11-10 11:37:27 +00:00
GDB Administrator
e0446214a0 Automatic date update in version.in 2023-11-10 00:00:07 +00:00
Michael Matz
21160d8a18 bfd: use less memory in string merging
the offset-to-entry mappings are allocated in blocks, which may
become a bit wasteful in case there are extremely many small
input files or sections.  This made it so that a large project
(Qt5WebEngine) didn't build anymore on x86 32bit due to address
space limits.  It barely fit into address space before the new
string merging, and then got pushed over the limit by this.

So instead of leaving the waste reallocate the maps to their final
size once known.  Now the link barely fits again.

bfd/
    * merge.c (record_section): Reallocate offset maps to their
    final size.
2023-11-09 17:42:48 +01:00
Michael Matz
836654b117 ld: Avoid overflows in string merging
as the bug report shows we had an overflow in the test if
hash table resizing is needed.  Reorder the expression to avoid
that.  There's still a bug somewhere in gracefully handling
failure in resizing (e.g. out of memory), but this pushes the
boundary for that occurring somewhen into the future and
immediately helps the reporter.

    bfd/

    PR ld/31009
    * merge.c (NEEDS_RESIZE): New macro avoiding overflow.
    (sec_merge_maybe_resize): Use it.
    (sec_merge_hash_insert): Ditto.
2023-11-09 17:42:04 +01:00
Szabolcs Nagy
fc48504c7a bfd: aarch64: Avoid BTI stub for a PLT that has BTI
We decide to emit BTI stubs based on the instruction at the target
location. But PLT code is generated later than the stubs so we always
read 0 which is not a valid BTI.

Fix the logic to special case the PLT section: this is code the linker
generates so we know when it will have BTI.

This avoids BTI stubs in large executables where the PLTs have them
already. An alternative is to never emit BTI stubs for PLTs, instead
use BTI in the PLT if a library gets too big, however that may be
more tricky given the ordering of PLT sizing and stub insertion.

Related to bug 30957.
2023-11-09 14:44:37 +00:00
Szabolcs Nagy
a74ac8c419 bfd: aarch64: Fix leaks in case of BTI stub reuse
BTI stub parameters were recomputed even if those were already set up.
This is unnecessary work and leaks the symbol name that is allocated
for the stub.
2023-11-09 14:44:37 +00:00
Szabolcs Nagy
d3a8dfdef0 bfd: aarch64: Fix broken BTI stub PR30930
Input sections are grouped together that can use the same stub area
(within reach) and these groups have a stable id.

Stubs have a name generated from the stub group id and target symbol.
When a relocation requires a stub with a name that already exists, the
stub is reused instead of adding a new one.

For an indirect branch stub another BTI stub may be inserted near the
target to provide a BTI landing pad.

The BTI stub can end up with the same stub group id and thus the same
name as the indirect stub. This happens if the target symbol is within
reach of the indirect branch stub. Then, due to the name collision,
only a single stub was emmitted which branched to itself causing an
infinite loop at runtime.

A possible solution is to just name the BTI stubs differently, but
since in the problematic case the indirect and BTI stub are in the
same stub area, a better solution is to emit a single stub with a
direct branch. The stub is still needed since the caller cannot reach
the target directly and we also want a BTI landing pad in the stub in
case other indirect stubs target the same symbol and thus need a BTI
stub.

In short we convert an indirect branch stub into a BTI stub when the
target is within reach and has no BTI. It is a hassle to change the
symbol of the stub so a BTI stub may end up with *_veneer instead of
*_bti_veneer after the conversion, but this should not matter much.
(Refactoring some of _bfd_aarch64_add_call_stub_entries would be
useful but too much for this bug fix patch.)

The same conversion to direct branch could be done even if the target
did not need a BTI. The stub groups are fixed in the current logic so
linking can fail if too many stubs are inserted and the section layout
is changed too much, but this only happens in extreme cases that can
be reasonably ignored. Because of this the target cannot go out of
reach during stub insertion so the optimization is valid, but not
implemented by this patch for the non-BTI case.

Fixes bug 30930.
2023-11-09 14:44:37 +00:00
Szabolcs Nagy
98b94ebb3f bfd: aarch64: Fix BTI stub optimization PR30957
The instruction was looked up in the wrong input file (file of branch
source instead of branch target) when optimizing away BTI stubs in

  commit 5834f36d93
  bfd: aarch64: Optimize BTI stubs PR30076

This can cause adding BTI stubs when they are not necessary or removing
them when they are (the latter is a correctness issue but it is very
unlikely in practice).

Fixes bug 30957.
2023-11-09 14:44:37 +00:00
GDB Administrator
cf5f570bd0 Automatic date update in version.in 2023-11-09 00:00:33 +00:00
Clément Chigot
fb29080935 ld: print branch fixups into the map file for ppc elf targets
In a safety context, it could interesting to track the trampolines being
generated, ensuring there are expected or not.

bfd/ChangeLog:

	* elf32-ppc.c (ppc_elf_relax_section): Log branch fixups.

ld/ChangeLog:

	* ld.texi (--print-map): Add new item about fixups.
2023-11-08 09:07:02 +01:00
Tom Tromey
1185b5b79a Add minimal thread-safety to BFD
This patch provides some minimal thread-safety to BFD.

The BFD client can request thread-safety by providing a lock and
unlock function.  The globals used during BFD creation (e.g.,
bfd_id_counter) are then locked, and the file descriptor cache is also
locked.  A function to clean up any thread-local data is now provided
for BFD clients.

	* bfd-in2.h: Regenerate.
	* bfd.c (lock_fn, unlock_fn): New globals.
	(bfd_thread_init, bfd_thread_cleanup, bfd_lock, bfd_unlock): New
	functions.
	* cache.c (bfd_cache_lookup_worker): Use _bfd_open_file_unlocked.
	(cache_btell, cache_bseek, cache_bread, cache_bwrite): Lock
	and unlock.
	(cache_bclose): Add comment.
	(cache_bflush, cache_bstat, cache_bmmap): Lock and unlock.
	(_bfd_cache_init_unlocked): New function.
	(bfd_cache_init): Use it.  Lock and unlock.
	(_bfd_cache_close_unlocked): New function.
	(bfd_cache_close, bfd_cache_close_all): Use it.  Lock and unlock.
	(_bfd_open_file_unlocked): New function.
	(bfd_open_file): Use it.  Lock and unlock.
	* doc/bfd.texi (BFD front end): Add Threading menu item.
	* libbfd.h: Regenerate.
	* opncls.c (_bfd_new_bfd): Lock and unlock.
	* po/bfd.pot: Regenerate.
2023-11-07 17:47:16 -07:00
Tom Tromey
c6d6a048f5 Make various error-related globals thread-local
This changes bfd_error et al to be thread-local.

	* Makefile.in: Regenerate.
	* aclocal.m4: Include ax_tls.m4.
	* ax_tls.m4: New file.
	* bfd.c: (bfd_error, input_error, input_bfd, _bfd_error_buf):
	Now thread-local.
	(bfd_asprintf): Update docs.
	* config.in, configure: Regenerate.
	* configure.ac: Call AX_TLS.
	* po/bfd.pot: Regenerate.
2023-11-07 17:47:12 -07:00
Tom Tromey
426931be4b Make _bfd_error_buf static
This makes _bfd_error_buf static and adds a way to clear it.  I felt
that this made the subsequent patches a little cleaner.

	* bfd.c (_bfd_error_buf): Now static.
	(bfd_set_input_error): Use _bfd_clear_error_data.
	(_bfd_clear_error_data): New function.
	(bfd_init): Use _bfd_clear_error_data.
	* libbfd.h: Regenerate.
	* opncls.c (bfd_close_all_done): Use _bfd_clear_error_data.
	* po/bfd.pot: Regenerate.
2023-11-07 17:30:15 -07:00
GDB Administrator
9da76ef30c Automatic date update in version.in 2023-11-08 00:00:26 +00:00
Mary Bennett
d1bd9787f9 RISC-V: Add support for XCValu extension in CV32E40P
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html

Contributors:
  Mary Bennett <mary.bennett@embecosm.com>
  Nandni Jamnadas <nandni.jamnadas@embecosm.com>
  Pietra Ferreira <pietra.ferreira@embecosm.com>
  Charlie Keaney
  Jessica Mills
  Craig Blackmore <craig.blackmore@embecosm.com>
  Simon Cook <simon.cook@embecosm.com>
  Jeremy Bennett <jeremy.bennett@embecosm.com>
  Helene Chelin <helene.chelin@embecosm.com>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Added `xcvalu`
          instruction class.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* config/tc-riscv.c (validate_riscv_insn): Added the necessary
          operands for the extension.
	(riscv_ip): Likewise.
	* doc/c-riscv.texi: Noted XCValu as an additional ISA extension
          for CORE-V.
	* testsuite/gas/riscv/cv-alu-boundaries.d: New test.
	* testsuite/gas/riscv/cv-alu-boundaries.l: New test.
	* testsuite/gas/riscv/cv-alu-boundaries.s: New test.
	* testsuite/gas/riscv/cv-alu-fail-march.d: New test.
	* testsuite/gas/riscv/cv-alu-fail-march.l: New test.
	* testsuite/gas/riscv/cv-alu-fail-march.s: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-01.d: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-01.l: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-01.s: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-02.d: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-02.l: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-02.s: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-03.d: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-03.l: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-03.s: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-04.d: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-04.l: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-04.s: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-05.d: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-05.l: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-05.s: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-06.d: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-06.l: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-06.s: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-07.d: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-07.l: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-07.s: New test.
	* testsuite/gas/riscv/cv-alu-insns.d: New test.
	* testsuite/gas/riscv/cv-alu-insns.s: New test.

opcodes/ChangeLog:

	* riscv-dis.c (print_insn_args): Disassemble xcb operand.
	* riscv-opc.c: Defined the MASK and added XCValu instructions.

include/ChangeLog:

	* opcode/riscv-opc.h: Added corresponding MATCH and MASK macros
          for XCValu.
	* opcode/riscv.h: Added corresponding EXTRACT and ENCODE macros
          for XCValu.
	(enum riscv_insn_class): Added the XCValu instruction class.
2023-11-07 12:06:32 +08:00
Mary Bennett
ccb388ca39 RISC-V: Add support for XCVmac extension in CV32E40P
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html

Contributors:
  Mary Bennett <mary.bennett@embecosm.com>
  Nandni Jamnadas <nandni.jamnadas@embecosm.com>
  Pietra Ferreira <pietra.ferreira@embecosm.com>
  Charlie Keaney
  Jessica Mills
  Craig Blackmore <craig.blackmore@embecosm.com>
  Simon Cook <simon.cook@embecosm.com>
  Jeremy Bennett <jeremy.bennett@embecosm.com>
  Helene Chelin <helene.chelin@embecosm.com>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Added `xcvmac`
          instruction class.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* config/tc-riscv.c (validate_riscv_insn): Added the necessary
          operands for the extension.
	(riscv_ip): Likewise.
	* doc/c-riscv.texi: Noted XCVmac as an additional ISA extension
          for CORE-V.
	* testsuite/gas/riscv/cv-mac-fail-march.d: New test.
	* testsuite/gas/riscv/cv-mac-fail-march.l: New test.
	* testsuite/gas/riscv/cv-mac-fail-march.s: New test.
	* testsuite/gas/riscv/cv-mac-fail-operand.d: New test.
	* testsuite/gas/riscv/cv-mac-fail-operand.l: New test.
	* testsuite/gas/riscv/cv-mac-fail-operand.s: New test.
	* testsuite/gas/riscv/cv-mac-insns.d: New test.
	* testsuite/gas/riscv/cv-mac-insns.s: New test.

opcodes/ChangeLog:

	* riscv-dis.c (print_insn_args): Disassemble information with
          the EXTRACT macro implemented.
	* riscv-opc.c: Defined the MASK and added
          XCVmac instructions.

include/ChangeLog:

	* opcode/riscv-opc.h: Added corresponding MATCH and MASK macros
          for XCVmac.
	* opcode/riscv.h: Added corresponding EXTRACT and ENCODE macros
          for uimm.
	(enum riscv_insn_class): Added the XCVmac instruction class.
2023-11-07 12:06:27 +08:00
GDB Administrator
e0da5ef09c Automatic date update in version.in 2023-11-07 00:00:18 +00:00
Nelson Chu
0c4b8ed69c RISC-V: Moved out linker internal relocations after R_RISCV_max.
Just the lightest modifications about this, without any further checks and
considering --emit-relocs.  We will need to improve it in the future, but
first do this to avoid conflicts between linker internal relocations and the
new definition of psabi.  For example, TLSDESC relocs.

Passed riscv-gnu-toolchain regressions, so should be safe enough to commit.

Co-authored-by: Tsukasa OI <research_trasio@irq.a4lg.com>

bfd/
	* reloc.c: Removed linker internal relocations.
	* bfd-in2.h: Regenerated.
	* libbfd.h: Regenerated.
	* elfnn-riscv.c: Defined R_RISCV_DELETE in include/elf/riscv.h.
	* elfxx-riscv.c (howto_table, howto_table_internal): Moved linker
	internal relocations from howto_table into howto_table_internal.
	(riscv_reloc_map): Removed linker internal relocations mapping.
	(riscv_elf_rtype_to_howto): Return howto of linker internal
	relocations from howto_table_internal.
include/
	* elf/riscv.h: Defined linker internal relocations after R_RISCV_max.
2023-11-06 17:21:42 +08:00
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Nick Clifton
a4a51292bb Accept and ignore the R_BPF_64_NODLYD32 relocation. 2023-10-30 12:18:45 +00:00
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Nelson Chu
2029e13917 RISC-V: Clarify the behaviors of SET/ADD/SUB relocations.
We are used to generate these kinds of relocations by data directives.
Considering the following example,
.word (A + 3) - (B + 2)
The GAS will generate a pair of ADD/SUB for this,
R_RISCV_ADD, A + 1
R_RISCV_SUB, 0

The addend of R_RISCV_SUB will always be zero, and the summary of the
constants will be stored in the addend of R_RISCV_ADD/SET.  Therefore,
we can always add the addend of these data relocations when doing relocations.

But unfortunately, I had heard that if we are using .reloc to generate
the data relocations will make the relocations failed.  Refer to this,
.reloc offset, R_RISCV_ADD32, A + 3
.reloc offset, R_RISCV_SUB32, B + 2
.word 0
Then we can get the relocations as follows,
R_RISCV_ADD, A + 3
R_RISCV_SUB, B + 2
Then...  Current LD does the relocation, B - A + 3 + 2, which is wrong
obviously...

So first of all, this patch fixes the wrong relocation behavior of
R_RISCV_SUB* relocations.

Afterwards, considering the uleb128 direcitve, we will get a pair of
SET_ULEB128/SUB_ULEB128 relocations for it for now,
.uleb128 (A + 3) - (B + 2)
R_RISCV_SET_ULEB128, A + 1
R_RISCV_SUB_ULEB128, B + 1

Which looks also wrong obviously, the summary of the constants should only
be stored into the addend of SET_ULEB128, and the addend of SUB_ULEB128 should
be zero like other SUB relocations.  But the current LD will still get the right
relocation values since we only add the addend of SUB_ULEB128 by accident...
Anyway, this patch also fixes the behaviors above, to make sure that no matter
using .uleb128 or .reloc directives, we should always get the right values.

bfd/
	* elfnn-riscv.c (perform_relocation):  Clarify that SUB relocations
	should substract the addend, rather than add.
	(riscv_elf_relocate_section): Since SET_ULEB128 won't go into
	perform_relocation, we should add it's addend here in advance.
gas/
	* config/tc-riscv.c (riscv_insert_uleb128_fixes): Set the addend of
	SUB_ULEB128 to zero since it should already be added into the addend
	of SET_ULEB128.
2023-10-27 08:33:19 +08:00