111951 Commits

Author SHA1 Message Date
36354a49b6 [testsuite] gdb.base/dlmopen: Fix test name and use gdb_attach
One test name in gdb.base/dlmopen.exp changes from run to run
since it includes a process id:

    PASS: gdb.base/dlmopen.exp: attach 3442682

This is not convenient do diff gdb.sum files to compare test runs.

Fix by using gdb_attach helper function to handle attaching to the
process as it produce a constant test name.

While at it also check gdb_attach's return value to only run the
rest of the test if the attach was successful.

Approved-By: Simon Marchi <simon.marchi@efficios.com>
2022-11-04 16:18:27 +00:00
45830439ce PowerPC update comments for the MMA instruction name changes.
The mnemonics for the pmxvf16ger*, pmxvf32ger*,pmxvf64ger*, pmxvi4ger8*,
pmxvi8ger4*, and pmxvi16ger2* instructions were officially changed to
pmdmxbf16ger*, pmdmxvf32ger*, pmdmxvf64ger*, pmdmxvi4ger8*, pmdmxvi8ger4*,
pmdmxvi16ger* respectively.  The old mnemonics are still supported by the
assembler as extended mnemonics.  The disassembler generates the new
mnemonics.  The name changes occurred in commit:

  commit bb98553cad4e017f1851153fa5de91f2cee98fb2
  Author: Peter Bergner <bergner@linux.ibm.com>
  Date:   Sat Oct 8 16:19:51 2022 -0500

    PowerPC: Add support for RFC02658 - MMA+ Outer-Product Instructions

    gas/
            * config/tc-ppc.c (md_assemble): Only check for prefix opcodes.
            * testsuite/gas/ppc/rfc02658.s: New test.
            * testsuite/gas/ppc/rfc02658.d: Likewise.
            * testsuite/gas/ppc/ppc.exp: Run it.

    opcodes/
            * ppc-opc.c (XMSK8, P_GERX4_MASK, P_GERX2_MASK, XX3GERX_MASK): New.
            (powerpc_opcodes): Add dmxvi8gerx4pp, dmxvi8gerx4, dmxvf16gerx2pp,
            dmxvf16gerx2, dmxvbf16gerx2pp, dmxvf16gerx2np, dmxvbf16gerx2,
            dmxvi8gerx4spp, dmxvbf16gerx2np, dmxvf16gerx2pn, dmxvbf16gerx2pn,
            dmxvf16gerx2nn, dmxvbf16gerx2nn, pmdmxvi8gerx4pp, pmdmxvi8gerx4,
            pmdmxvf16gerx2pp, pmdmxvf16gerx2, pmdmxvbf16gerx2pp, pmdmxvf16gerx2np,
            pmdmxvbf16gerx2, pmdmxvi8gerx4spp, pmdmxvbf16gerx2np, pmdmxvf16gerx2pn,
            pmdmxvbf16gerx2pn, pmdmxvf16gerx2nn, pmdmxvbf16gerx2nn.

This patch updates the comments in the various gdb files to reflect the
name changes.  There are no functional changes made by this patch.

The older instruction names are still used in the test
gdb.reverse/ppc_record_test_isa_3_1.exp for backwards compatibility.

Patch has been tested on Power 10 with no regressions.
2022-11-04 12:14:01 -04:00
49977100a1 PowerPC fix for the gdb.arch/powerpc-power10.exp test.
The mnemonics for the pmxvf16ger*, pmxvf32ger*,pmxvf64ger*, pmxvi4ger8*,
pmxvi8ger4*, pmxvi16ger2* instructions were officially changed to
pmdmxvf16ger*, pmdmxvf32ger*, pmdmxvf64ger*, pmdmxvi4ger8*, pmdmxvi8ger4*,
pmdmxvi16ger* respectively.  The old mnemonics are still supported by the
assembler as extended mnemonics.  The disassembler generates the new
mnemonics.  The name changes occurred in commit:

  commit bb98553cad4e017f1851153fa5de91f2cee98fb2
  Author: Peter Bergner <bergner@linux.ibm.com>
  Date:   Sat Oct 8 16:19:51 2022 -0500

    PowerPC: Add support for RFC02658 - MMA+ Outer-Product Instructions

    gas/
            * config/tc-ppc.c (md_assemble): Only check for prefix opcodes.
            * testsuite/gas/ppc/rfc02658.s: New test.
            * testsuite/gas/ppc/rfc02658.d: Likewise.
            * testsuite/gas/ppc/ppc.exp: Run it.

    opcodes/
            * ppc-opc.c (XMSK8, P_GERX4_MASK, P_GERX2_MASK, XX3GERX_MASK): New.
            (powerpc_opcodes): Add dmxvi8gerx4pp, dmxvi8gerx4, dmxvf16gerx2pp,
            dmxvf16gerx2, dmxvbf16gerx2pp, dmxvf16gerx2np, dmxvbf16gerx2,
            dmxvi8gerx4spp, dmxvbf16gerx2np, dmxvf16gerx2pn, dmxvbf16gerx2pn,
            dmxvf16gerx2nn, dmxvbf16gerx2nn, pmdmxvi8gerx4pp, pmdmxvi8gerx4,
            pmdmxvf16gerx2pp, pmdmxvf16gerx2, pmdmxvbf16gerx2pp, pmdmxvf16gerx2np,
            pmdmxvbf16gerx2, pmdmxvi8gerx4spp, pmdmxvbf16gerx2np, pmdmxvf16gerx2pn,
            pmdmxvbf16gerx2pn, pmdmxvf16gerx2nn, pmdmxvbf16gerx2nn.

The above commit results in about 224 failures on Power 10 since the
disassembled names do not match the expected names in the test.  This
patch updates the expected names in the test to match the values produced
by the disassembler.

This patch updates file gdb.arch/powerpc-power10.exp with the new expected
values to the instructions.  The comment giving the name of the instruction
for each binary value in the file gdb.arch/powerpc-power10.c is updated
with the new name.   There are no functional changes in file
gdb.arch/powerpc-power10.c.
2022-11-04 12:13:52 -04:00
91836f41e2 Powerpc fix for gdb.base/unwind-on-each-insn.exp
The test disassembles function foo and searches for the line
"End of assembler dump" to determing the last address in the function.  The
assumption is the last instruction will be given right before the line
"End of assembler dump".  This assumption fails on PowerPC.

The PowerPC disassembly of the function foo looks like:
 Dump of assembler code for function foo:
#  => 0x00000000100006dc <+0>:     std     r31,-8(r1)
#     0x00000000100006e0 <+4>:     stdu    r1,-48(r1)
#     0x00000000100006e4 <+8>:     mr      r31,r1
#     0x00000000100006e8 <+12>:    nop
#     0x00000000100006ec <+16>:    addi    r1,r31,48
#     0x00000000100006f0 <+20>:    ld      r31,-8(r1)
#     0x00000000100006f4 <+24>:    blr
#     0x00000000100006f8 <+28>:    .long 0x0
#     0x00000000100006fc <+32>:    .long 0x0
#     0x0000000010000700 <+36>:    .long 0x1000180
#     End of assembler dump.

The blr instruction is the last instruction in function foo.  The lines
with .long following the blr instruction need to be ignored.

This patch adds a new condition to the gdb_test_multiple "disassemble foo"
test to ignore the lines with the .long.

The patch has been tested on PowerPC and Intel X86-64.
2022-11-04 12:06:37 -04:00
ac87b20a96 x86: adjust recently introduced testcases
The issue addressed by 2c02c72c62d2 ("re: Support Intel AMX-FP16") has
been introduced once again in a number of new tests.
2022-11-04 14:13:01 +01:00
1da0b075ae Update release documentation with regard to uploading gprofng docs 2022-11-04 12:01:03 +00:00
476410b3bc gdb/testsuite: add KFAILs to gdb.reverse/step-reverse.exp
Recent changes to gdb.reverse/step-reverse.exp revealed the latent bug
PR record/29745, where we can't skip one funcion forward if we're using
native-gdbserver. This commit just adds kfails to the test.

Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=29745
Approved-By: Simon Marchi <simon.marchi@efficios.com>
2022-11-04 12:02:32 +01:00
d8521074fe opcodes/arm: silence compiler warning about uninitialized variable use
After this commit:

  commit 6576bffe6cbbb53c5756b2fccd2593ba69b74cdf
  Date:   Thu Jul 7 13:43:45 2022 +0100

      opcodes/arm: add disassembler styling for arm

Some people were seeing their builds failing with complaints about a
possible uninitialized variable usage.  I previously fixed an instance
of this issue in this commit:

  commit 2df82cd4b459fbc32120e0ad1ce19e26349506fe
  Date:   Tue Nov 1 10:36:59 2022 +0000

      opcodes/arm: silence compiler warning about uninitialized variable use

which did fix the build problems that the sourceware buildbot was
hitting, however, an additional instance of the same problem was
brought to my attention, and that is fixed in this commit.

Where commit 2df82cd4b4 fixed the uninitialized variable problem in
print_mve_unpredictable, this commit fixes the same problem in
print_mve_undefined.

As with the previous commit, I don't believe we could really ever get
an uninitialized variable usage, based on the current usage of the
function, so I have just initialized the reason variable to "??".
2022-11-04 10:46:59 +00:00
b0119424d1 sim: rx: drop unused $arch setting
This is only needed for CGEN ports which RX isn't, so drop it.
2022-11-04 14:23:50 +07:00
9146585a05 sim: build: remove various obsolete generation dep variables
These manual settings were necessary when we weren't doing automatic
header dependency tracking.  That was changed a while ago, and we use
automake now to do it all for us.  As a result, many of these vars
aren't even referenced anymore.

Further, some of the source file generation (e.g. .c files, or igen,
or cgen outputs) were moved to the common automake build, and it takes
care of dependency tracking for us with the object files.
2022-11-04 13:58:42 +07:00
c55c1f6e9d sim: don't hardcode -ldl for SDL support
Since we use AC_SEARCH_LIBS to find dlopen, we don't need to hardcode
-ldl when using SDL ourselves.
2022-11-04 13:50:37 +07:00
01d8ce742c Support Intel AVX-NE-CONVERT
gas/ChangeLog:

	* NEWS: Support Intel AVX-NE-CONVERT.
	* config/tc-i386.c: Add avx_ne_convert.
	* doc/c-i386.texi: Document .avx_ne_convert.
	* testsuite/gas/i386/i386.exp: Run AVX NE CONVERT tests.
	* testsuite/gas/i386/avx-ne-convert-intel.d: New test.
	* testsuite/gas/i386/avx-ne-convert.d: Ditto.
	* testsuite/gas/i386/avx-ne-convert.s: Ditto.
	* testsuite/gas/i386/x86-64-avx-ne-convert-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx-ne-convert.d: Ditto.
	* testsuite/gas/i386/x86-64-avx-ne-convert.s: Ditto.

opcodes/ChangeLog:

	* i386-dis.c (Mw): New.
	(PREFIX_VEX_0F3872): Ditto.
	(PREFIX_VEX_0F38B0_W_0): Ditto.
	(PREFIX_VEX_0F38B1_W_0): Ditto.
	(VEX_W_0F3872_P_1): Ditto.
	(VEX_W_0F38B0): Ditto.
	(VEX_W_0F38B1): Ditto.
	(prefix_table): Add PREFIX_VEX_0F3872, PREFIX_VEX_0F38B0_W_0,
	PREFIX_VEX_0F38B1_W_0.
	(vex_w_table): Add VEX_W_0F3872_P_1, VEX_W_0F38B0, VEX_W_0F38B1.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX_NE_CONVERT_FLGAS and
	CPU_ANY_AVX_NE_CONVERT_FLAGS.
	(cpu_flags): Add CpuAVX_NE_CONVERT.
	* i386-init.h: Regenerated.
	* i386-opc.h (CpuAVX_NE CONVERT): New.
	(i386_cpu_flags): Add cpuavx_ne_convert.
	* i386-opc.tbl: Add Intel AVX-NE-CONVERT instructions.
	* i386-tbl.h: Regenerated.
2022-11-04 11:42:17 +08:00
4e0dd3abff i386: Rename <xy> template.
opcodes/
            * i386-opc.tbl: Rename <xy> template for VEX insn with x/y suffix to <Vxy>.
	    Rename <xy> for EVEX insn with x/y suffix to <Exy>.
2022-11-04 11:42:15 +08:00
853ba67882 Support multiple .eh_frame sections
This patch is based on MULTIPLE_FRAME_SECTIONS and EH_FRAME_LINKONCE,
	it allows backend to enable this feature and use '--gc-sections' simply.

	* gas/dw2gencfi.h (TARGET_MULTIPLE_EH_FRAME_SECTIONS): New.
	(MULTIPLE_FRAME_SECTIONS): Add TARGET_MULTIPLE_EH_FRAME_SECTIONS.
	* gas/dw2gencfi.c (EH_FRAME_LINKONCE): Add TARGET_MULTIPLE_EH_FRAME_SECTIONS.
	(is_now_linkonce_segment): Likewise.
	(get_cfi_seg): Create relocation info between .eh_frame.* and .text.* section.

	* bfd/elf-bfd.h (elf_backend_can_make_multiple_eh_frame): New.
	* bfd/elfxx-target.h (elf_backend_can_make_multiple_eh_frame): Likewise.
	* bfd/elflink.c (_bfd_elf_default_action_discarded): Add checking for
	elf_backend_can_make_multiple_eh_frame.
2022-11-04 10:30:18 +08:00
a494349e80 gas/doc/internals.texi: fix typo
* gas/doc/internals.texi (md_emit_single_noop_insn):
	fix '@var missing closing brace'
	* gas/doc/internals.texi (Hash tables):
	fix '@menu reference to nonexistent node `Hash tables''
2022-11-04 09:53:17 +08:00
0dea8b8d9f sim: drop -lm from SIM_EXTRA_LIBS
We have configure tests for this in the top-level configure script
to link this when necessary, so we don't need to explicitly list it
for specific ports.
2022-11-04 07:42:31 +07:00
051081585e sim: build: change AC_CHECK_LIB to AC_SEARCH_LIBS
With more C libraries moving functions entirely into the main -lc,
change the AC_CHECK_LIB calls to AC_SEARCH_LIBS so we look in there
first and avoid extra linkage when possible.
2022-11-04 07:42:31 +07:00
49ea4303bf sim: build: drop duplicate $(LIBS) usage
COMMON_LIBS is set to $(LIBS), and CONFIG_LIBS is set to that plus
@LIBS@.  This leds to the values being used twice.  Inline the
CONFIG_LIBS variable without @LIBS@ since it's used only once.
2022-11-04 07:42:31 +07:00
89cf99a910 sim: build: switch to bfd & opcodes libtool linker scripts
Now that we use libtool to link, we don't need to duplicate all the
libs that bfd itself uses.  This simplifies the configure & Makefile.
2022-11-04 07:42:31 +07:00
90db43bb03 sim: build: switch to libtool for linking
The top-level already sets up a libtool script for the host, so use
that when linking rather than invoking CC directly.  This will also
happen when we (someday) move the building to pure automake.
2022-11-04 07:42:31 +07:00
231f62da1d Automatic date update in version.in 2022-11-04 00:00:16 +00:00
7b3dd7b9b3 sim: testsuite: fix cris stat3 in diff setups
This test uses the test itself as an input to stating regular files.
This gets funky though: when we run check in parallel, the output
object dir is the subdir that matches the .exp file.  When we run
with -j1, the output object dir is the sim builddir itself.

The old test would append argv[0] to find the file, while the new
test uses basename on it.  Each method works in only one of the
aforementioned build scenarios.  Rather than complicate this any
more, switch to a different file that we know will always exist:
the Makefile.
2022-11-04 01:42:41 +07:00
4ce3ba0865 sim: testsuite: fix cris badarch in multi-target builds
This test assumes that /bin/sh will never be a CRIS ELF by way of
assuming that the current bfd cannot load it (since a basic cris
cross-compiler only understands CRIS ELFs).  In a multi-target
build though, bfd understands just about every ELF out there, so
we're able to read the /bin/sh format before failing at a diff
point in the cris code.

Let's switch to using / instead since it'll fail for a similar
reason (at least similar enough for what this test is testing).
2022-11-04 01:42:41 +07:00
2734f0a275 sim: cleanup unused SIM_EXTRA_CFLAGS
We want to eventually delete this, so at least drop the empty ones.
2022-11-04 01:40:38 +07:00
8183b5f53f sim: m32c/rx: drop useless $(ENDLIST)
This is used to allow for dangling \ in object lists, but these are the
only ports that do it, and it isn't really necessary.  Punt it to keep
the various makefiles harmonized.
2022-11-04 01:39:05 +07:00
ccc4ba5959 sim: mips: simplify fpu configure logic
The configure code always defaults to HARD_FLOATING_POINT, so inline
that value and drop redundant target checks as a result.
2022-11-04 01:37:16 +07:00
fa71c76d47 sim: erc32: link sis to run program
The erc32 sim does a lot itself, including handling of the CLI.  It
used to provide a run-compatible interface in the pre-nrun days, but
it was dropped when the old run interface was punted.  Since the old
commit 465fb143c87076b6416a8d0d5dd79bb016060fe3 ("sim: make nrun the
default run program"), the erc32 run & sis programs have been the
same, and erc32 hasn't provide a real run-compatible interface.

Simplify this by linking the two programs via ln/cp instead of running
the linking phase twice to produce the same result.  If/when we fix up
the erc32 port to have a proper run interface, it should be easy to
split these back apart into real programs.

Note: the interf.o reference in here is a bit of a misdirect.  Since
that object is placed into libsim.a, it's never been linked into the
programs since the linker ignores objects that aren't referenced, and
only gdb uses those symbols.
2022-11-04 01:37:07 +07:00
e26943f9c7 V850 Linker: do not complain about RWX segments.
PR 29748
	* configure.tgt (ac_default_ld_warn_rwx_segments): Set to 0 for
	the V850.
2022-11-03 16:27:31 +00:00
b830591caf sim: v850: switch to standard (high-level) trace defines
The v850 port uses -DDEBUG to control whether to enable internal tracing.
We already have such options via the common trace framework, and those
can be controlled at build time via configure flags (which the v850 code
currently cannot).  So switch it over to WITH_TRACE_ANY_P to simplify the
v850 build code even if it doesn't (yet) respect any other trace options.
2022-11-03 22:21:04 +07:00
75bed973c8 sim: ppc: include copyright & license in --version
This makes it match the other sim run programs and GNU tools.
2022-11-03 20:15:29 +07:00
4556d82e8a sim: update --version copyright year
Probably should have done this 11 months ago ...
2022-11-03 20:09:09 +07:00
d91d55b907 sim: ppc: drop use of DATE & TIME
No other tool does this, sim or otherwise, and it makes the ppc build
non-reproducible.  Drop it to simplify & make reproducible.
2022-11-03 20:09:07 +07:00
e7e7469e7a gdb: Fix issue with Clang CLI macros
Clang up to version 15 (current) adds macros that were defined in the
command line or by "other means", according to the Dwarf specification,
after the last DW_MACRO_end_file, instead of before the first
DW_MACRO_start_file, as the specification dictates.  When GDB reads the
macros after the last file is closed, the macros never end up "in scope"
and so we can't print them.  This has been submitted as a bug to Clang
developers (https://github.com/llvm/llvm-project/issues/54506), and PR
macros/29034 was opened for GDB to keep track of this.

Seeing as there is no expected date for it to be fixed, add a workaround
for all current versions of Clang.  The workaround detects when
the main file would be closed and if the producer is Clang, and turns
that operation into a noop, so we keep a reference to the current_file
as those macros are read.

A test case was added to confirm the functionality, and the KFAIL for
running gdb.base/macro-source-path when using clang.

Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=29034
Approved-By: Simon Marchi <simon.marchi@efficios.com>
2022-11-03 14:08:17 +01:00
78cd9188d0 AVR Linker: Allow the start of the data region to be specified on the linker command line. [Fix PR number in ChangeLog entry]
PR 29741
	* scripttempl/avr.sc (__DATA_REGION_ORIGIN__): Define.  If a value
	has not been provided on the command line then use DATA_ORIGIN.
	(MEMORY): Use __DATA_REGION_ORIGIN__ as the start of the data region.
2022-11-03 09:20:37 +00:00
fa6895ad35 AVR Linker: Allow the start of the data region to specified on the command line.
PR 29471
	* scripttempl/avr.sc (__DATA_REGION_ORIGIN__): Define.  If a value
	has not been provided on the command line then use DATA_ORIGIN.
	(MEMORY): Use __DATA_REGION_ORIGIN__ as the start of the data region.
2022-11-03 09:17:41 +00:00
a1af8f405c sim: move common flags to default AM_CPPFLAGS
Since all host files we compile use these settings, move them out of
libcommon.a and into the default AM_CPPFLAGS.  This has the effect of
dropping the custom per-target automake rules.  Currently it saves us
~150 lines, but since it's about ~8 lines per object, the overhead
will increase quite a bit as we merge more files into a single build.

This also changes the object output names, so we have to tweak the
rules that were pulling in the common objects when linking.
2022-11-03 12:55:19 +05:45
46a1e1f20b sim: merge gnulib logic into the top-level
We aren't using this just yet, but we will, so make it available to
building of common sim files.
2022-11-03 12:53:49 +05:45
ca7b34c5be sim: common: remove unused include paths
A bunch of these paths don't include any headers, and most likely
never will, so there's no real need to keep them.  This will let
us harmonize paths with the top-level Makefile more easily, which
will in turn make it easier to move more compile steps there.
2022-11-03 12:51:21 +05:45
ae1c45ead6 Automatic date update in version.in 2022-11-03 00:00:08 +00:00
7eb96b2f03 arm: PR 29739 Fix typo where ';' should not have been replaced with '@'
';' does not always indicate the start of a comment, and commit
8cb6e17571f3fb66ccd4fa19f881602542cd06fc incorrectly replaced 3
instances of ';' with '@' in expected diagnostics, leading to tests
failures.

This patch restores the original ';' as needed in these testcases.

Fixes bug: https://sourceware.org/bugzilla/show_bug.cgi?id=29739
2022-11-02 17:58:53 +00:00
fde7c6bf64 sim: split CPPFLAGS between build & host
In order to merge more common/ files into the top-level, we need to
add more host flags to CPPFLAGS, and that conflicts with our current
use with build-time tools.  So split them apart like we do with all
other build flags to avoid the issue.
2022-11-02 20:59:14 +05:45
e4f2bc9c05 sim: h8300: switch to cpu for state
Rather than rely on pulling out the first cpu from the sim state
for cpu state, pass down the active cpu that's already available.
2022-11-02 20:57:20 +05:45
ee1cffd388 sim: common: change sim_{fetch,store}_register helpers to use void* buffers
When reading/writing arbitrary data to the system's memory, the unsigned
char pointer type doesn't make that much sense.  Switch it to void so we
align a bit with standard C library read/write functions, and to avoid
having to sprinkle casts everywhere.
2022-11-02 20:31:10 +05:45
26f228db71 Fix Cygwin build after 20489cca
Update code under __CYGWIN__ which accesses inferior process information
which is now stored in windows_process_info rather than globals.
2022-11-02 14:36:16 +00:00
559a5ea452 Fix Cygwin build after bcb9251f
Absent _UNICODE being defined (which gdb's Makefile doesn't do),
windows.h will always define STARTUPINFO is as STARTUPINFOA, so this
cast isn't correct when create_process expects a STARTUPINFOW
parameter (i.e. in a Cygwin build).

Instead write this as &info_ex.StartupInfo (which is always of the
correct type).
2022-11-02 14:36:14 +00:00
39a28a7cf2 x86: drop bogus Tbyte
Prior to commit 1cb0ab18ad24 ("x86/Intel: restrict suffix derivation")
the Tbyte modifier on the FLDT and FSTPT templates was pointless, as
No_ldSuf would have prevented it being accepted. Due to the special
nature of LONG_DOUBLE_MNEM_SUFFIX said commit, however, has led to these
insns being accepted in Intel syntax mode even when "tbyte ptr" was
present. Restore original behavior by dropping Tbyte there. (Note that
these insns in principle should by marked AT&T syntax only, but since
they haven't been so far we probably shouldn't change that.)
2022-11-02 08:21:04 +01:00
be1643ff05 x86: simplify expressions in update_imm()
Comparing the sum of the relevant .imm<N> fields against a constant imo
makes more obvious what is actually meant. It allows dropping of two
static variables, with a 3rd drop requiring two more minor adjustments
elsewhere, utilizing that "i" is zeroed first thing in md_assemble().
This also increases the chances of the compiler doing the calculations
all in registers.
2022-11-02 08:18:24 +01:00
d918451a04 RISC-V: Fixed the missing $x+arch when adding odd paddings for alignment.
Consider the case,

.option arch, rv32i
.option norelax
.option arch, +c
.byte   1
.align  2
addi    a0, zero, 1

Assembler adds $d for the odd .byte, and then adds $x+arch for the
alignment.  Since norelax, riscv_add_odd_padding_symbol will add the
$d and $x for the odd alignment, but accidently remove the $x+arch because
it has the same address as $d.  Therefore, we will get the unexpected result
before applying this patch,

.byte   1            # $d
.align  2            # odd alignment, $xrv32ic replaced by $d + $x

After this patch, the expected result should be,

.byte   1            # $d
.align  2            # odd alignment, $xrv32ic replaced by $d + $xrv32ic

gas/
    * config/tc-riscv.c (make_mapping_symbol): If we are adding mapping symbol
    for odd alignment, then we probably will remove the $x+arch by accidently
    when it has the same address of $d.  Try to add the removed $x+arch back
    after the $d rather than just $x.
    (riscv_mapping_state): Updated since parameters of make_mapping_symbol are
    changed.
    (riscv_add_odd_padding_symbol): Likewise.
    (riscv_remove_mapping_symbol): Removed and moved the code into the
    riscv_check_mapping_symbols.
    (riscv_check_mapping_symbols): Updated.
    * testsuite/gas/riscv/mapping-dis.d: Updated and added new testcase.
    * testsuite/gas/riscv/mapping-symbols.d: Likewise.
    * testsuite/gas/riscv/mapping.s: Likewise.
2022-11-02 13:00:27 +08:00
2188d6ea4f Support Intel MSRLIST
gas/ChangeLog:

	* NEWS: Support Intel MSRLIST.
	* config/tc-i386.c: Add msrlist.
	* doc/c-i386.texi: Document .msrlist.
	* testsuite/gas/i386/i386.exp: Add MSRLIST tests.
	* testsuite/gas/i386/msrlist-inval.l: New test.
	* testsuite/gas/i386/msrlist-inval.s: Ditto.
	* testsuite/gas/i386/x86-64-msrlist-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-msrlist.d: Ditto.
	* testsuite/gas/i386/x86-64-msrlist.s: Ditto.

opcodes/ChangeLog:

	* i386-dis.c (X86_64_0F01_REG_0_MOD_3_RM_6_P_1): New.
	(X86_64_0F01_REG_0_MOD_3_RM_6_P_3): Ditto.
	(prefix_table): New entry for msrlist.
	(x86_64_table): Add X86_64_0F01_REG_0_MOD_3_RM_6_P_1
	and X86_64_0F01_REG_0_MOD_3_RM_6_P_3.
	* i386-gen.c (cpu_flag_init): Add CPU_MSRLIST_FLAGS
	and CPU_ANY_MSRLIST_FLAGS.
	* i386-init.h: Regenerated.
	* i386-opc.h (CpuMSRLIST): New.
	(i386_cpu_flags): Add cpumsrlist.
	* i386-opc.tbl: Add MSRLIST instructions.
	* i386-tbl.h: Regenerated.
2022-11-02 09:19:26 +08:00
941f083324 Support Intel WRMSRNS
gas/ChangeLog:

        * NEWS: Support Intel WRMSRNS.
        * config/tc-i386.c: Add wrmsrns.
        * doc/c-i386.texi: Document .wrmsrns.
        * testsuite/gas/i386/i386.exp: Add WRMSRNS tests.
        * testsuite/gas/i386/wrmsrns-intel.d: New test.
        * testsuite/gas/i386/wrmsrns.d: Ditto.
        * testsuite/gas/i386/wrmsrns.s: Ditto.
        * testsuite/gas/i386/x86-64-wrmsrns-intel.d: Ditto.
        * testsuite/gas/i386/x86-64-wrmsrns.d: Ditto.

opcodes/ChangeLog:

	* i386-dis.c (PREFIX_0F01_REG_0_MOD_3_RM_6): New.
	(prefix_table): Add PREFIX_0F01_REG_0_MOD_3_RM_6.
	(rm_table): New entry for wrmsrns.
	* i386-gen.c (cpu_flag_init): Add CPU_WRMSRNS_FLAGS
	and CPU_ANY_WRMSRNS_FLAGS.
	(cpu_flags): Add CpuWRMSRNS.
        * i386-init.h: Regenerated.
        * i386-opc.h (CpuWRMSRNS): New.
	(i386_cpu_flags): Add cpuwrmsrns.
        * i386-opc.tbl: Add WRMSRNS instructions.
        * i386-tbl.h: Regenerated.
2022-11-02 09:19:24 +08:00