Warning without knowing what's going to follow isn't useful, the more
that appropriate warnings are emitted elsewhere in all cases. Not
updating state (file/line in particular) also isn't helpful, as it's
always the last directive ahead of a construct potentially needing
fiddling with that's "guilty" in that fiddling being suppressed.
.nop and .nops generate code, not data. Hence them invoking
md_cons_align() is at best inappropriate. In fact it actually gets in
the of x86'es state maintenance involving i386_cons_align().
Otherwise intermediate section switches result in inconsistent behavior.
Note, however, that intermediate sub-section switches will continue to
result in inconsistent or even inappropriate behavior.
While there also add recording of state to s_insn().
... as MSR index specifier: It is unreasonable to demand that people
write less readable / understandable code, just because the present
documentation mentions only Reg64. Whether to also adjust the
disassembler is a separate question, perhaps indeed more tightly tied
to what the spec says.
SiFive has define as set of flexible instruction for extending vector
coprocessor, it able to encoding opcode like .insn but with predefined
format.
List of instructions:
sf.vc.x
sf.vc.i
sf.vc.vv
sf.vc.xv
sf.vc.iv
sf.vc.fv
sf.vc.vvv
sf.vc.xvv
sf.vc.ivv
sf.vc.fvv
sf.vc.vvw
sf.vc.xvw
sf.vc.ivw
sf.vc.fvw
sf.vc.v.x
sf.vc.v.i
sf.vc.v.vv
sf.vc.v.xv
sf.vc.v.iv
sf.vc.v.fv
sf.vc.v.vvv
sf.vc.v.xvv
sf.vc.v.ivv
sf.vc.v.fvv
sf.vc.v.vvw
sf.vc.v.xvw
sf.vc.v.ivw
sf.vc.v.fvw
Spec of Xsfvcp
https://www.sifive.com/document-file/sifive-vector-coprocessor-interface-vcix-software
Co-authored-by: Hau Hsu <hau.hsu@sifive.com>
Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
Back then when the support for the RISC-V vector crypto extensions
was merged, the specification was frozen, but not ratified.
A frozen specification is allowed to change within tight bounds
before ratification and this has happend with the vector crypto
extensions.
The following changes were applied:
* A new extension Zvkb was defined, which is a strict subset of Zvbb.
* Zvkn and Zvks include now Zvkb instead of Zvbb.
This patch implements these changes between the frozen and the
ratified specification.
Note, that this technically an incompatible change of Zvkn and Zvks,
but I am not aware of any project that depends on the currently
implemented behaviour of Zvkn and Zvks. So this patch should be fine.
Reported-By: Jerry Shih <jerry.shih@sifive.com>
Reported-By: Eric Biggers <ebiggers@kernel.org>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
On MIPSr6, the encoding of JR instruction has been chaned.
This patch can fix these failures for r6 default triples:
ST Microelectronics Loongson-2F workarounds of Jump Instruction issue
This behavior is used by downstream toolchain since 2014,
and has been in GCC since the same year.
We don't support mips64*-img* due to GCC doesn't support it,
and we believe that the multilib should be used for this case.
This patch makes the BPF assembler to support double-slash line
comments, like the llvm BPF assembler does. At this point both
assemblers support the same commenting styles:
- Line comments preceded by # or //.
- Non-nestable block comments delimited by /* and */.
This patch also adds a couple of tests to make sure all the comment
styles work in both normal and pseudoc syntax. The manual is also
updated to mention double-slash line comments.
The BPF assembler in clang uses semi-colon (;) to separate statements,
not to be begin line comments. This patch adapts the GNU assembler
accordingly.
Testsuite and documentation updated accordingly.
2023-11-28 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-bpf.c: Semicolon does not start a comment, but
separates multiple commands on a single line.
* testsuite/gas/bpf/alu-pseudoc.s: Adapt test accordingly.
* testsuite/gas/bpf/spacing-pseudoc.s: Likewise.
* testsuite/gas/bpf/offset16-overflow.s: Likewise.
* testsuite/gas/bpf/jump-relax-jump.s: Likewise.
* testsuite/gas/bpf/jump-relax-ja.s: Likewise.
* testsuite/gas/bpf/imm32-overflow.s: Likewise.
* testsuite/gas/bpf/disp32-overflow.s: Likewise.
* testsuite/gas/bpf/disp16-overflow-relax.s: Likewise.
* testsuite/gas/bpf/disp16-overflow.s: Likewise.
* doc/c-bpf.texi (BPF Special Characters): Update.
Add extended mnemonics specified in the z/Architecture Principles of
Operation [1] and z/Architecture Reference Summary [2], that were
previously missing from the opcode table.
The following added extended mnemonics are synonyms to a base mnemonic
and therefore disassemble into their base mnemonic:
jc, jcth, lfi, llgfi, llghi
The following added extended mnemonics are more specific than their base
mnemonic and therefore disassemble into the added extended mnemonic:
risbhgz, risblgz, rnsbgt, rosbgt, rxsbgt
The following added extended mnemonics are more specific than their base
mnemonic, but disassemble into their base mnemonic due to design
constraints:
notr, notgr
The missing extended mnemonic jl* conditional jump long flavors cannot
be added, as they would clash with the existing non-standard extended
mnemonic j* conditional jump flavors jle and jlh. The missing extended
mnemonic jlc jump long conditional is not added, as the related jl*
flavors cannot be added.
Note that these missing jl* conditional jump long flavors are already
defined as non-standard jg* flavors instead. While the related missing
extended mnemonic jlc could be added as non-standard jgc instead it is
forgone in favor of not adding further non-standard mnemonics.
The missing extended mnemonics sllhh, sllhl, slllh, srlhh, srlhl, and
srllh cannot be implemented using the current design, as they require
computed operands. For that reason the following missing extended
mnemonics are not added as well, as they fall into the same category of
instructions that operate on high and low words of registers. They
should better be added together, not to confuse the user, which of those
instructions are currently implemented or not.
lhhr, lhlr, llhfr, llchhr, llchlr, llclhr, llhhhr, llhhlr, llhlhr,
nhhr, nhlr, nlhr, ohhr, ohlr, olhr, xhhr, xhlr, xlhr
[1] IBM z/Architecture Principles of Operation, SA22-7832-13, IBM z16,
https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf
[2] IBM z/Architecture Reference Summary, SA22-7871-11,
https://www.ibm.com/support/pages/sites/default/files/2022-09/SA22-7871-11.pdf
opcodes/
* s390-opc.c: Define operand formats R_CP16_28, U6_18, and
U5_27. Define instruction formats RIE_RRUUU3, RIE_RRUUU4,
and RRF_R0RR4.
* s390-opc.txt: Add extended mnemonics jc, jcth, lfi, llgfi,
llghi, notgr, notr, risbhgz, risblgz, rnsbgt, rosbgt, and
rxsbgt.
gas/
* config/tc-s390.c: Add support to insert operand for format
R_CP16_28, reusing existing logic for format V_CP16_12.
* testsuite/gas/s390/esa-g5.s: Add test for extended mnemonic
jc.
* testsuite/gas/s390/esa-g5.d: Likewise.
* testsuite/gas/s390/zarch-z900.s: Add test for extended
mnemonic llghi.
* testsuite/gas/s390/zarch-z900.d: Likewise.
* testsuite/gas/s390/zarch-z9-109.s: Add tests for extended
mnemonics lfi and llgfi.
* testsuite/gas/s390/zarch-z9-109.d: Likewise.
* testsuite/gas/s390/zarch-z10.s: Add tests for extended
mnemonics rnsbgt, rosbgt, and rxsbgt.
* testsuite/gas/s390/zarch-z10.d: Likewise.
* testsuite/gas/s390/zarch-z196.s: Add tests for extended
mnemonics jcth, risbhgz, and risblgz.
* testsuite/gas/s390/zarch-z196.d: Likewise.
* testsuite/gas/s390/zarch-arch13.s: Add tests for extended
mnemonics notr and notgr.
* testsuite/gas/s390/zarch-arch13.d: Likewise.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
The IBM z/Architecture Principle of Operation [1] specifies the last
operand(s) of some (extended) mnemonics to be optional. Align the
mnemonic definitions in the opcode table according to specification.
This changes the last operand of the following (extended) mnemonics to
be optional:
risbg, risbgz, risbgn, risbgnz, risbhg, risblg, rnsbg, rosbg, rxsbg
Note that efpc and sfpc actually have only one operand, but had
erroneously been defined to have two. For backwards compatibility the
wrong RR register format must be retained. Since the superfluous second
operand is defined as optional the instruction can still be coded as
specified.
[1]: IBM z/Architecture Principles of Operation, SA22-7832-13, IBM z16,
https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf
opcodes/
* s390-opc.txt: Align optional operand definition to
specification.
testsuite/
* zarch-z10.s: Add test cases for risbg, risbgz, rnsbg, rosbg,
and rxsbg.
* zarch-z10.d: Likewise.
* zarch-z196.s: Add test cases for risbhg and risblg.
* zarch-z196.d: Likewise.
* zarch-zEC12.s: Add test cases for risbgn and risbgnz.
* zarch-zEC12.d: Likewise.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
The ESA opcode test cases for IBM z900 contain a few edge cases. They
exercise the brasl mnemonic with its largest allowed negative and
positive offsets. Linux on zSeries in ESA mode executes in 31-bit
addressing mode. Therefore the ESA test cases are assembled with -m31.
In 31-bit addressing mode the address computation using those large
offsets wraps, which is correctly reflected in the disassembly.
Linux on Z in z/Architecture mode executes in 64-bit addressing mode.
Therefore the z/Architecture (zarch) test cases are assembled with -m64.
In 64-bit addressing mode the address computation using those large
offsets does not necessarily wrap.
gas/
* testsuite/gas/s390/zarch-z900.s: Add brasl tests from ESA that
exercise edge cases.
* testsuite/gas/s390/zarch-z900.d: Likewise.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
Opcode test cases for z/Architecture instructions that use relative
addressing contained hardcoded offsets in the test verification
patterns. Inserting or reordering of instructions into those test cases
therefore required updating of those hardcoded offsets.
Use regular expressions with backreferences to verify results of test
cases containing instructions with relative addressing. This makes the
verification position independent.
gas/
* testsuite/gas/s390/esa-g5.d: Make opcode test verification
pattern position independent where possible.
* testsuite/gas/s390/esa-z900.d: Likewise.
* testsuite/gas/s390/zarch-z900.d: Likewise.
* testsuite/gas/s390/zarch-z10.d: Likewise.
* testsuite/gas/s390/zarch-z196.d: Likewise.
* testsuite/gas/s390/zarch-zEC12.d: Likewise.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.
This patch adds permutation instructions for the "XTheadVector"
extension. The 'th' prefix and the "XTheadVector" extension
are documented in a PR for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>
gas/ChangeLog:
* testsuite/gas/riscv/x-thead-vector.d: Add tests for
permutation instructions.
* testsuite/gas/riscv/x-thead-vector.s: Likewise.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_TH_VMVXS): New.
opcodes/ChangeLog:
* riscv-opc.c: Likewise.
T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.
This patch adds mask instructions for the "XTheadVector"
extension. The 'th' prefix and the "XTheadVector" extension
are documented in a PR for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>
gas/ChangeLog:
* testsuite/gas/riscv/x-thead-vector.d: Add tests for
mask instructions.
* testsuite/gas/riscv/x-thead-vector.s: Likewise.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_TH_VMPOPCM): New.
opcodes/ChangeLog:
* riscv-opc.c: Likewise.
T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.
This patch adds reductions instructions for the "XTheadVector"
extension. The 'th' prefix and the "XTheadVector" extension
are documented in a PR for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>
gas/ChangeLog:
* testsuite/gas/riscv/x-thead-vector.d: Add tests for
reductions instructions.
* testsuite/gas/riscv/x-thead-vector.s: Likewise.
opcodes/ChangeLog:
* riscv-opc.c: Likewise.
T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.
This patch adds floating-point arithmetic instructions for the
"XTheadVector" extension. The 'th' prefix and the
"XTheadVector" extension are documented in a PR for the
RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>
gas/ChangeLog:
* testsuite/gas/riscv/x-thead-vector.d: Add tests for
floating-point arithmetic instructions.
* testsuite/gas/riscv/x-thead-vector.s: Likewise.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_TH_VFSQRTV): New.
opcodes/ChangeLog:
* riscv-opc.c: Likewise.
T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.
This patch adds fixed-point arithmetic instructions for the
"XTheadVector" extension. The 'th' prefix and the
"XTheadVector" extension are documented in a PR for the
RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>
gas/ChangeLog:
* testsuite/gas/riscv/x-thead-vector.d: Add tests for
fixed-point arithmetic instructions.
* testsuite/gas/riscv/x-thead-vector.s: Likewise.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_TH_VAADDVV): New.
opcodes/ChangeLog:
* riscv-opc.c: Likewise.
T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.
This patch adds integer arithmetic instructions for the
"XTheadVector" extension. The 'th' prefix and the
"XTheadVector" extension are documented in a PR for the
RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>
gas/ChangeLog:
* testsuite/gas/riscv/x-thead-vector.d: Add tests for
integer arithmetic instructions.
* testsuite/gas/riscv/x-thead-vector.s: Likewise.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_TH_VADCVVM): New.
opcodes/ChangeLog:
* riscv-opc.c: Likewise.
T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.
This patch adds the sub-extension "XTheadZvamo" for the
"XTheadVector" extension, and it provides AMO instructions
for T-Head VECTOR vendor extension. The 'th' prefix and the
"XTheadVector" extension are documented in a PR for the
RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add support
for "XTheadZvamo" extension.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* doc/c-riscv.texi:
* testsuite/gas/riscv/x-thead-vector-zvamo.d: New test.
* testsuite/gas/riscv/x-thead-vector-zvamo.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_TH_VAMOADDWV): New.
* opcode/riscv.h (enum riscv_insn_class): Add insn class.
opcodes/ChangeLog:
* riscv-opc.c: Likewise.
T-Head has a range of vendor-specific instructions. Therefore it
makes sense to group them into smaller chunks in form of vendor
extensions.
This patch adds provides load/store segment instructions for T-Head VECTOR
vendor extension, which same as the "Zvlsseg" extension in RVI 0.71 vector
extension, but belongs to the "XTheadVector" extension. The 'th' prefix
and the "XTheadVector" extension are documented in a PR for the
RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>
gas/ChangeLog:
* testsuite/gas/riscv/x-thead-vector.d: Add test.
* testsuite/gas/riscv/x-thead-vector.s: Likewise.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_TH_VLSEG2BV): New.
opcodes/ChangeLog:
* riscv-opc.c: Likewise.
T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.
This patch adds load/store instructions for the "XTheadVector"
extension. The 'th' prefix and the "XTheadVector" extension are
documented in a PR for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>
gas/ChangeLog:
* testsuite/gas/riscv/x-thead-vector.d: Add tests for
load/store instructions.
* testsuite/gas/riscv/x-thead-vector.s: Likewise.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_TH_VLBV): New.
opcodes/ChangeLog:
* riscv-opc.c: Likewise.
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds configuration-setting instructions for the "XTheadVector"
extension. The 'th' prefix and the "XTheadVector" extension are documented
in a PR for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>
gas/ChangeLog:
* testsuite/gas/riscv/x-thead-vector.d: New test.
* testsuite/gas/riscv/x-thead-vector.s: New test.
opcodes/ChangeLog:
* riscv-opc.c: Likewise..
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the CSRs for XTheadVector. Because of the
conflict between encoding and teh 'V' extension, it is implemented
by alias. The 'th' prefix and the "XTheadVector" extension are
documented in a PR for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>
gas/ChangeLog:
* config/tc-riscv.c (enum riscv_csr_class): Add the class for
the CSRs of the "XTheadVector" extension.
(riscv_csr_address): Likewise.
* testsuite/gas/riscv/x-thead-vector-csr-warn.d: New test.
* testsuite/gas/riscv/x-thead-vector-csr-warn.l: New test.
* testsuite/gas/riscv/x-thead-vector-csr.d: New test.
* testsuite/gas/riscv/x-thead-vector-csr.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (DECLARE_CSR_ALIAS): Likewise.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Prefix the CSRs disassembly with 'th'.
T-Head has a range of vendor-specific instructions ([2]).
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the "XTheadVector" extension, a collection of
T-Head-specific vector instructions. The 'th' prefix and the
"XTheadVector" extension are documented in a PR for the RISC-V
toolchain conventions ([1]).
Here are some things that need to be explained:
The "XTheadVector" extension is not a custom-extension, but
a non-standard non-conforming extension. The encoding space
of the "TheadVector" instructions overlaps with those of
the 'V' extension. This encoding space conflict is not on
purpose, but the result of issues in the past that have
been resolved since. Therefore, the "XTheadVector" extension
and the 'V' extension are in conflict.
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
[2] https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_parse_check_conflicts): The
"XTheadVector" extension and the 'V' extension are in conflict.
(riscv_multi_subset_supports): Likewise..
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* doc/c-riscv.texi:
* testsuite/gas/riscv/x-thead-vector-fail.d: New test.
* testsuite/gas/riscv/x-thead-vector-fail.l: New test.
* testsuite/gas/riscv/x-thead-vector.s: New test.
include/ChangeLog:
* opcode/riscv.h (enum riscv_insn_class):
This changes parse_bpf_register to detect possible symbols that start with valid
register name, however due some following characters are not.
Also changed the regs-for-symbols-pseudo.s, adding some entries that
should not error if parser is properly detecting the symbol.
2023-11-18 Jose E. Marchesi <jemarch@gnu.org>
* config/tc-bpf.c (parse_bpf_register): Move before
bpf_parse_name.
(bpf_parse_name): Do not allow using symbols that are also
register names as operands in pseudo-c syntax.
* testsuite/gas/bpf/regs-for-symbols-pseudoc.d: New file.
* testsuite/gas/bpf/regs-for-symbols-pseudoc.s: Likewise.
* testsuite/gas/bpf/regs-for-symbols-pseudoc.l: Likewise.
* doc/c-bpf.texi (BPF Registers): Document that it is not possible
to refer to register names as symbols in instruction operands.
To support the "pseudo-C" asm dialect in BPF, the BPF parser must often
attempt multiple different templates for a single instruction. In some
cases this can cause the parser to incorrectly parse part of the
instruction opcode as an expression, which leads to the creation of a
new undefined symbol.
Once the parser recognizes the error, the expression is discarded and it
tries again with a new instruction template. However, symbols created
during the process are added to the symbol table and are not removed
even if the expression is discarded.
This is a problem for BPF: generally the assembled object will be loaded
directly to the Linux kernel, without being linked. These erroneous
parser-created symbols are rejected by the kernel BPF loader, and the
entire object is refused.
This patch remedies the issue by tentatively creating symbols while
parsing instruction operands, and storing them in a temporary list
rather than immediately inserting them into the symbol table. Later,
after the parser is sure that it has correctly parsed the instruction,
those symbols are committed to the real symbol table.
This approach is modeled directly after Jan Beulich's patch for RISC-V:
commit 7a29ee2903
RISC-V: adjust logic to avoid register name symbols
Many thanks to Jan for recognizing the problem as similar, and pointing
me to that patch.
gas/
* config/tc-bpf.c (parsing_insn_operands): New.
(parse_expression): Set it here.
(deferred_sym_rootP, deferred_sym_lastP): New.
(orphan_sym_rootP, orphan_sym_lastP): New.
(bpf_parse_name): New.
(parse_error): Clear deferred symbol list on error.
(md_assemble): Clear parsing_insn_operands. Commit deferred
symbols to symbol table on successful parse.
* config/tc-bpf.h (md_parse_name): Define to...
(bpf_parse_name): ...this. New prototype.
* testsuite/gas/bpf/asm-extra-sym-1.s: New test source.
* testsuite/gas/bpf/asm-extra-sym-1.d: New test.
* testsuite/gas/bpf/bpf.exp: Run new test.
PR gas/31043
"unsupported instruction ..." can mean about anything, and can also be
mistaken to mean something that isn't meant. Replace most of its uses by
more specific diagnostics,
While there also take the opportunity and purge the no longer used
invalid_register_operand enumerator.
{disp16} is invalid to use in 64-bit mode, while {disp32} is invalid to
use on pre-386 CPUs. The latter, also affecting other (real) prefixes,
further requires that like for insns we fully check the CPU flags; till
now only Cpu64/CpuNo64 were taken into consideration.
Due to a missing check "crc32q %al, %rax" was wrongly translated to the
encoding of "crc32q %rax, %rax", rather than being rejected as invalid.
(The mnemonic suffix describes the source operand, not the destination
one.)
Note that check_{word,long}_reg() do not (currently) appear to require
similar amending, as there are no insn templates permitting an L or W
suffix and having an operand which allows for Reg8 and Reg64, but
neither Reg16 nor Reg32.
This patch adds the permission model enhancement and memory
attribute index enhancement features and their corresponding
system registers in AArch64 assembler.
Permission Indirection Extension (FEAT_S1PIE, FEAT_S2PIE)
Permission Overlay Extension (FEAT_S1POE, FEAT_S2POE)
Memory Attribute Index Enhancement (FEAT_AIE)
Extension to Translation Control Registers (FEAT_TCR2)
These features are available by default from Armv9.4-A architecture.
This patch also adds support for:
1. FEAT_RASv2 feature and "ERXGSR_EL1" system register.
RASv2 feature is enabled by passing +rasv2 to -march
(eg: -march=armv8-a+rasv2).
2. FEAT_SCTLR2 and following system registers.
SCTLR2_EL1, SCTLR2_EL12, SCTLR2_EL2 and SCTLR2_EL3.
3. FEAT_FGT2 and following system registers.
HDFGRTR2_EL2, HDFGWTR2_EL2, HFGRTR2_EL2, HFGWTR2_EL2
4. FEAT_PFAR and following system registers.
PFAR_EL1, PFAR_EL2 and PFAR_EL12.
FEAT_RASv2, FEAT_SCTLR2, FEAT_FGT2 and FEAT_PFAR features are by default
enabled from Armv9.4-A architecture.
This patch also adds support for two read only system registers
id_aa64mmfr3_el1 and id_aa64mmfr4_el1, which are available from
Armv8-A Architecture.
This patch adds features to the Statistical Profiling Extension,
identified as FEAT_SPEv1p4, FEAT_SPE_FDS, and FEAT_SPE_CRR, which
are enabled by default from Armv9.4-A.
Also adds support for system register "pmsdsfr_el1".
* testsuite/gas/elf/elf.exp (section2): Add -mpdr option to assembler command line for mips-irix targets.
* testsuite/gas/mips/elf-rel26.d: Add -mpdr command line option.
* testsuite/gas/mips/mips16-e.d: Likewise.
* testsuite/gas/mips/mips16-f.d: Likewise.
* testsuite/gas/mips/mips16-hilo-match.d: Likewise.
* testsuite/gas/mips/mips16-e-irix.d: Likewise.
* testsuite/gas/mips/call-nonpic-1.d: Adjust regexp to allow for mips-irix targets.
* testsuite/gas/mips/irix-no-pdr.d: New test file.
* testsuite/gas/mips/mips.exp: Run new test for mips-irix targets.
The erroneous omission of a "reg_value == " in the THE system register
encoding check added in [1] led to an error which was not picked up in
GCC but which was flagged in Clang due to its use of
[-Werror,-Wconstant-logical-operand] check. Together with this fix we
add a new test for the THE registers to pick up their illegal use,
adding an extra and important layer of validation.
Furthermore, in separating system register from instruction
implementation (with which only the former was of concern in the cited
patch), additions made to `aarch64-tbl.h' are rolled back so
that these can be added later when adding THE instructions to the
codebase, a more natural place for these changes.
[1] https://sourceware.org/pipermail/binutils/2023-November/130314.html
opcodes/ChangeLog:
* aarch64-opc.c (aarch64_sys_ins_reg_supported_p): Fix typo.
* aarch64-tbl.h (THE): Remove.
(aarch64_feature_set aarch64_feature_the): Likewise.
gas/ChangeLog:
* testsuite/gas/aarch64/illegal-sysreg-8.l: Add tests for THE
system registers.
* testsuite/gas/aarch64/illegal-sysreg-8.s: Likewise.
