2 Commits

Author	SHA1	Message	Date
Mike Frysinger	d5a71b1131	sim: cgen: move cgen_cpu_max_extra_bytes logic into the common code ... Every arch handles this the same way, so move it to the common code. This will also make unifying the sim_cpu structure easier.	2021-04-12 00:14:32 -04:00
Mike Frysinger	26da232cbd	sim: example-synacor: a simple implementation for reference ... Provide a simple example simulator for people porting to new targets to use as a reference. This one has the advantage of being used by people and having a fun program available for it. It doesn't require a special target -- the example simulators can be built for any existing port.	2021-04-03 16:19:16 -04:00