92 Commits

Author SHA1 Message Date
4cd7de783b sim: formally assume unistd.h always exists (via gnulib)
We have many uses of unistd.h that are unprotected by HAVE_UNISTD_H,
so this is more formalizing the reality that we require this header.
Since we switched to gnulib, it guarantees that a unistd.h exists
for us to include, so we're doubly OK.
2023-01-16 04:35:48 -05:00
8290c8b5dd sim: v850: fix SMP compile
The igen tool sets up the SD & CPU defines for code fragments to use,
but v850 was expecting "sd".  Change all the igen related code to use
SD so it actually compiles, and fix a few places to use "CPU" instead
of hardcoding cpu0.
2022-12-25 02:10:22 -05:00
f625c714c2 sim: v850: standardize the arch-specific settings a little
Rename v850_sim.h to v850-sim.h to match other ports, and move most
of the arch-specific content out of sim-main.h to it.  This isn't a
big win though as we still have to include the header in sim-main.h
due to the igen interface: it hardcodes including sim-main.h in its
files.  So until we can fix that, we have to keep bleeding these
settings into the common codes.
2022-12-23 08:32:58 -05:00
ae0faac067 sim: v850: switch from SIM_ADDR to address_word
The latter type matches the address size configured for this sim.
2022-12-22 19:46:36 -05:00
b830591caf sim: v850: switch to standard (high-level) trace defines
The v850 port uses -DDEBUG to control whether to enable internal tracing.
We already have such options via the common trace framework, and those
can be controlled at build time via configure flags (which the v850 code
currently cannot).  So switch it over to WITH_TRACE_ANY_P to simplify the
v850 build code even if it doesn't (yet) respect any other trace options.
2022-11-03 22:21:04 +07:00
5b94c38081 sim: common: change sim_read & sim_write to use void* buffers
When reading/writing arbitrary data to the system's memory, the unsigned
char pointer type doesn't make that much sense.  Switch it to void so we
align a bit with standard C library read/write functions, and to avoid
having to sprinkle casts everywhere.
2022-10-31 21:24:39 +05:45
477904ca75 Fix for v850e divq instruction
This is the last of the correctness fixes I've been carrying around for the
v850.

Like the other recent fixes, this is another case where we haven't been as
careful as we should WRT host vs target types.   For the divq instruction
both operands are 32 bit types.  Yet in the simulator code we convert them
from unsigned int to signed long by assignment.  So 0xfffffffb (aka -5)
turns into 4294967291 and naturally that changes the result of our division.

The fix is simple, insert a cast to int32_t to force interpretation as a
signed value.

Testcase for the simulator is included.  It has a trivial dependency on the
bins patch.
2022-04-06 11:10:40 -04:00
49fffa58f7 Fix "bins" simulation for v850e3v5
I've been carrying this for a few years.   One test in the GCC testsuite is
failing due to a bug in the handling of the v850e3v5 instruction "bins".

When the "bins" instruction specifies a 32bit bitfield size, the simulator
exhibits undefined behavior by trying to shift a 32 bit quantity by 32 bits.
In the case of a 32 bit shift, we know what the resultant mask should be.  So
we can just set it.

That seemed better than using 1UL for the constant (on a 32bit host unsigned
long might still just be 32 bits) or needlessly forcing everything to
long long types.

Thankfully the case where this shows up is only bins <src>, 0, 32, <dest>
which would normally be encoded as a simple move.

	* testsuite/v850/allinsns.exp: Add v850e3v5.
	* testsuite/v850/bins.cgs: New test.
	* v850/simops.c (v850_bins): Avoid undefined behavior on left shift.
2022-04-06 11:06:53 -04:00
5321c31bc7 Fix for MUL instruction on the v850
* sim/v850/simops.c (Multiply64): Properly test if we need to
	negate either of the operands.

	* sim/testsuite/v850/mul.cgs: New test.
2022-03-29 20:08:35 -04:00
436c3d9d7b sim: v850: migrate to standard uintXX_t types
This old port setup its own uintXX types, but since we require C11
now, we can assume the standard uintXX_t types exist and use them.
2022-01-06 01:17:37 -05:00
96b1eb7e17 sim: v850: switch to new target-newlib-syscall
Use the new target-newlib-syscall module.  This is needed to merge all
the architectures into a single build, and v850 has a custom syscall
table for its newlib/libgloss port.

This allows cleaning up the syscall ifdef logic.  We know these will
always exist now.
2021-11-28 13:23:58 -05:00
1fef66b0dc sim: split sim-signal.h include out
The sim-basics.h is too big and includes too many things.  This leads
to some arch's sim-main.h having circular loop issues with defs, and
makes it hard to separate out common objects from arch-specific defs.
By splitting up sim-basics.h and killing off sim-main.h, it'll make
it easier to separate out the two.
2021-06-18 00:50:14 -04:00
c469a50252 sim: v850: assume chown is available
Now that gnulib provides a wrapper, assume it always exists.
2021-06-08 00:15:56 -04:00
1f8ef36f75 sim: v850: add pointer casts for execv on Windows
The execv prototypes on Windows via mingw64 include extra const
markings on the argv/envp pointers than what POSIX specifies.
Cast them to void* as a hack to get it working on all platforms.
2021-05-29 15:32:59 -04:00
6df01ab8ab sim: switch config.h usage to defs.h
The defs.h header will take care of including the various config.h
headers.  For now, it's just config.h, but we'll add more when we
integrate gnulib in.

This header should be used instead of config.h, and should be the
first include in every .c file.  We won't rely on the old behavior
where we expected files to include the port's sim-main.h which then
includes the common sim-basics.h which then includes config.h.  We
have a ton of code that includes things before sim-main.h, and it
sometimes needs to be that way.  Creating a dedicated header avoids
the ordering mess and implicit inclusion that shows up otherwise.
2021-05-16 22:38:41 -04:00
5f05936d9b sim: v850: cleanup build warnings
This port only had one minor warning left in it, so fix it and then
enable -Werror behavior by deleting the macro call.  We'll use the
common default now (which is -Werror).
2021-01-31 15:19:16 -05:00
44b30b7f0e sim: v850: fix handling of SYS_times
My recent rewrite of the nltvals generator fixed a bug where SYS_times
was not being exported for v850.  But that in turn uncovered this bug
where the SYS_times codepath had a compile error.
2021-01-31 15:15:33 -05:00
68ed285428 sim: clean up C11 header includes
Since we require C11 now, we can assume many headers exist, and
clean up all of the conditional includes.  It's not like any of
this code actually accounted for the headers not existing, just
whether we could include them.

The strings.h cleanup is a little nuanced: it isn't in C11, but
every use of it in the codebase will include strings.h only if
string.h doesn't exist.  Since we now assume the C11 string.h
exists, we'll never include strings.h, so we can delete it.
2021-01-11 08:05:54 -05:00
1d19cae752 Fix invalid left shift of negative value
Fix occurrences of left-shifting negative constants in C code.

sim/arm/ChangeLog:

	* thumbemu.c (handle_T2_insn): Fix left shift of negative value.
	* armemu.c (handle_v6_insn): Likewise.

sim/avr/ChangeLog:

	* interp.c (sign_ext): Fix left shift of negative value.

sim/mips/ChangeLog:

	* micromips.igen (process_isa_mode): Fix left shift of negative
	value.

sim/msp430/ChangeLog:

	* msp430-sim.c (get_op, put_op): Fix left shift of negative value.

sim/v850/ChangeLog:

	* simops.c (v850_bins): Fix left shift of negative value.
2015-12-15 14:09:14 +01:00
a3976a7c56 Fixes problems building the V850 simulator introduced with the previous delta.
* sim-main.h (reg64_t): New type.
	(v850_regs): Add selID_sregs field.
	(VR, SAT16, SAT32, ABS16, ABS32 ): New macros.
	* v850-dc: Add fields for v850e3v5 instructions.
	* v850.igen (cvtf.dl): Use correctly signed local value.
	(cvtf.dw, cvtf.sw, trncf.dul, trncf.dl, trncf.sul, trncf.sw):
	Likewise.
	* interp.c: Fix old style function declarations.
	* simops.c: Likewise.
2015-02-27 09:53:03 +00:00
67d7515b0a * simops.c (v850_rotl): New function.
(v850_bins): New function.
	* simops.h: Add prototypes fir v850_rotl and v850_bins.
	* v850-dc: Add entries for V850e3v5.
	* v850.igen: Add support for v850e3v5.
	(ld.dw, st.dw, rotl, bins): New patterns.
2013-01-28 10:06:51 +00:00
2aaed97917 Commit gdb and sim support for v850e2 and v850e2v3 on behalf of
Rathish C <Rathish.C@kpitcummins.com>.
2012-03-29 00:57:19 +00:00
d0f0baa272 * simops (OP_10007E0): Update errno handling as most traps
do not invoke the host's functionality directly.  Invoke
	sim_io_stat() instead of stat() for implementing TARGET_SYS_stat.
	Implement TARGET_SYS_fstat, TARGET_SYS_rename, and TARGET_SYS_unlink.
2011-03-21 22:05:56 +00:00
d79fe0d643 sim: punt zfree()
The sim keeps track of which allocations are zero-ed internally (via
zalloc) and then calls a helper "zfree" function rather than "free".
But this "zfree" function simply calls "free" itself.  Since I can
see no point in this and it is simply useless overhead, punt it.

The only real change is in hw-alloc.c where we remove the zalloc_p
tracking, and sim-utils.c where zfree is delete.  The rest of the
changes are a simple `sed` from "zfree" to "free".

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-02-14 05:14:28 +00:00
98e460c30d * simops.c (OP_1C007E0): Compensate for 64 bit hosts.
(OP_18007E0): Likewise.
(OP_2C007E0): Likewise.
(OP_28007E0): Likewise.
* v850.igen (divh): Likewise.
2008-02-06 04:41:26 +00:00
c5fbc25baf Index: ChangeLog
* configure.ac (v850): V850 now has a testsuite.
	* configure (v850): Likewise.

Index: testsuite/ChangeLog

	* sim/v850/: New directory.
	* sim/v850/allinsns.exp: New.
	* sim/v850/bsh.cgs: New.
	* sim/v850/div.cgs: New.
	* sim/v850/divh.cgs: New.
	* sim/v850/divh_3.cgs: New.
	* sim/v850/divhu.cgs: New.
	* sim/v850/divu.cgs: New.
	* sim/v850/sar.cgs: New.
	* sim/v850/satadd.cgs: New.
	* sim/v850/satsub.cgs: New.
	* sim/v850/satsubi.cgs: New.
	* sim/v850/satsubr.cgs: New.
	* sim/v850/shl.cgs: New.
	* sim/v850/shr.cgs: New.
	* sim/v850/testutils.cgs: New.
	* sim/v850/testutils.inc: New.

Index: v850/ChangeLog

	* simops.c (OP_C0): Correct saturation logic.
	(OP_220): Likewise.
	(OP_A0): Likewise.
	(OP_660): Likewise.
	(OP_80): Likewise.

	* simops.c (OP_2A0): If the shift count is zero, clear the
	carry.
	(OP_A007E0): Likewise.
	(OP_2C0): Likewise.
	(OP_C007E0): Likewise.
	(OP_280): Likewise.
	(OP_8007E0): Likewise.

	* simops.c (OP_2C207E0): Correct PSW flags for special divu
	conditions.
	(OP_2C007E0): Likewise, for div.
	(OP_28207E0): Likewise, for divhu.
	(OP_28007E0): Likewise, for divh.  Also, sign-extend the correct
	operand.
	* v850.igen (divh): Likewise, for 2-op divh.

	* v850.igen (bsh): Fix carry logic.
2008-02-06 00:40:05 +00:00
4389ce38f0 * simops.c: Include <sys/types.h>. 2004-01-18 14:56:40 +00:00
ebc115b7bb * simops.c (OP_40): Delete. Move code to...
* v850-igen.c (): ...Here. Sign extend the first operand.
* simops.h (OP_40): Remove prototype.
2003-04-06 08:51:04 +00:00
0da2b66558 2002-11-30 Andrew Cagney <cagney@redhat.com>
* simops.c: Use int, 1, 0 instead of boolean, true and false.
	* sim-main.h: Ditto.
2002-11-30 18:01:30 +00:00
30458d39d6 Fix handling of v850e bit-twiddle instructions.
* simops.c (OP_E6077E0): And op1 with 7 after reading register, not
	before.
	(BIT_CHANGE_OP): Likewise.
2002-09-30 20:11:08 +00:00
2e8162cedb Fix bug in support for trap instruction.
* simops (OP_10007E0): Don't subtract 4 from PC.
2002-09-27 18:59:08 +00:00
e551c2572e Makefile.in: Add gen-zero-r0 option.
sim-main.h (GPR_SET, GPR_CLEAR): Define.
simops.c (OP_24007E0):  Sign extend the imm9 operand of a mul instruction.
2002-08-29 16:59:20 +00:00
d62274a397 * simops.c (trace_result): Fix printf formatting. 2002-06-17 21:49:05 +00:00
c906108c21 Initial creation of sourceware repository 1999-04-16 01:35:26 +00:00
071ea11e85 Initial creation of sourceware repository 1999-04-16 01:34:07 +00:00
a276b6f057 Clean up tracing for Bcond & jmp insns.
Fix computation of disp16 and disp22.
Clean up tracing of sld* insns.
1997-09-19 06:39:21 +00:00
bd4c35cc6d Fix cmov immed. 1997-09-19 02:20:02 +00:00
60fe0e06a8 Fix cmov insn. 1997-09-19 00:50:19 +00:00
a72f8fb439 Clean up more tracing.
FIX interrupt delivery - was zapping PSW before it had been saved.
FIX interrupt return, was one instruction out.
1997-09-17 08:14:23 +00:00
6aead89a5f Fix tracing for: "ctret", "bsw", "hsw"
Fix bugs in: "bsh", "callt", "stsr".
1997-09-17 05:31:00 +00:00
fb1fd47514 Smooth some of ALU tracing's rough edges.
Fix switch insn.
1997-09-16 14:00:15 +00:00
3f33acd039 Use trace_one_insn in trace functions. Buffer up trace data so that
it is displayed in a single block.
1997-09-16 07:03:41 +00:00
c7db488f71 Restrict ldsr (load system register) to modifying just non-reserved PSW bits.
For v850eq, include PSW[US] in bits that can be modified.
1997-09-16 04:49:24 +00:00
5262de2167 * simops.c (Multiply64): Don't store into register zero. 1997-09-16 01:45:23 +00:00
bda6163995 Fix sanitization for v850 V v850e V v850eq 1997-09-15 14:42:51 +00:00
658303f7d4 For v850eq start up with US bit set.
Let sim_analyze_program determine the architecture.
Fix various sanitizations.
1997-09-15 08:18:20 +00:00
02508bb179 Have trace_input, trace_output use sim-trace for IO. 1997-09-10 05:40:04 +00:00
5d37a07bc5 Add multi-sim support to v850/v850e/v850eq simulators. 1997-09-08 17:42:48 +00:00
da3a66e5ca Replace memory model with one from sim/common directory. 1997-09-04 10:10:02 +00:00
b5e935ae85 Pacify gcc-current -Wall. 1997-09-03 07:30:17 +00:00