59 Commits

Author SHA1 Message Date
dc5a462160 sim: sh: rework carry checks to not rely on integer overflows
In <=gcc-7 versions, -fstrict-overflow is enabled by default, and that
triggers warnings in this code that relies on integer overflows to test
for carries.  Change the logic to test against the limit directly.
2021-11-13 00:57:00 -05:00
524d770c9c sim: sh: fix uninitialized variable usage with pdmsb
This block of code relies on i to control which bits to test and how
many times to run through the loop, but it never actually initialized
it.  There is another chunk of code that handles the pdmsb instruction
that sets i to 16, so use that here too assuming it's correct.  The
programming manual suggests this is the right value too, but I am by
no means a SuperH DSP expert.  The tests are still passing though ...
2021-11-06 20:32:31 -04:00
ee7af46230 sim: sh: constify a few read-only lookup tables 2021-11-06 20:32:31 -04:00
6b015f8977 sim: sh: fix various parentheses warnings
Add parentheses to a bunch of places where the compiler suggests we
do to avoid confusion to most readers.
2021-11-06 20:32:31 -04:00
7256320b95 sim: sh: fix unused-value warnings
These macro expansions are deliberate in not using the computed value
so that they trigger side-effects (possible invalid memory accesses)
but while otherwise being noops.  Add a (void) cast so the compiler
knows these are intentional.
2021-11-06 20:32:31 -04:00
74bbe64132 sim: sh: rework register layout with anonymous unions & structs
Now that we require C11, we can leverage anonymous unions & structs
to fix a long standing issue with the SH register layout.  The use
of sregs.i for sh-dsp has generated a lot of compiler warnings about
the access being out of bounds -- it only has 7 elements declared,
but code goes beyond that to reach into the fregs that follow.  But
now that we have anonymous unions, we can reduce the nested names
and have sregs cover all of these registers.
2021-11-06 20:32:31 -04:00
13a590ca65 sim: use ARRAY_SIZE instead of ad-hoc sizeof calculations 2017-02-13 01:26:21 -05:00
93e6fe04cc Fix primary reason why the SH simulation hasn't been working on 64 bit hosts.
sim/sh/
	* interp.c (dmul): Split into dmul_s and dmul_u.  Use explicit integer
	width types and simplify implementation.
	* gencode.c (dmuls.l, dmulu.l): Use new functions dmul_s and dmul_u.
2016-04-10 11:02:47 +09:00
6cc9885631 sim: sh: delete global callback/argv
We can use the sim state everywhere now to get these values on the fly.
2015-11-22 00:53:23 -05:00
5fa71a1b13 sim: sh: clean up some warnings
Mostly converting old style prototypes.  Also include a few missing
headers, and add static/casts where appropriate.
2015-03-28 17:45:31 -04:00
02131c7ff6 sim: sh: fix broken handling in DSR reg
A missing */ caused a case statement to be incorrect masked out which
also hide an error where the wrong value was being checked.  Fix both.
2015-03-28 17:45:30 -04:00
ed4d32c28a sim: sh: clean up gencode
The build line was missing the normal BUILD_xxx flags.  Once we added
that, we get warnings that weren't shown before.  As we fix those, we
notice that the -d option segfaults because it tries to write readonly
memory.  Fix that too as part of the const/prototype clean up.
2015-03-28 17:45:30 -04:00
57df9adf2d Correct fabs and fneg insns in simulator
It seems that the implementation of the SH fabs and fneg insns in the
simulator is not correct.  They use the FP_UNARY macro which checks the
FPSCR.PR setting and raises an exception if PR = 1 (double precision)
and the register number is not even (i.e. a valid DF reg number).
For normal unary FP insns this is fine.  However, fneg and fabs perform
the same (integer) operations regardless of the FPSCR.PR setting.

This issue initially popped up here
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63260

I've checked some of the failing tests mentioned in GCC PR 63260 above
with the patch applied and the failures go away.

sim/sh/ChangeLog (tiny patch):

	* gencode.c (fabs, fneg): Implement as integer operation
	instead of using the FP_UNARY macro.
2014-11-28 19:44:03 +04:00
4d43927194 2007-09-24 Andrew Stubbs <andrew.stubbs@st.com>
* gencode.c (tab): Add RAISE_EXCEPTION_IF_IN_DELAY_SLOT to the
	definition of PC relative 'mov.l'/'mov.w' and also 'mova'.
2007-10-08 11:51:31 +00:00
6a1754a359 2007-03-02 Andrew Stubbs <andrew.stubbs@st.com>
* gencode.c (tab): Correct pre-decrement instructions when m == n.
2007-03-02 12:15:01 +00:00
195b8a572e * gencode.c (tab): Avoid lvalue casts. Suggested by
Ralf Corsepius <ralf.corsepius@rtems.org>.
2005-06-17 03:13:07 +00:00
53f541af8d * gencode.c (tab): Avoid inserting code before variables all declared. 2005-04-14 20:16:06 +00:00
ae0a84af70 * gencode.c (movua.l): Compensate for endianness.
* interp.c (RAISE_EXCEPTION_IF_IN_DELAY_SLOT): New macro.
	(in_delay_slot): New flag variable.
	(Delay_Slot): Set in_delay_slot.
	(sim_resume): Reset in_delay_slot after leaving code switch.
	* gencode.c (op tab): Call RAISE_EXCEPTION_IF_IN_DELAY_SLOT for all
	instructions not allowed in delay slots.

	Commited by Corinna Vinschen <vinschen@redhat.com>
	Introduce SH2a support.
	* interp.c: Change type of jump table to short.  Add various macros.
	(sim_load): Save the bfd machine code.
	(sim_create_inferior): Ditto.
	(union saved_state_type): Add tbr, ibnr and ibcr registers.
	Move bfd_mach to end of struct.  Add regstack pointer.
	(init_dsp): Don't swap contents of sh_dsp_table any more.  Instead
	use it directly in its own switch statement.  Allocate space for 512
	register banks.
	(do_long_move_insn): New function.
	(do_blog_insn): Ditto.
	(trap): Use trap #13 and trap #14 to set ibnr and ibcr.
	* gencode.c: Move movx/movy insns into separate switch statement.
	(op tab): Add sh2a insns.  Reject instructions that are disabled
	on that chip.
	(gensim_caselist): Generate default case here instead of in caller.
	(gensim): Generate two separate switch statements.  Call
	gensim_caselist once for each (for movsxy_tab and for tab).
	Add tokens for r15 and multiple regs.
	(conflict_warn, warn_conflicts): Add for debugging.
2004-09-08 09:11:50 +00:00
a134f341e6 * gencode.c (tab): For shad snd shld, fix result for
(op1 < 0 && shift_amount == 0).
2004-08-18 11:47:15 +00:00
915213a4d5 2004-02-02 Michael Snyder <msnyder@redhat.com>
* gencode.c (movua.l): Set thislock to 0, not n.
2004-02-13 00:01:19 +00:00
3e5117978b 2004-02-12 Michael Snyder <msnyder@redhat.com>
* gencode.c (table): Change from char to short.
	(dumptable): Change generated table from char to short.
	* interp.c (sh_jump_table, sh_dsp_table, ppi_table): char to short.
	(init_dsp): Compute size of sh_dsp_table.
	(sim_resume): Change jump_table from char to short.
2004-02-12 19:32:12 +00:00
0145ab2e52 2004-01-27 Michael Snyder <msnyder@redhat.com>
* gencode.c: (op tab): Some refs and defs fixes.
	"fsrra" -> "fsrra <FREG_N>".
        "sleep": replace array ref with array addr.
        "trapa": ditto.
2004-01-27 23:30:01 +00:00
4ae0cff4ca 2004-01-27 Michael Snyder <msnyder@redhat.com>
* gencode.c: Comment and whitespace clean-ups.
2004-01-27 23:23:57 +00:00
87acb4a7d1 2004-01-07 Michael Snyder <msnyder@redhat.com>
* gencode.c: Whitespace	cleanup.
        * interp.c: Ditto.
2004-01-10 00:43:28 +00:00
86bc60ebf4 2004-01-07 Michael Snyder <msnyder@redhat.com>
* gencode.c: Replace 'Hitachi' with 'Renesas'.
        (op tab): Add new instructions for sh4a, DBR, SBR.
        (expand_opcode): Add handling for new movxy combinations.
        (gensym_caselist): Ditto.
        (expand_ppi_movxy): Remove movx/movy expansions,
        now handled in expand_opcode.
        (gensym): Add some helpful macros.
        (expand_ppi_code): Flatten loop for simplicity, tweak for 12-bit
        instead of 8-bit table (some insns are ambiguous to 8 bits).
	(ppi_gensim, main): Generate 12-bit instead of 8-bit ppi table.

	* interp.c: Replace 'Hitachi' with 'Renesas'.
        (union saved_state_type): Add dbr, sgr, ldst.
        (get_loop_bounds_ext): New function.
        (init_dsp): Add bfd_mach_sh4al_dsp.
	(sim_resume): Handle extended loop bounds.
2004-01-09 19:44:50 +00:00
673fc5d0a7 2003-12-18 Michael Snyder <msnyder@redhat.com>
* gencode.c (expand_opcode): Simplify and reorganize.
        Eliminate "shift" parameter.  Eliminate "4 bits at a time"
        assumption.  Flatten switch statement to a single level.
        Add "eeee" token for even-numbered registers.
        (bton): Delete.
        (fsca): Use "eeee" token.
        (ppi_moves): Rename to "expand_ppi_movxy".  Do the ddt
        [movx/movy] expansion here, as well as the ppi expansion.
        (gensim_caselist): Accept 'eeee' along with 'nnnn'.
2004-01-06 01:05:02 +00:00
794cd17b28 * interp.c (fsca_s, fsrra_s): New functions.
* gencode.c (tab): Add entries for fsca and fsrra.
	(expand_opcode): Allow variable length n / m fields.
2003-11-03 14:14:15 +00:00
d1789acece 2003-08-11 Shrinivas Atre <shrinivasa@KPITCummins.com>
* sim/sh/gencode.c ( tab[] ): Addition of MAC.L handler and
        correction for MAC.W handler
        * sim/sh/interp.c ( macl ): New Function. Implementation of
        MAC.L handler.
2003-08-11 19:28:05 +00:00
240f98d342 2003-08-07 Michael Snyder <msnyder@redhat.com>
* gencode.c (expand_ppi_code): Comment spelling fix.
2003-08-07 21:36:43 +00:00
437b0e60a1 2003-07-25 Michael Snyder <msnyder@redhat.com>
* gencode.c (pshl): Change < to <= (shift by 16 is allowed).
        Cast argument of >> to unsigned to prevent sign extension.
        (psha): Change < to <= (shift by 32 is allowed).
2003-07-25 23:52:43 +00:00
32fcda6a20 2003-07-24 Michael Snyder <msnyder@redhat.com>
* gencode.c: Fix typo in comment.
2003-07-25 00:59:36 +00:00
e343a93ac0 2003-07-23 Michael Snyder <msnyder@redhat.com>
* gencode.c: A few more fix-ups of refs and defs.
        (frchg): Raise SIGILL if in double-precision mode.
        (ldtlb): We don't simulate cache, so this is a no-op.
        (movsxy_tab): Correct a few bit pattern errors.
2003-07-24 00:38:07 +00:00
1b606171ad 2003-07-09 Michael Snyder <msnyder@redhat.com>
* gencode.c (prnd): Clear LSW of result to zeros.
2003-07-23 21:47:28 +00:00
fcfae95cf8 2003-07-09 Michael Snyder <msnyder@redhat.com>
* gencode.c (pmuls): Expression is mis-parenthesized.
2003-07-23 21:43:50 +00:00
c13a4caaf8 2003-07-09 Michael Snyder <msnyder@redhat.com>
* gencode.c (ppi_gensim): For a conditional ppi insn, if the
        condition is false, we want to return (not break).  A break
        will take us to the end of the function where registers will
	be updated, whereas the desired outcome is for nothing to change.
2003-07-23 21:28:06 +00:00
b939d772c1 2003-06-27 Michael Snyder <msnyder@redhat.com>
* gencode.c (op tab): Some fix-ups of refs and defs.
        (ocbi, ocbp): Cache not simulated, but may cause memory fault.
        (gensym_caselist): Add default case to switch statement.
        (expand_ppi_code): Add default case to switch statement.
2003-07-23 21:25:41 +00:00
d2f18ae42a 2003-06-27 Michael Snyder <msnyder@redhat.com>
* gencode.c (op tab): Implement movca.l.
2003-07-23 21:23:32 +00:00
9e1d0fc1a1 2003-06-27 Michael Snyder <msnyder@redhat.com>
* gencode.c (op movsxy_tab): Fix an error in the bit pattern.
2003-07-23 21:17:33 +00:00
15dee5d561 2003-06-27 Michael Snyder <msnyder@redhat.com>
* gencode.c (gensim_caselist): The movy instructions use
        registers R6 and R7 (not R4 and R5 like the movx insns).
2003-07-23 21:14:54 +00:00
e53a5a69d7 2003-07-03 Michael Snyder <msnyder@redhat.com>
* gencode.c (movs): Fix a couple of text transpositions.
2003-07-04 00:03:52 +00:00
0b2828595e 2003-06-27 Michael Snyder <msnyder@redhat.com>
* gencode.c (op movsxy_tab): Fix up some copy/paste errors
        in name: s/REG_x/REG_y/.
2003-06-28 01:34:47 +00:00
8dc30ef74a 2003-06-27 Michael Snyder <msnyder@redhat.com>
* gencode.c (op tab): Move misplaced semicolon.
2003-06-27 21:18:42 +00:00
2bc8946db8 Commit Sh2E addition 2003-02-06 10:42:33 +00:00
fd8f4948fe gcc uses trap 33 for profiling, but the simulator didn't support it.
This patch fixes the gcc.dg/nest.c failures for sh-elf.

Fri Oct 11 16:22:28 2002  J"orn Rennecke <joern.rennecke@superh.com>

	* interp.c (trap): Return int.  Take extra parameter for address
	of the trap instruction.  Changed all callers.
	Add case 33 for profiling.
	* gencode.c (trapa): Handle trap 33 using the trap function.
	Add read of vector for generic traps.
2002-10-11 15:31:28 +00:00
8f1e3ff591 * pendanticism
2000-10-24  Ben Elliston  <bje@redhat.com>

	* gencode.c (tab): Delimit strings with commas where applicable.
2000-10-24 01:02:53 +00:00
63978407cb sh-dsp support, simulator speedup by using host byte order:
sim:
	* Makefile.in (interp.o): Depends on ppi.c .
	(ppi.c): New rule.
	* gencode.c (printonmatch, think, genopc): Deleted.
	(MAX_NR_STUFF): Now 42.
	(tab): Add SH-DSP CPU instructions.
	Amalgamate ldc / stc / lds / sts instructions with similar
	bit patterns.  Fix opcodes of stc Rm_BANK,@-<REG_N>.
	Fix semantics of lds.l @<REG_N>+,MACH (no sign extend).
	(movsxy_tab): New array.
	For movs, change MMMM field to GGGG, and mmmm field to MMMM.
	Added entries for movx, movy and parallel processing insns.
	(ppi_tab): New array.
	(qfunc): Stabilize sort.
	(expand_opcode): Handle [01][01]NN, [01][01]xx and [01][01]yy.
	Handle 'M', 'G' 's' 'X', 'a', 'Y' and 'A'.
	(dumptable): Now takes three arguments.  Changed all callers.
	Emit just one contigous jump table.
	(filltable): Now takes an argument.  Changed all callers.
	Make index static.
	(ppi_moves, expand_ppi_code, ppi_filltable, ppi_gensim): New functions.
	(gensim_caselist): New function, broken out of gensim.
	Handle opcode fields 'x', 'y', 's', 'M', 'G', 'X', 'a', and 'Y'.
	Handle ref '9'.
	(gensim): Handle 'N' in code field and '8' in refs field.
	Call gensim_caselist - twice.
	(ppi_index): New static variable.
	(main): Unsupport default action.
	Add dsp support for -x / -s option.  Add -p option.
	* interp.c (sh_jump_table, sh_dsp_table, ppi_table): Declare.
	(saved_state_type): Rearrange to allow amalgamated ldc / stc /
	lds / sts to work efficiently.
	(target_dsp): New static variable.
	(GBR, VBR, SSR, SPC, MACH, MACL): Reflect saved_state_type change.
	(FPUL, Rn_BANK, SET_Rn_BANK, M, Q, S, T, SR_BL, SR_RB): Likewise.
	(SR_MD, SR_RC, SET_SR_BIT, GET_SR, SET_RC, GET_FPSCR): Likewise.
	(RS, RE, MOD, MOD_ME, DSP_R): Likewise.
	(set_fpscr1): Likewise.  Use target_dsp to check for dsp.
	(MOD_MSi, SIG_BUS_FETCH): Deleted.
	(CREG, SREG, PR, SR_MASK_DMY, SR_MASK_DMX, SR_DMY): New macros.
	(SR_DMX, DSR, MOD_DELTA, GET_DSP_GRD): Likewise.
	(SET_MOD): Reflect saved_state_type change.  Set MOD_DELTA instead
	of MOD_MS, and encode SR_DMY / SR_DMX into high word of MOD_ME.
	(set_sr): Reflect saved_state_type change.  Fix SR_RB handling.
	Use SET_MOD.
	(MA, L, TL, TB): Now controlled by ACE_FAST.
	(SEXT32): Just cast to int.
	(SIGN32): Fixed to only shift by 31.
	(CHECK_INSN_PTR): SIGBUS at insn fetch now represented by insn_end 0.
	(ppi_insn): Declare.
	(ppi.c): Include.
	(init_dsp): Set target_dsp.  When it changes, switch end of
	sh_jump_table with sh_dsp_table.
	(sim_resume) Don't declare sh_jump_table0.  Use sh_jump_table instead.
	Don't Declare PR if it's #defined.
	Fix single-stepping (Was broken in Mar  6 16:59:10 patch).
	(sim_store_register, sim_read_register): Translate accesses to
	reflect saved_state_type change.

	* interp.c (set_sr): Set sr.
	(SET_RC, MOD, MOD_MS, MOD_ME, SET_MOD, MOD_MS, MOD_ME): New macros.
	(set_fpscr1): Don't bank-switch fpu registers when simulating sh-dsp.
	(DSP_R): Fix definition.
	(sim_resume): Remove outdated SET_SR use.

	* interp.c (saved_state): New members for struct member asregs:
	rs, re, insn_end, xram_start, yram_start.
	(struct loop_bounds): New struct.
	(SKIP_INSN): New macro.
	(get_loop_bounds): New function.
	(endianw): Renamed to global_endianw.
	(maskw): negated bits.
	(PC): Now insn_ptr.
	(SR_MASK_RC, SR_RC_INCREMENT, SR_RC, RAISE_EXCEPTION): New macros.
	(RS, RE, DSP_R, DSP_GRD, A1, A0, X0, X1, Y0, Y1, M0, A1G): Likewise.
	(M1, A0G, RIAT, PT2H, PH2T, SET_NIP, CHECK_INSN_PTR): Likewise.
	(SIG_BUS_FETCH): Likewise
	(raise_exception, riat_fast): New functions.
	(raise_buserror, sim_stop): Use raise_exception.
	(PROCESS_SPECIAL_ADDRESS): Use xram_start / yram_start.
	(BUSERROR, WRITE_BUSERROR, READ_BUSERROR):
	Reverse sense of mask argument.
	(FP_OP, set_dr): Use RAISE_EXCEPTION.
	(wlat_fast, wwat_fast, wbat_fast, rlat_fast, rwat_fast, rbat_fast):
	Declare.  Remove redundant masking.
	(wwat_fast, rwat_fast): Add argument endianw.  Changed callers.
	(MA): Updated for change pc -> PC.
	(Delay_Slot): Use RIAT.
	(empty): Deleted.
	(trap): Remove argument little_endian.  Add argument endianw.
	Changed all callers.  Use raise_exception.
	(macw): Add argument endainw.  Changed all callers.
	(init_dsp): New function, extended after broken out of init_pointers.
	(sim_resume): Replace pc with insn_ptr.  Replace little_endian with
	endianw.  Replace nia with nip.  Reverse sense of maskb / maskw /
	maskl.  Implement logic for zero-overhead loops.  Don't try to
	interpret garbage when getting a SIGBUS at insn fetch.
	(sim_open): Call init_dsp.
	* gencode.c (tab): Use SET_NIP instead of nia = .  Use PH2T / PT2H /
	RAISE_EXCEPTION where appropriate.
	Add extra cycles for brai, braf , bsr, bsrf, jmp, jsr.

	* interp.c (sim_store_register, sim_fetch_register):
	Do proper endianness switch.

	* interp.c (saved_state_type): New members for struct member asregs:
	xymem_select, xmem, ymem, xmem_offset, ymem_offset.
	(special_address): Delete.
	(BUSERROR): Now a two-argument predicate.
	(PROCESS_SPECIAL_ADDRESS, WRITE_BUSERROR, READ_BUSERROR): New macros.
	(wlat_little, wwat_little, wbat_any, wlat_big, wwat_big): Delete.
	(process_wlat_addr, process_wwat_addr): New functions.
	(process_wbat_addr, process_rlat_addr, process_rwat_addr): Likewise.
	(process_rbat_addr): Likewise.
	(wlat_fast, wwat_fast, wbat_fast): Use WRITE_BUSERROR.
	(rlat_little, rwat_little, rbat_any, rlat_big, rwat_big): Delete.
	(rlat_fast, rwat_fast, rbat_fast): Use READ_BUSERROR.
	(RWAT, RLAT, RBAT, WWAT, WLAT, WBAT): Delete SLOW versions.
	(do_rdat, trap): Delete SLOW code.
	(SEXT32, SIGN32): New macros.
	(swap, swap16): Now integer in - integer out.  Changed all callers.
	(strswaplen, strnswap): Delete SLOW versions.
	(init_pointers): Initialize dsp memory selection (preliminary).
	(sim_store_register, sim_fetch_register): Use swap instead of
	big / little endian read / write functions.

	* interp.c (maskl): Deleted.
	(endianw, endianb): New variables.
	(special_address): Now inline.
	(bp_holder): Put raising of buserror there, rename to:
	(raise_buserror).
	(BUSERROR): Now yields a value.  Changed all users.
	(wbat_big): Delete.
	(wlat_fast, wwat_fast, wbat_fast): New functions.
	(rlat_fast, rwat_fast, rbat_fast): Likewise.
	(RWAT, RLAT, RBAT, WWAT, WLAT, WBAT): Use new functions.
	(do_rdat, do_wdat): Likewise.  Take maskl argument instead of
	little_endian one.  Changed caller macros.
	(swap, swap16): Use w[rw]lat_big / w[rw]lat_little directly.
	(strswaplen, strnswap): New functions.
	(trap): Use them to fix up endian mismatches;
	disable SYS_execve and SYS_execv; fix double address translation for
	SYS_pipe and SYS_stat.
	(sym_write, sym_read): Add endianness translation.
	(sym_store_register, sym_fetch_register): Add maskl local variable.
	(sim_open): Set endianw and endianb.

gdb:

	* sh-tdep.c (sh_dsp_reg_names, sh3_dsp_reg_names): New arrays.
	(sh_processor_type_table): Add entries for bfd_mach_sh_dsp and
	 bfd_mach_sh3_dsp.
	(sh_show_regs): Floating point registers are called fr0-fr15.
	For sh4, display fpul, fpscr and fr0-fr15 / dr0-dr14 as appropriate.
	Handle sh-dsp and sh3-dsp.
	config/sh/tm-sh.h (REGISTER_VIRTUAL_TYPE): sh-dsp / sh3-dsp
	don't have floating point registers.
	(DSR_REGNUM, A0G_REGNUM, A0_REGNUM, A1G_REGNUM, A1_REGNUM): Define.
	(M0_REGNUM, M1_REGNUM, X0_REGNUM, X1_REGNUM, Y0_REGNUM): Likewise.
	(Y1_REGNUM, MOD_REGNUM, RS_REGNUM, RE_REGNUM, R0B_REGNUM): Likewise.
2000-05-15 21:12:42 +00:00
104c1213b4 import gdb-1999-08-30 snapshot 1999-08-31 01:14:27 +00:00
7a292a7adf import gdb-19990422 snapshot 1999-04-26 18:34:20 +00:00
c906108c21 Initial creation of sourceware repository 1999-04-16 01:35:26 +00:00
071ea11e85 Initial creation of sourceware repository 1999-04-16 01:34:07 +00:00