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4 Commits

Author SHA1 Message Date
Andrew Burgess
4749b84b51 gdb/riscv: better support for fflags and frm registers 
First, some background on the RISC-V registers fflags, frm, and fcsr.

These three registers all relate to the floating-point status and
control mechanism on RISC-V.  The fcsr is the floatint-point control
status register, and consists of two parts, the flags (bits 0 to 4)
and the rounding-mode (bits 5 to 7).

The fcsr register is just one of many control/status registers (or
CSRs) available on RISC-V.  The fflags and frm registers are also
CSRs.  These CSRs are aliases for the relevant parts of the fcsr
register.  So fflags is an alias for bits 0 to 4 of fcsr, and frm is
an alias for bits 5 to 7 of fcsr.

This means that a user can change the floating-point rounding mode
either, by writing a complete new value into fcsr, or by writing just
the rounding mode into frm.

How this impacts on GDB is like this: a target description could,
legitimately include all three registers, fcsr, fflags, and frm.  The
QEMU target currently does this, and this makes sense.  The target is
emulating the complete system, and has all three CSRs available, so
why not tell GDB about this.

In contrast, the RISC-V native Linux target only has access to the
fcsr.  This is because the ptrace data structure that the kernel uses
for reading and writing floating point state only contains a copy of
the fcsr, after all, this one field really contains both the fflags
and frm fields, so why carry around duplicate data.

So, we might expect that the target description for the RISC-V native
Linux GDB would only contain the fcsr register.  Unfortunately, this
is not the case.  The RISC-V native Linux target uses GDB's builtin
target descriptions by calling riscv_lookup_target_description, this
will then add an fpu feature from gdb/features/riscv, either
32bit-fpu.xml or 64bit-fpu.xml.  The problem, is that these features
include an entry for fcsr, fflags, and frm.  This means that GDB
expects the target to handle reading and writing these registers.  And
the RISC-V native Linux target currently doesn't.

In riscv_linux_nat_target::store_registers and
riscv_linux_nat_target::fetch_registers only the fcsr register is
handled, this means that, for RISC-V native Linux, the fflags and frm
registers always show up as <unavailable> - they are present in the
target description, but the target doesn't know how to access the
registers.

A final complication relating to these floating pointer CSRs is which
target description feature the registers appear in.

These registers are CSRs, so it would seem sensible that these
registers should appear in the CSR target description feature.

However, when I first added RISC-V target description support, I was
using a RISC-V simulator that didn't support any CSRs other than the
floating point related ones.  This simulator bundled all the float
related CSRs into the fpu target feature.  This didn't feel completely
unreasonable to me, and so I had GDB check for these registers in
either target feature.

In this commit I make some changes relating to how GDB handles the
three floating point CSR:

1. Remove fflags and frm from 32bit-fpu.xml and 64bit-fpu.xml.  This
means that the default RISC-V target description (which RISC-V native
FreeBSD), and the target descriptions created for RISC-V native Linux,
will not include these registers.  There's nothing stopping some other
target (e.g. QEMU) from continuing to include all three of these CSRs,
the code in riscv-tdep.c continues to check for all three of these
registers, and will handle them correctly if they are present.

2. If a target supplied fcsr, but does not supply fflags and/or frm,
then RISC-V GDB will now create two pseudo registers in order to
emulate the two missing CSRs.  These new pseudo-registers do the
obvious thing of just reading and writing the fcsr register.

3. With the new pseudo-registers we can no longer make use of the GDB
register numbers RISCV_CSR_FFLAGS_REGNUM and RISCV_CSR_FRM_REGNUM.
These will be the numbers used if the target supplies the registers in
its target description, but, if GDB falls back to using
pseudo-registers, then new, unique numbers will be used.  To handle
this I've added riscv_gdbarch_tdep::fflags_regnum and
riscv_gdbarch_tdep::frm_regnum, I've then updated the RISC-V code to
compare against these fields.

When adding the pseudo-register support, it is important that the
pseudo-register numbers are calculated after the call to
tdesc_use_registers.  This is because we don't know the total number
of physical registers until after this call, and the psuedo-register
numbers must follow on from the real (target supplied) registers.

I've updated some tests to include more testing of the fflags and frm
registers, as well as adding a new test.
 2022-08-31 16:07:05 +01:00
Tom Tromey
268a13a5a3 Rename common to gdbsupport 
This is the next patch in the ongoing series to move gdbsever to the
top level.

This patch just renames the "common" directory.  The idea is to do
this move in two parts: first rename the directory (this patch), then
move the directory to the top.  This approach makes the patches a bit
more tractable.

I chose the name "gdbsupport" for the directory.  However, as this
patch was largely written by sed, we could pick a new name without too
much difficulty.

Tested by the buildbot.

gdb/ChangeLog
2019-07-09  Tom Tromey  <tom@tromey.com>

	* contrib/ari/gdb_ari.sh: Change common to gdbsupport.
	* configure: Rebuild.
	* configure.ac: Change common to gdbsupport.
	* gdbsupport: Rename from common.
	* acinclude.m4: Change common to gdbsupport.
	* Makefile.in (CONFIG_SRC_SUBDIR, COMMON_SFILES)
	(HFILES_NO_SRCDIR, stamp-version, ALLDEPFILES): Change common to
	gdbsupport.
	* aarch64-tdep.c, ada-lang.c, ada-lang.h, agent.c, alloc.c,
	amd64-darwin-tdep.c, amd64-dicos-tdep.c, amd64-fbsd-nat.c,
	amd64-fbsd-tdep.c, amd64-linux-nat.c, amd64-linux-tdep.c,
	amd64-nbsd-tdep.c, amd64-obsd-tdep.c, amd64-sol2-tdep.c,
	amd64-tdep.c, amd64-windows-tdep.c, arch-utils.c,
	arch/aarch64-insn.c, arch/aarch64.c, arch/aarch64.h, arch/amd64.c,
	arch/amd64.h, arch/arm-get-next-pcs.c, arch/arm-linux.c,
	arch/arm.c, arch/i386.c, arch/i386.h, arch/ppc-linux-common.c,
	arch/riscv.c, arch/riscv.h, arch/tic6x.c, arm-tdep.c, auto-load.c,
	auxv.c, ax-gdb.c, ax-general.c, ax.h, breakpoint.c, breakpoint.h,
	btrace.c, btrace.h, build-id.c, build-id.h, c-lang.h, charset.c,
	charset.h, cli/cli-cmds.c, cli/cli-cmds.h, cli/cli-decode.c,
	cli/cli-dump.c, cli/cli-option.h, cli/cli-script.c,
	coff-pe-read.c, command.h, compile/compile-c-support.c,
	compile/compile-c.h, compile/compile-cplus-symbols.c,
	compile/compile-cplus-types.c, compile/compile-cplus.h,
	compile/compile-loc2c.c, compile/compile.c, completer.c,
	completer.h, contrib/ari/gdb_ari.sh, corefile.c, corelow.c,
	cp-support.c, cp-support.h, cp-valprint.c, csky-tdep.c, ctf.c,
	darwin-nat.c, debug.c, defs.h, disasm-selftests.c, disasm.c,
	disasm.h, dtrace-probe.c, dwarf-index-cache.c,
	dwarf-index-cache.h, dwarf-index-write.c, dwarf2-frame.c,
	dwarf2expr.c, dwarf2loc.c, dwarf2read.c, event-loop.c,
	event-top.c, exceptions.c, exec.c, extension.h, fbsd-nat.c,
	features/aarch64-core.c, features/aarch64-fpu.c,
	features/aarch64-pauth.c, features/aarch64-sve.c,
	features/i386/32bit-avx.c, features/i386/32bit-avx512.c,
	features/i386/32bit-core.c, features/i386/32bit-linux.c,
	features/i386/32bit-mpx.c, features/i386/32bit-pkeys.c,
	features/i386/32bit-segments.c, features/i386/32bit-sse.c,
	features/i386/64bit-avx.c, features/i386/64bit-avx512.c,
	features/i386/64bit-core.c, features/i386/64bit-linux.c,
	features/i386/64bit-mpx.c, features/i386/64bit-pkeys.c,
	features/i386/64bit-segments.c, features/i386/64bit-sse.c,
	features/i386/x32-core.c, features/riscv/32bit-cpu.c,
	features/riscv/32bit-csr.c, features/riscv/32bit-fpu.c,
	features/riscv/64bit-cpu.c, features/riscv/64bit-csr.c,
	features/riscv/64bit-fpu.c, features/tic6x-c6xp.c,
	features/tic6x-core.c, features/tic6x-gp.c, filename-seen-cache.h,
	findcmd.c, findvar.c, fork-child.c, gcore.c, gdb_bfd.c, gdb_bfd.h,
	gdb_proc_service.h, gdb_regex.c, gdb_select.h, gdb_usleep.c,
	gdbarch-selftests.c, gdbthread.h, gdbtypes.h, gnu-nat.c,
	go32-nat.c, guile/guile.c, guile/scm-ports.c,
	guile/scm-safe-call.c, guile/scm-type.c, i386-fbsd-nat.c,
	i386-fbsd-tdep.c, i386-go32-tdep.c, i386-linux-nat.c,
	i386-linux-tdep.c, i386-tdep.c, i387-tdep.c,
	ia64-libunwind-tdep.c, ia64-linux-nat.c, inf-child.c,
	inf-ptrace.c, infcall.c, infcall.h, infcmd.c, inferior-iter.h,
	inferior.c, inferior.h, inflow.c, inflow.h, infrun.c, infrun.h,
	inline-frame.c, language.h, linespec.c, linux-fork.c, linux-nat.c,
	linux-tdep.c, linux-thread-db.c, location.c, machoread.c,
	macrotab.h, main.c, maint.c, maint.h, memattr.c, memrange.h,
	mi/mi-cmd-break.h, mi/mi-cmd-env.c, mi/mi-cmd-stack.c,
	mi/mi-cmd-var.c, mi/mi-interp.c, mi/mi-main.c, mi/mi-parse.h,
	minsyms.c, mips-linux-tdep.c, namespace.h,
	nat/aarch64-linux-hw-point.c, nat/aarch64-linux-hw-point.h,
	nat/aarch64-linux.c, nat/aarch64-sve-linux-ptrace.c,
	nat/amd64-linux-siginfo.c, nat/fork-inferior.c,
	nat/linux-btrace.c, nat/linux-btrace.h, nat/linux-namespaces.c,
	nat/linux-nat.h, nat/linux-osdata.c, nat/linux-personality.c,
	nat/linux-procfs.c, nat/linux-ptrace.c, nat/linux-ptrace.h,
	nat/linux-waitpid.c, nat/mips-linux-watch.c,
	nat/mips-linux-watch.h, nat/ppc-linux.c, nat/x86-dregs.c,
	nat/x86-dregs.h, nat/x86-linux-dregs.c, nat/x86-linux.c,
	nto-procfs.c, nto-tdep.c, objfile-flags.h, objfiles.c, objfiles.h,
	obsd-nat.c, observable.h, osdata.c, p-valprint.c, parse.c,
	parser-defs.h, ppc-linux-nat.c, printcmd.c, probe.c, proc-api.c,
	procfs.c, producer.c, progspace.h, psymtab.h,
	python/py-framefilter.c, python/py-inferior.c, python/py-ref.h,
	python/py-type.c, python/python.c, record-btrace.c, record-full.c,
	record.c, record.h, regcache-dump.c, regcache.c, regcache.h,
	remote-fileio.c, remote-fileio.h, remote-sim.c, remote.c,
	riscv-tdep.c, rs6000-aix-tdep.c, rust-exp.y, s12z-tdep.c,
	selftest-arch.c, ser-base.c, ser-event.c, ser-pipe.c, ser-tcp.c,
	ser-unix.c, skip.c, solib-aix.c, solib-target.c, solib.c,
	source-cache.c, source.c, source.h, sparc-nat.c, spu-linux-nat.c,
	stack.c, stap-probe.c, symfile-add-flags.h, symfile.c, symfile.h,
	symtab.c, symtab.h, target-descriptions.c, target-descriptions.h,
	target-memory.c, target.c, target.h, target/waitstatus.c,
	target/waitstatus.h, thread-iter.h, thread.c, tilegx-tdep.c,
	top.c, top.h, tracefile-tfile.c, tracefile.c, tracepoint.c,
	tracepoint.h, tui/tui-io.c, ui-file.c, ui-out.h,
	unittests/array-view-selftests.c,
	unittests/child-path-selftests.c, unittests/cli-utils-selftests.c,
	unittests/common-utils-selftests.c,
	unittests/copy_bitwise-selftests.c, unittests/environ-selftests.c,
	unittests/format_pieces-selftests.c,
	unittests/function-view-selftests.c,
	unittests/lookup_name_info-selftests.c,
	unittests/memory-map-selftests.c, unittests/memrange-selftests.c,
	unittests/mkdir-recursive-selftests.c,
	unittests/observable-selftests.c,
	unittests/offset-type-selftests.c, unittests/optional-selftests.c,
	unittests/parse-connection-spec-selftests.c,
	unittests/ptid-selftests.c, unittests/rsp-low-selftests.c,
	unittests/scoped_fd-selftests.c,
	unittests/scoped_mmap-selftests.c,
	unittests/scoped_restore-selftests.c,
	unittests/string_view-selftests.c, unittests/style-selftests.c,
	unittests/tracepoint-selftests.c, unittests/unpack-selftests.c,
	unittests/utils-selftests.c, unittests/xml-utils-selftests.c,
	utils.c, utils.h, valarith.c, valops.c, valprint.c, value.c,
	value.h, varobj.c, varobj.h, windows-nat.c, x86-linux-nat.c,
	xml-support.c, xml-support.h, xml-tdesc.h, xstormy16-tdep.c,
	xtensa-linux-nat.c, dwarf2read.h: Change common to gdbsupport.

gdb/gdbserver/ChangeLog
2019-07-09  Tom Tromey  <tom@tromey.com>

	* configure: Rebuild.
	* configure.ac: Change common to gdbsupport.
	* acinclude.m4: Change common to gdbsupport.
	* Makefile.in (SFILES, OBS, GDBREPLAY_OBS, IPA_OBJS)
	(version-generated.c, gdbsupport/%-ipa.o, gdbsupport/%.o): Change
	common to gdbsupport.
	* ax.c, event-loop.c, fork-child.c, gdb_proc_service.h,
	gdbreplay.c, gdbthread.h, hostio-errno.c, hostio.c, i387-fp.c,
	inferiors.c, inferiors.h, linux-aarch64-tdesc-selftest.c,
	linux-amd64-ipa.c, linux-i386-ipa.c, linux-low.c,
	linux-tic6x-low.c, linux-x86-low.c, linux-x86-tdesc-selftest.c,
	linux-x86-tdesc.c, lynx-i386-low.c, lynx-low.c, mem-break.h,
	nto-x86-low.c, regcache.c, regcache.h, remote-utils.c, server.c,
	server.h, spu-low.c, symbol.c, target.h, tdesc.c, tdesc.h,
	thread-db.c, tracepoint.c, win32-i386-low.c, win32-low.c: Change
	common to gdbsupport.
 2019-07-09 07:45:38 -06:00
Andrew Burgess
172fb711a2 gdb/riscv: Use legacy register numbers in default target description 
When the target description support was added to RISC-V, the register
numbers assigned to the fflags, frm, and fcsr control registers in the
default target descriptions didn't match the register numbers used by
GDB before the target description support was added.

What this means is that if a tools exists in the wild that is using
hard-coded register number, setup to match GDB's old numbering, then
this will have been broken (for fflags, frm, and fcsr) by the move to
target descriptions.  QEMU is such a tool.

There are a couple of solutions that could be used to work around this
issue:

 - The user can create their own xml description file with the
   register numbers setup to match their old tool, then load this by
   telling GDB 'set tdesc filename FILENAME'.

 - Update their old tool to use the newer default numbering scheme, or
   better yet add proper target description support to their tool.

 - We could have RISC-V GDB change to maintain the old defaults.

This patch changes GDB back to using the old numbering scheme.

This change is only visible to remote targets that don't supply their
own xml description file and instead rely on GDB's default numbering.

Note that even though 32bit-cpu.xml and 64bit-cpu.xml have changed,
the corresponding .c file has not, this is because the numbering added
to the registers in the xml files is number 0, this doesn't result in
any new C code being generated .

gdb/ChangeLog:

	* features/riscv/32bit-cpu.xml: Add register numbers.
	* features/riscv/32bit-fpu.c: Regenerate.
	* features/riscv/32bit-fpu.xml: Add register numbers.
	* features/riscv/64bit-cpu.xml: Add register numbers.
	* features/riscv/64bit-fpu.c: Regenerate.
	* features/riscv/64bit-fpu.xml: Add register numbers.
 2019-02-26 22:57:35 +02:00
Andrew Burgess
b5ffee3181 gdb/riscv: Add target description support 
This commit adds target description support for riscv.

I've used the split feature approach for specifying the architectural
features, and the CSR feature is auto-generated from the riscv-opc.h
header file.

If the target doesn't provide a suitable target description then GDB
will build one by looking at the bfd headers.

This commit does not implement target description creation for the
Linux or FreeBSD native targets, both of these will need to add
read_description methods into their respective target classes, which
probe the target features, and then call
riscv_create_target_description to build a suitable target
description.  Until this is done Linux and FreeBSD will get the same
default target description based on the bfd that bare-metal targets
get.

I've only added feature descriptions for 32 and 64 bit registers, 128
bit registers (for RISC-V) are not supported in the reset of GDB yet.

This commit removes the special reading of the MISA register in order
to establish the target features, this was only used for figuring out
the f-register size, and even that wasn't done consistently.  We now
rely on the target to tell us what size of registers it has (or look
in the BFD as a last resort).  The result of this is that we should
now support RV64 targets with 32-bit float, though I have not
extensively tested this combination yet.

	* Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o.
	(HFILES_NO_SRCDIR): Add arch/riscv.h.
	* arch/riscv.c: New file.
	* arch/riscv.h: New file.
	* configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into
	this list, and add arch/riscv.o.
	* features/Makefile: Add riscv features.
	* features/riscv/32bit-cpu.c: New file.
	* features/riscv/32bit-cpu.xml: New file.
	* features/riscv/32bit-csr.c: New file.
	* features/riscv/32bit-csr.xml: New file.
	* features/riscv/32bit-fpu.c: New file.
	* features/riscv/32bit-fpu.xml: New file.
	* features/riscv/64bit-cpu.c: New file.
	* features/riscv/64bit-cpu.xml: New file.
	* features/riscv/64bit-csr.c: New file.
	* features/riscv/64bit-csr.xml: New file.
	* features/riscv/64bit-fpu.c: New file.
	* features/riscv/64bit-fpu.xml: New file.
	* features/riscv/rebuild-csr-xml.sh: New file.
	* riscv-tdep.c: Add 'arch/riscv.h' include.
	(riscv_gdb_reg_names): Delete.
	(csr_reggroup): New global.
	(struct riscv_register_alias): Delete.
	(struct riscv_register_feature): New structure.
	(riscv_register_aliases): Delete.
	(riscv_xreg_feature): New global.
	(riscv_freg_feature): New global.
	(riscv_virtual_feature): New global.
	(riscv_csr_feature): New global.
	(riscv_create_csr_aliases): New function.
	(riscv_read_misa_reg): Delete.
	(riscv_has_feature): Delete.
	(riscv_isa_xlen): Simplify, just return cached xlen.
	(riscv_isa_flen): Simplify, just return cached flen.
	(riscv_has_fp_abi): Update for changes in struct gdbarch_tdep.
	(riscv_register_name): Update to make use of tdesc_register_name.
	Look up xreg and freg names in the new globals riscv_xreg_feature
	and riscv_freg_feature.  Don't supply csr aliases here.
	(riscv_fpreg_q_type): Delete.
	(riscv_register_type): Use tdesc_register_type in almost all
	cases, override the returned type in a few specific cases only.
	(riscv_print_one_register_info): Handle errors reading registers.
	(riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for
	registers that are otherwise unknown to GDB.  Also check the
	csr_reggroup.
	(riscv_print_registers_info): Remove assert about upper register
	number, and use gdbarch_register_reggroup_p instead of
	short-cutting.
	(riscv_find_default_target_description): New function.
	(riscv_check_tdesc_feature): New function.
	(riscv_add_reggroups): New function.
	(riscv_setup_register_aliases): New function.
	(riscv_init_reggroups): New function.
	(_initialize_riscv_tdep): Add calls to setup CSR aliases, and
	setup register groups.  Register new riscv debug variable.
	* riscv-tdep.h: Add 'arch/riscv.h' include.
	(struct gdbarch_tdep): Remove abi union, and add
	riscv_gdbarch_features field.  Remove cached quad floating point
	type, and provide initialisation for double type field.
	* target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to
	the list of targets using the feature based target descriptions.
	* NEWS: Mention target description support.

gdb/doc/ChangeLog:

	* gdb.texinfo (Standard Target Features): Add RISC-V Features
	sub-section.
 2018-11-21 13:09:50 +00:00