Before commit:
commit 2438b771ee07be19d5b01ea55e077dd8b7cef445
Date: Wed Nov 2 15:53:43 2022 +0000
opcodes/mips: use .word/.short for undefined instructions
unknown 32-bit microMIPS instructions were disassembled as a raw
32-bit number with no '.word' directive. The above commit changed
this and added a '.word' directive before the 32-bit number.
It was pointed out on the mailing list, that for microMIPS it would be
better to display such 32-bit instructions using a '.short' directive
followed by two 16-bit values.
This commit updates the mips disassembler to do this, and adds a new
test that validates this output.
The newer update-copyright.py fixes file encoding too, removing cr/lf
on binutils/bfdtest2.c and ld/testsuite/ld-cygwin/exe-export.exp, and
embedded cr in binutils/testsuite/binutils-all/ar.exp string match.
While working on disassembler styling for MIPS, I noticed that
undefined instructions are printed by the disassembler as raw number
with no assembler directive prefix (e.g. without .word or .short).
I think adding something like .word, or .short, helps to make it
clearer the size of the value that is being displayed, and is inline
with what many of the other libopcode disassemblers do.
In this commit I've added the .word and .short directives, and updated
all the tests that I spotted that failed as a result.
Correct issues with INSN2_ALIAS annotation for branch instructions:
- regular MIPS BEQZ/L and BNEZ/L assembly instructions are idioms for
BEQ/L and BNE/L respectively with the `rs' operand equal to $0,
- microMIPS 32-bit BEQZ and BNEZ assembly instructions are idioms for
BEQ and BNE respectively with the `rt' operand equal to $0,
- regular MIPS BAL assembly instruction is an idiom for architecture
levels of up to the MIPSr5 ISA and a machine instruction on its own
from the MIPSr6 ISA up.
Add missing annotation to BEQZ/L and BNEZ/L accordingly then and add a
new entry for BAL for the MIPSr6 ISA, correcting a disassembly bug:
$ mips-linux-gnu-objdump -m mips:isa64r6 -M no-aliases -d bal.o
bal.o: file format elf32-tradlittlemips
Disassembly of section .text:
00000000 <foo>:
0: 04110000 0x4110000
...
$
Add test cases accordingly.
Parts for regular MIPS BEQZ/L and BNEZ/L instructions from Sagar Patel.
2022-03-06 Maciej W. Rozycki <macro@orcam.me.uk>
binutils/
* testsuite/binutils-all/mips/mips1-branch-alias.d: New test.
* testsuite/binutils-all/mips/mips1-branch-noalias.d: New test.
* testsuite/binutils-all/mips/mips2-branch-alias.d: New test.
* testsuite/binutils-all/mips/mips2-branch-noalias.d: New test.
* testsuite/binutils-all/mips/mips32r6-branch-alias.d: New test.
* testsuite/binutils-all/mips/mips32r6-branch-noalias.d: New
test.
* testsuite/binutils-all/mips/micromips-branch-alias.d: New
test.
* testsuite/binutils-all/mips/micromips-branch-noalias.d: New
test.
* testsuite/binutils-all/mips/mips-branch-alias.s: New test
source.
* testsuite/binutils-all/mips/micromips-branch-alias.s: New test
source.
* testsuite/binutils-all/mips/mips.exp: Run the new tests.
2022-03-06 Sagar Patel <sagarmp@cs.unc.edu>
Maciej W. Rozycki <macro@orcam.me.uk>
opcodes/
* mips-opc.c (mips_builtin_opcodes): Fix INSN2_ALIAS annotation
for "bal", "beqz", "beqzl", "bnez" and "bnezl" instructions.
* micromips-opc.c (micromips_opcodes): Likewise for "beqz" and
"bnez" instructions.
The result of running etc/update-copyright.py --this-year, fixing all
the files whose mode is changed by the script, plus a build with
--enable-maintainer-mode --enable-cgen-maint=yes, then checking
out */po/*.pot which we don't update frequently.
The copy of cgen was with commit d1dd5fcc38ead reverted as that commit
breaks building of bfp opcodes files.
The CP0 control register set has never been defined, however encodings
for the CFC0 and CTC0 instructions remained available for implementers
up until the MIPS32 ISA declared them invalid and causing the Reserved
Instruction exception[1]. Therefore we handle them for both assembly
and disassembly, however in the latter case the names of CP0 registers
from the regular set are incorrectly printed if named registers are
requested. This is because we do not define separate operand classes
for coprocessor regular and control registers respectively, which means
the disassembler has no way to tell the two cases apart. Consequently
nonsensical disassembly is produced like:
cfc0 v0,c0_random
Later the MIPSr5 ISA reused the encodings for XPA ASE MFHC0 and MTHC0
instructions[2] although it failed to document them in the relevant
opcode table until MIPSr6 only.
Correct the issue then by defining a new register class, OP_REG_CONTROL,
and corresponding operand codes, `g' and `y' for the two positions in
the machine instruction a control register operand can take. Adjust the
test cases affected accordingly.
While at it swap the regular MIPS opcode table "cfc0" and "ctc0" entries
with each other so that they come in the alphabetical order.
References:
[1] "MIPS32 Architecture For Programmers, Volume II: The MIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00086,
Revision 1.00, August 29, 2002, Table A-9 "MIPS32 COP0 Encoding of
rs Field", p. 242
[2] "MIPS Architecture For Programmers, Volume II-A: The MIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00086,
Revision 5.04, December 11, 2013, Section 3.2 "Alphabetical List of
Instructions", pp. 195, 216
include/
* opcode/mips.h: Document `g' and `y' operand codes.
(mips_reg_operand_type): Add OP_REG_CONTROL enumeration
constant.
gas/
* tc-mips.c (convert_reg_type) <OP_REG_CONTROL>: New case.
(macro) <M_TRUNCWS, M_TRUNCWD>: Use the `g' rather than `G'
operand code.
opcodes/
* mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
handling code over to...
<OP_REG_CONTROL>: ... this new case.
* mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
(mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
"cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
replacing the `G' operand code with `g'. Update "cftc1" and
"cftc2" entries replacing the `E' operand code with `y'.
* micromips-opc.c (decode_micromips_operand) <'g'>: New case.
(micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
entries replacing the `G' operand code with `g'.
binutils/
* testsuite/binutils-all/mips/mips-xpa-virt-1.d: Correct CFC0
operand disassembly.
* testsuite/binutils-all/mips/mips-xpa-virt-3.d: Likewise.
Fix commit 9785fc2a4d22 ("MIPS: Fix XPA base and Virtualization ASE
instruction handling") and explicitly use the `mips:3000' machine for
disassembly across the XPA base and XPA Virtualization ASE test cases,
providing actual coverage for the `virt' and `xpa' disassembler options
and removing failures for targets that default to those ASEs enabled:
mipsisa32r2-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r2-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r2-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r2-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r2-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r2-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r2el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r2el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r2el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r2el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r2el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r2el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r3-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r3-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r3-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r3-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r3-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r3-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r3el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r3el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r3el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r3el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r3el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r3el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r5-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r5-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r5-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r5-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r5-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r5-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r5el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r5el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r5el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r5el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r5el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r5el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r6-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r6-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r6-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r6-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r6-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r6-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r6el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r6el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r6el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r6el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r6el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r6el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r2-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r2-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r2-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r2-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r2-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r2-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r2el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r2el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r2el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r2el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r2el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r2el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r3-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r3-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r3-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r3-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r3-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r3-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r3el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r3el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r3el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r3el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r3el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r3el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r5-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r5-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r5-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r5-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r5-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r5-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r5el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r5el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r5el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r5el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r5el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r5el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r6-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r6-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r6-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r6-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r6-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r6-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r6el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r6el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r6el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r6el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r6el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r6el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
This is because the test cases rely on these ASEs being disabled for
disassembly by default and expect instructions belonging to these ASEs
not to be shown unless explicitly enabled. The `mips-xpa-virt-4' test
case passes regardless, but we want it to verify the explicit options do
work, so use the `mips:3000' machine to set the defaults there as well.
binutils/
* testsuite/binutils-all/mips/mips-xpa-virt-1.d: Use `mips:3000'
machine for disassembly.
* testsuite/binutils-all/mips/mips-xpa-virt-2.d: Likewise.
* testsuite/binutils-all/mips/mips-xpa-virt-3.d: Likewise.
* testsuite/binutils-all/mips/mips-xpa-virt-4.d: Likewise.
Make the MIPS/IRIX naming of local section symbols consistent between
files produced by generic ELF code and ELF linker code, complementing
commit 174fd7f95561 ("New bfd elf hook: force naming of local section
symbols"), <https://sourceware.org/ml/binutils/2004-02/msg00072.html>.
Local section symbols have no names in the standard ELF gABI, however
the lack of a name causes problems with IRIX's MIPSpro linker. To work
around the issue we give them names, however we do that in generic ELF
code only, based on what the `elf_backend_name_local_section_symbols'
hook returns if present. That makes objects created by GAS or `objdump'
work correctly, however not ones created by `ld -r'. That would not
normally cause issues with IRIX systems using GAS and `objdump' only
with the MIPSpro linker, however if GNU LD was used for whatever reason
in producing objects later fed to IRIX's MIPSpro linker, then things
would break.
Modify ELF linker code accordingly then, using the same hook. Adjust
the `ld-elf/64ksec-r' test accordingly so that it also accepts a section
symbol with a name.
Also modify the hook itself so that only actual ET_REL objects have
names assigned to local section symbols. Other kinds of ELF files are
not ever supposed to be relocated with the MIPSpro linker, so we can
afford producing more standard output.
Add suitable GAS, LD and `objcopy' test cases to the relevant testsuites
to keep these tools consistently verified. This change also fixes:
FAIL: objcopy executable (pr25662)
across MIPS targets using the IRIX compatibility mode.
bfd/
* elflink.c (bfd_elf_final_link): Give local symbols a name if
so requested.
* elfxx-mips.c (_bfd_mips_elf_name_local_section_symbols): Only
return TRUE if making ET_REL output.
binutils/
* testsuite/binutils-all/mips/global-local-symtab-sort-o32.d:
New test.
* testsuite/binutils-all/mips/global-local-symtab-sort-o32t.d:
New test.
* testsuite/binutils-all/mips/global-local-symtab-sort-n32.d:
New test.
* testsuite/binutils-all/mips/global-local-symtab-sort-n32t.d:
New test.
* testsuite/binutils-all/mips/global-local-symtab-sort-n64.d:
New test.
* testsuite/binutils-all/mips/global-local-symtab-sort-n64t.d:
New test.
* testsuite/binutils-all/mips/global-local-symtab-final-o32.d:
New test.
* testsuite/binutils-all/mips/global-local-symtab-final-n32.d:
New test.
* testsuite/binutils-all/mips/global-local-symtab-final-n64.d:
New test.
* testsuite/binutils-all/mips/mips.exp: Run the new tests.
gas/
* testsuite/gas/mips/global-local-symtab-sort-o32.d: New test.
* testsuite/gas/mips/global-local-symtab-sort-o32t.d: New test.
* testsuite/gas/mips/global-local-symtab-sort-n32.d: New test.
* testsuite/gas/mips/global-local-symtab-sort-n32t.d: New test.
* testsuite/gas/mips/global-local-symtab-sort-n64.d: New test.
* testsuite/gas/mips/global-local-symtab-sort-n64t.d: New test.
* testsuite/gas/mips/mips.exp: Run the new tests.
ld/
* testsuite/ld-elf/sec64k.exp: Also accept a section symbol with
a name.
* testsuite/ld-mips-elf/global-local-symtab-sort-o32.d: New
test.
* testsuite/ld-mips-elf/global-local-symtab-sort-o32t.d: New
test.
* testsuite/ld-mips-elf/global-local-symtab-sort-n32.d: New
test.
* testsuite/ld-mips-elf/global-local-symtab-sort-n32t.d: New
test.
* testsuite/ld-mips-elf/global-local-symtab-sort-n64.d: New
test.
* testsuite/ld-mips-elf/global-local-symtab-sort-n64t.d: New
test.
* testsuite/ld-mips-elf/global-local-symtab-final-o32.d: New
test.
* testsuite/ld-mips-elf/global-local-symtab-final-n32.d: New
test.
* testsuite/ld-mips-elf/global-local-symtab-final-n64.d: New
test.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
Correct ELF linker code so as to set the `sh_info' value of the static
symbol table section according to the section symbols vs other symbols
split where required by the selection of the IRIX compatibility mode for
MIPS target. Add a `elf_backend_elfsym_local_is_section' hook for that
purpose, returning TRUE if it is only STB_LOCAL/STT_SECTION symbols that
are to be considered local for the purpose of this split rather than all
STB_LOCAL symbols.
We do it already in generic ELF code, and have done it since 1993, with
the `elf_backend_sym_is_global' hook, affecting GAS and `objcopy', so
these tools produce correct ELF output in the IRIX compatibility mode,
however if such output is fed as input to `ld -r', then the linker's
output is no longer valid for that mode. The relevant changes to
generic ELF code are:
commit 062189c6eab72c7ba1bab1cf30fdb27d67a7d668
Author: Ian Lance Taylor <ian@airs.com>
Date: Thu Nov 18 17:12:47 1993 +0000
and:
commit 6e07e54f1b347f885cc6c021c3fd912c79bdaf55
Author: Ian Lance Taylor <ian@airs.com>
Date: Thu Jan 6 20:01:42 1994 +0000
(split across two GIT commits likely due to repository conversion
peculiarities).
The `elf_backend_sym_is_global' hook however operates on BFD rather than
ELF symbols, making it unsuitable for the ELF linker as the linker does
not convert any symbol tables processed into the BFD format. Converting
the hook to operate on ELF symbols would in principle be possible, but
it would still require a considerable rewrite of `bfd_elf_final_link' to
adapt to the interface.
Therefore, especially given that no new use for the IRIX compatibility
mode is expected, minimize changes made to the ELF linker code and just
add an entirely new hook, and wire it in the o32 and n32 MIPS backends
accordingly; the n64 backend never uses the IRIX compatibility mode.
Since we have no coverage here at all add suitable GAS, LD and `objcopy'
test cases to the relevant testsuites to keep these tools consistently
verified.
bfd/
* elf-bfd.h (elf_backend_data): Add
`elf_backend_elfsym_local_is_section' member.
* elfxx-target.h (elf_backend_elfsym_local_is_section): New
macro.
(elfNN_bed): Add `elf_backend_elfsym_local_is_section' member.
* elflink.c (bfd_elf_final_link): Use it to determine whether
set the `.symtab' section's `sh_info' value to the index of the
first non-local or non-section symbol.
* elf32-mips.c (mips_elf32_elfsym_local_is_section): New
function.
(elf_backend_elfsym_local_is_section): New macro.
* elfn32-mips.c (mips_elf_n32_elfsym_local_is_section): New
function.
(elf_backend_elfsym_local_is_section): New macro.
binutils/
* testsuite/binutils-all/mips/global-local-symtab-o32.d: New
test.
* testsuite/binutils-all/mips/global-local-symtab-o32t.d: New
test.
* testsuite/binutils-all/mips/global-local-symtab-n32.d: New
test.
* testsuite/binutils-all/mips/global-local-symtab-n32t.d: New
test.
* testsuite/binutils-all/mips/global-local-symtab-n64.d: New
test.
* testsuite/binutils-all/mips/mips.exp: Run the new tests.
gas/
* testsuite/gas/mips/global-local-symtab-o32.d: New test.
* testsuite/gas/mips/global-local-symtab-o32t.d: New test.
* testsuite/gas/mips/global-local-symtab-n32.d: New test.
* testsuite/gas/mips/global-local-symtab-n32t.d: New test.
* testsuite/gas/mips/global-local-symtab-n64.d: New test.
* testsuite/gas/mips/global-local-symtab.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
ld/
* testsuite/ld-mips-elf/global-local-symtab-o32.d: New test.
* testsuite/ld-mips-elf/global-local-symtab-o32t.d: New test.
* testsuite/ld-mips-elf/global-local-symtab-n32.d: New test.
* testsuite/ld-mips-elf/global-local-symtab-n32t.d: New test.
* testsuite/ld-mips-elf/global-local-symtab-n64.d: New test.
* testsuite/ld-mips-elf/global-local-symtab.ld: New test linker
script.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
The binutils testsuite supports involving LD in processing test cases
and with the MIPS target that has the same issues the LD testsuite does.
So to support LD in the MIPS part of the binutils testsuite similarly
to commit 86b24e15c45b ("MIPS/LD/testsuite: Correct comm-data.exp test
ABI/emul/endian arrangement") update the mips.exp test script to:
- correctly select emulations for targets using non-traditional MIPS
emulations,
- correctly select ABIs for targets that do not support all of them,
- use the default endianness selection where possible to benefit targets
that support only one,
- simplify test invocation by providing ABI-specific `run_dump_test'
wrappers, specifically `run_dump_test_o32', `run_dump_test_n32' and
`run_dump_test_n64', which remove the need to use conditionals across
the Expect script or to repeat ABI-specific GAS and LD flags with each
invocation,
borrowing changes from commit 78da84f99405 ("MIPS/LD/testsuite: Correct
mips-elf.exp test ABI/emul/endian arrangement").
As a side effect this disables o32 ABI testing for targets that are not
supposed to support them and do not with LD, but still have such support
with BFD and GAS due to our inflexibility in configuration. Ultimately
we ought to support having o32 completely disabled.
binutils/
* testsuite/binutils-all/mips/mips.exp (run_dump_test_abi)
(run_dump_test_o32, run_dump_test_n32, run_dump_test_n64): New
procedures.
(has_newabi): Remove variable.
(has_abi, abi_asflags, abi_ldflags): New associative array
variables.
(irixemul): New variable.
Replace `run_dump_test' calls where applicable throughout with
`run_dump_test_o32', `run_dump_test_n32' and `run_dump_test_n64'
as appropriate. Use `noarch' for tests that require their own
architecture setting.
* testsuite/binutils-all/mips/mips-ase-1.d: Remove GAS flags.
* testsuite/binutils-all/mips/mips-ase-2.d: Likewise.
* testsuite/binutils-all/mips/mips-ase-3.d: Likewise.
* testsuite/binutils-all/mips/mips-note-2-n32.d: Likewise.
* testsuite/binutils-all/mips/mips-note-2-n64.d: Likewise.
* testsuite/binutils-all/mips/mips-note-2.d: Likewise.
* testsuite/binutils-all/mips/mips-note-2r-n32.d: Likewise.
* testsuite/binutils-all/mips/mips-note-2r-n64.d: Likewise.
* testsuite/binutils-all/mips/mips-note-2r.d: Likewise.
* testsuite/binutils-all/mips/mips-reginfo-n32.d: Likewise.
* testsuite/binutils-all/mips/mips-reginfo.d: Likewise.
* testsuite/binutils-all/mips/mips16-extend-noinsn.d: Likewise.
* testsuite/binutils-all/mips/mips16-pcrel.d: Likewise.
* testsuite/binutils-all/mips/mips16-alias.d: Remove `-32' from
GAS flags.
* testsuite/binutils-all/mips/mips16-extend-insn.d: Likewise.
* testsuite/binutils-all/mips/mips16-noalias.d: Likewise.
* testsuite/binutils-all/mips/mips16-undecoded.d: Likewise.
* testsuite/binutils-all/mips/mips16e2-extend-insn.d: Likewise.
* testsuite/binutils-all/mips/mips16e2-undecoded.d: Likewise.
* testsuite/binutils-all/mips/mixed-micromips.d: Likewise.
* testsuite/binutils-all/mips/mixed-mips16.d: Likewise.
Report an error when an unsupported `.reginfo' section size is found in
`_bfd_mips_elf_section_processing', removing an assertion that triggers
at elfxx-mips.c:7105 in GAS when assembling input like:
.section .reginfo
.word 0xdeadbeef
and in `objcopy --rename-section' when renaming an incorrectly sized
section to `.reginfo'.
bfd/
* elfxx-mips.c (_bfd_mips_elf_section_processing): For
SHT_MIPS_REGINFO sections don't assert the correct size and
report an error instead.
binutils/
* testsuite/binutils-all/mips/mips-reginfo.d: New test.
* testsuite/binutils-all/mips/mips-reginfo-n32.d: New test.
* testsuite/binutils-all/mips/mips-reginfo.s: New test source.
* testsuite/binutils-all/mips/mips.exp: Run the new tests.
gas/
* testsuite/gas/mips/reginfo-2.d: New test.
* testsuite/gas/mips/reginfo-2-n32.d: New test.
* testsuite/gas/mips/reginfo-2.l: New test stderr output.
* testsuite/gas/mips/reginfo-2.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
I am checking in the attached patch which updates the binutils
support for version 3 binary annotation notes. (Version 3 adds
an end address to the ranges covered by the notes, so that it
is possible to detect gaps in the coverage).
This patch also stops the note merging feature of objcopy from
executing if the notes have relocations against them. This makes the
code simpler, and prevents the problems with architectures which have
unusual relocation management issues.
* objcopy.c (objcopy_internal_note): New structure.
(gap_exists): New function.
(is_open_note): New function.
(is_func_note): New function.
(is_64bit): New function.
(merge_gnu_build_notes): Handle v3 notes. Do not merge
if there are relocations against the notes.
* readelf.c (get_note_type): Use short names for build attribute
notes.
(print_symbol_for_build_attribute): Rename to
get_symbol_for_build_attribute. Returns the found symbol rather
than printing it.
(print_gnu_build_attribute_description): Maintain address ranges
for function notes as well as global notes. Handle v3 notes.
(print_gnu_build_attribute_name): Use more space for printing the
name in wide mode.
* testsuite/binutils-all/note-2-32.s: Use .dc.l instead of .word.
Eliminate symbol references in order to remove the need for
relocations.
* testsuite/binutils-all/note-2-64.s: Likewise.
* testsuite/binutils-all/note-3-32.s: Add a size to the note_1
symbol.
* testsuite/binutils-all/note-3-64.s: Likewise.
* testsuite/binutils-all/mips/mips-note-2r-n32.d: Update expected
output.
* testsuite/binutils-all/mips/mips-note-2r-n64.d: Likewise.
* testsuite/binutils-all/mips/mips-note-2r.d: Likewise.
* testsuite/binutils-all/note-2-32.d: Likewise.
* testsuite/binutils-all/note-2-64.d: Likewise.
* testsuite/binutils-all/note-3-32.d: Likewise.
* testsuite/binutils-all/note-3-64.d: Likewise.
* testsuite/binutils-all/note-4-64.s: New test. Checks v3 notes.
* testsuite/binutils-all/note-4-32.s: New test.
* testsuite/binutils-all/note-4-64.d: New test result file.
* testsuite/binutils-all/note-4-32.d: New test result file.
Correct a commit 7d64c587c15f ("Add support for the MIPS eXtended
Physical Address (XPA) ASE.") bug, causing XPA base and Virtualization
ASE instructions to be wrongly always enabled with the selection of the
MIPS32r2 or higher ISA.
For example this source assembles successfully as shown below:
$ cat xpa.s
mfhc0 $2, $1
$ as -32 -mips32 -o xpa.o xpa.s
xpa.s: Assembler messages:
xpa.s:1: Error: opcode not supported on this processor: mips32 (mips32) `mfhc0 $2,$1'
$ as -32 -mips32r2 -o xpa.o xpa.s
$ objdump -d xpa.o
xpa.o: file format elf32-tradbigmips
Disassembly of section .text:
00000000 <.text>:
0: 40420800 mfhc0 v0,c0_random
...
$
To address this issue remove the I33 (INSN_ISA32R2) marking from all XPA
instructions in the opcode table. Additionally, for XPA Virtualization
ASE instructions implement an XPAVZ (ASE_XPA_VIRT) combination ASE flag
and use it in place of IVIRT|XPA (ASE_VIRT|ASE_XPA).
Now the same source is correctly rejected unless the `-mxpa' option is
also used:
$ as -32 -mips32r2 -o xpa.o xpa.s
xpa.s: Assembler messages:
xpa.s:1: Error: opcode not supported on this processor: mips32r2 (mips32r2) `mfhc0 $2,$1'
$ as -32 -mips32r2 -mxpa -o xpa.o xpa.s
$
Add test cases for XPA base and XPA Virtualization ASE instructions.
Parts of this change by Andrew Bennett.
include/
* opcode/mips.h (ASE_XPA_VIRT): New macro.
opcodes/
* mips-dis.c (mips_calculate_combination_ases): Handle the
ASE_XPA_VIRT flag.
(parse_mips_ase_option): New function.
(parse_mips_dis_option): Factor out ASE option handling to the
new function. Call `mips_calculate_combination_ases'.
* mips-opc.c (XPAVZ): New macro.
(mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
"mfhgc0", "mthc0" and "mthgc0".
gas/
* config/tc-mips.c (mips_set_ase): Handle the ASE_XPA_VIRT flag.
* testsuite/gas/mips/xpa.d: Remove `xpa' from `-M' in `objdump'
flags. Add `-mvirt' to `as' flags.
* testsuite/gas/mips/xpa-err.d: New test.
* testsuite/gas/mips/xpa-virt-err.d: New test.
* testsuite/gas/mips/xpa-err.l: New stderr output.
* testsuite/gas/mips/xpa-virt-err.l: New stderr output.
* testsuite/gas/mips/xpa-err.s: New test source.
* testsuite/gas/mips/xpa-virt-err.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
binutils/
* testsuite/binutils-all/mips/mips-xpa-virt-1.d: New test.
* testsuite/binutils-all/mips/mips-xpa-virt-2.d: New test.
* testsuite/binutils-all/mips/mips-xpa-virt-3.d: New test.
* testsuite/binutils-all/mips/mips-xpa-virt-4.d: New test.
* testsuite/binutils-all/mips/mips-xpa-virt.s: New test source.
* testsuite/binutils-all/mips/mips.exp: Run the new tests.
Revert parts of commit fee24f1c5bfe ("objdump improvements for mips
elf64"), <https://sourceware.org/ml/binutils/2003-03/msg00108.html>, and
make the `->reloc_count' member of `struct bfd_section' hold the actual
number of internal relocations stored in its `->relocation' vector. To
do so adjust `mips_elf64_slurp_one_reloc_table' to set `->reloc_count'
to the actual number of internal relocations retrieved and discard
`mips_elf64_canonicalize_reloc', `mips_elf64_canonicalize_dynamic_reloc'
and their corresponding target macros. Contrary to the description of
`mips_elf64_slurp_one_reloc_table', adjusted appropriately, this makes
generic relocation processing code happy and satisfies the "merge notes
section" binutils test case.
Add extra binutils test cases to expand the coverage of the generic
"merge notes section" test case, now passing with the n64 ABI, across
the MIPS o32, n32 and n64 ABIs regardless of the default ABI selected in
target configuration, and also to verify correctness of the relocations
produced. Conversely, do not provide any additional test cases for the
original issue addressed with the commit referred:
- objdump would display only 1/3 of the total number of relocations,
because it used the external relocation count, but each external
relocation is brought in as 3 internal relocations.
as n64 ABI relocation processing with `objdump -r' and `objdump -R' is
already widely covered across the GAS and LD test suites.
bfd/
* elf64-mips.c (mips_elf64_canonicalize_reloc): Remove prototype
and function.
(mips_elf64_canonicalize_dynamic_reloc): Likewise.
(mips_elf64_slurp_one_reloc_table): Set `reloc_count' to the
actual number of internal relocations retrieved. Adjust
function description.
(bfd_elf64_canonicalize_reloc): Remove macro.
(bfd_elf64_canonicalize_dynamic_reloc): Likewise.
binutils/
* testsuite/binutils-all/mips/mips-note-2.d: New test.
* testsuite/binutils-all/mips/mips-note-2r.d: New test.
* testsuite/binutils-all/mips/mips-note-2-n32.d: New test.
* testsuite/binutils-all/mips/mips-note-2-n64.d: New test.
* testsuite/binutils-all/mips/mips-note-2r-n32.d: New test.
* testsuite/binutils-all/mips/mips-note-2r-n64.d: New test.
* testsuite/binutils-all/mips/mips.exp: Define `has_newabi'.
Run the new tests.
We have but ELF binutils tests in the MIPS subset, and non-ELF MIPS/GAS
ports are gone, making a future addition of any non-ELF tests unlikely.
Bail out right away then if non-ELF, consuming one level of indentation
across the actual tests run.
binutils/
* testsuite/binutils-all/mips/mips.exp: Bail out right away if
non-ELF.
Verify MIPS16e2 ASE instruction assembly, disassembly and object file
flags.
binutils/
* testsuite/binutils-all/mips/mips16-undecoded.d: Add `-mips3'
to `as' flags.
* testsuite/binutils-all/mips/mips16e2-undecoded.d: New test.
* testsuite/binutils-all/mips/mips16e2-extend-insn.d: New test.
* testsuite/binutils-all/mips/mips16-undecoded.s: Remove
`.module mips3'.
* testsuite/binutils-all/mips/mips.exp: Run the new tests.
gas/
* testsuite/gas/mips/mips16e2.d: New test.
* testsuite/gas/mips/mips16e2-mt.d: New test.
* testsuite/gas/mips/mips16e2-sub.d: New test.
* testsuite/gas/mips/mips16e2@mips16e2-sub.d: New test.
* testsuite/gas/mips/mips16e2-mt-sub.d: New test.
* testsuite/gas/mips/mips16e2@mips16e2-mt-sub.d: New test.
* testsuite/gas/mips/mips16e2-hilo.d: New test.
* testsuite/gas/mips/mips16e2-hilo-n32.d: New test.
* testsuite/gas/mips/mips16e2-reloc-error.d: New test.
* testsuite/gas/mips/mips16e2-imm-error.d: New test.
* testsuite/gas/mips/elf_ase_mips16e2.d: New test.
* testsuite/gas/mips/elf_ase_mips16e2-2.d: New test.
* testsuite/gas/mips/elf-rel9-mips16e2.d: New test.
* testsuite/gas/mips/mips16e2-lui.d: New test.
* testsuite/gas/mips/mips16e2@mips32r2-sync.d: New test.
* testsuite/gas/mips/mips16e2@mips32r2-sync-1.d: New test.
* testsuite/gas/mips/mips16e2@lui-2.d: New test.
* testsuite/gas/mips/mips16e2-reloc-error.l: New stderr output.
* testsuite/gas/mips/mips16e2-imm-error.l: New stderr output.
* testsuite/gas/mips/mips16e2@lui-2.l: New stderr output.
* testsuite/gas/mips/mips16e2.s: New test source.
* testsuite/gas/mips/mips16e2-mt.s: New test source.
* testsuite/gas/mips/mips16e2-sub.s: New test source.
* testsuite/gas/mips/mips16e2-mt-sub.s: New test source.
* testsuite/gas/mips/mips16e2-hilo.s: New test source.
* testsuite/gas/mips/mips16e2-reloc-error.s: New test source.
* testsuite/gas/mips/mips16e2-imm-error.s: New test source.
* testsuite/gas/mips/elf-rel9-mips16e2.s: New test source.
* testsuite/gas/mips/mips16e2-lui.s: New test source.
* testsuite/gas/mips/mips.exp: Expand `mips32r2-sync',
`mips32r2-sync-1', `lui-1' and `lui-2' tests across MIPS16e2
architectures. Run the new tests.
Disassemble the MIPS16 BREAK and SDBBP instruction's immediate operand
in the hexadecimal rather than decimal numeral system and add respective
operandless variants with an implicit 0 operand, making our handling of
these instructions consistent with how we have processed their regular
MIPS and microMIPS counterparts since forever.
opcodes/
* mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
type to hexadecimal.
(mips16_opcodes): Add operandless "break" and "sdbbp" entries.
binutils/
* testsuite/binutils-all/mips/mips16-extend-insn.d: Adjust BREAK
and SDBBP disassembly.
gas/
* testsuite/gas/mips/mips16.d: Adjust BREAK disassembly.
* testsuite/gas/mips/mips16-64@mips16.d: Likewise.
* testsuite/gas/mips/mips16-64.d: Likewise.
* testsuite/gas/mips/mips16-64@mips16-64.d: Likewise.
* testsuite/gas/mips/mips16-macro.d: Likewise.
* testsuite/gas/mips/mips16-64@mips16-macro.d: Likewise.
* testsuite/gas/mips/mips16-sub.d: Likewise.
* testsuite/gas/mips/mips16-32@mips16-sub.d: Likewise.
Define `tempfile' and `copyfile' in `mips.exp' so that standalone script
execution via `RUNTESTFLAGS=mips.exp' works rather than producing:
Running .../binutils/testsuite/binutils-all/mips/mips.exp ...
ERROR: tcl error sourcing
.../binutils/testsuite/binutils-all/mips/mips.exp.
ERROR: can't read "tempfile": no such variable
while executing
"binutils_assemble_flags ${srcfile} $tempfile $opts(as)"
(procedure "run_dump_test" line 207)
invoked from within
"run_dump_test "mips-ase-1""
invoked from within
"if [is_elf_format] {
run_dump_test "mips-ase-1"
run_dump_test "mips-ase-2"
run_dump_test "mips-ase-3"
run_dump_test "mixed-mips16"
..."
(file ".../binutils/testsuite/binutils-all/mips/mips.exp" line 22)
invoked from within
"source .../binutils/testsuite/binutils-all/mips/mips.exp"
("uplevel" body line 1)
invoked from within
"uplevel #0 source .../binutils/testsuite/binutils-all/mips/mips.exp"
invoked from within
"catch "uplevel #0 source $test_file_name""
testcase .../binutils/testsuite/binutils-all/mips/mips.exp completed in 0 seconds
binutils/
* testsuite/binutils-all/mips/mips.exp: Define `tempfile' and
`copyfile' variables.
Correct the disassembly of the PC-relative immediate argument of the
MIPS16 synthetic LA, LW, DLA and LD instructions and do not mask the
LSB, which in this case is a part of the data address rather than the
ISA bit and has to be fully presented.
opcodes/
* mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
and branches and not synthetic data instructions.
binutils/
* testsuite/binutils-all/mips/mips16-undecoded.d: Adjust the
disassembly of PC-relative LA and LW synthetic instructions.
Complement commit 986e18a5a9fd ("Add a second 'pinfo' member to
mips_opcode to extend number of available bits"),
<https://sourceware.org/ml/binutils/2005-01/msg00261.html>, and annotate
MIPS16 NOP, LA, DLA and the synthetic forms of LD and LW instructions as
aliases. These correspond to MOVE, and the PC-relative ADDIU, DADDIU,
LD and LW hardware instructions respectively.
binutils/
* testsuite/binutils-all/mips/mips16-alias.d: New test.
* testsuite/binutils-all/mips/mips16-noalias.d: New test.
* testsuite/binutils-all/mips/mips16-alias.s: New test source.
* testsuite/binutils-all/mips/mips.exp: Run the new tests.
opcodes/
* mips16-opc.c (AL): New macro.
(mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
of "ld" and "lw" as aliases.
Add ASMACRO instruction support as per the MIPS16e ASE architecture
specifications [1][2], completing MIPS16e instruction set support.
[1] "MIPS32 Architecture for Programmers, Volume IV-a: The MIPS16e
Application-Specific Extension to the MIPS32 Architecture", MIPS
Technologies, Inc., Document Number: MD00076, Revision 2.63, July
16, 2013, Section 4.1 "MIPS16e Instruction Descriptions", p. 65
[2] "MIPS64 Architecture for Programmers, Volume IV-a: The MIPS16e
Application-Specific Extension to the MIPS64 Architecture", MIPS
Technologies, Inc., Document Number: MD00077, Revision 2.60, June
25, 2008, Section 1.1 "MIPS16e Instruction Descriptions", p. 66
include/
* opcode/mips.h: Document `0', `1', `2', `3', `4' and `s'
operand codes.
opcodes/
* mips16-opc.c (decode_mips16_operand): Add `0', `1', `2', `3',
`4' and `s' operand codes.
(mips16_opcodes): Add "asmacro" entry.
binutils/
* testsuite/binutils-all/mips/mips16-extend-insn.d: Update for
ASMACRO support.
gas/
* testsuite/gas/mips/mips16-asmacro.d: New test.
* testsuite/gas/mips/mips16-32@mips16-asmacro.d: New test.
* testsuite/gas/mips/mips16-64@mips16-asmacro.d: New test.
* testsuite/gas/mips/mips16-asmacro.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Identify non-extensible instructions in the MIPS16 opcode table and
disallow their use with the `.e' instruction size suffix in assembly and
do not interpret any EXTEND prefix present as a part of the instruction
in disassembly.
According to all versions of the MIPS16 ASE specifications the following
instructions encodings are not extensible [1][2][3][4][5][6]: I8/MOV32R,
I8/MOVR32, all RRR minor opcodes, all RR minor opcodes except from DSRA
and DSRL, and EXTEND itself, and as from revision 2.50 of the MIPS16e
ASE specifications it has been further clarified what was previously
implied, that non-extesiable instructions when preceded with an EXTEND
prefix must cause a Reserved Instruction exception [3][5].
Therefore in the presence of an EXTEND prefix none of these instructions
are supposed to be handled as extended instructions and supporting these
forms in disassembly causes confusion, and in the case of the RRR major
opcode it also clashes with the ASMACRO encoding.
References:
[1] "Product Description, MIPS16 Application-Specific Extension",
Version 1.3, MIPS Technologies, Inc., 970130, Table 3. "MIPS16
Instruction Set Summary", p. 5
[2] same, Table 5 "RR Minor Opcodes (RR-type instructions)", p.10
[3] "MIPS32 Architecture for Programmers, Volume IV-a: The MIPS16e
Application-Specific Extension to the MIPS32 Architecture", MIPS
Technologies, Inc., Document Number: MD00076, Revision 2.63, July
16, 2013, Section 3.9 "MIPS16e Instruction Summaries", pp. 37-39
[4] same, Section 3.15 "Instruction Bit Encoding", pp. 46-49
[5] "MIPS64 Architecture for Programmers, Volume IV-a: The MIPS16e
Application-Specific Extension to the MIPS64 Architecture", MIPS
Technologies, Inc., Document Number: MD00077, Revision 2.60, June
25, 2008, Section 1.9 "MIPS16e Instruction Summaries", pp. 38-41
[6] same, Section 1.15 "Instruction Bit Encoding", pp. 48-51
include/
* opcode/mips.h (INSN2_SHORT_ONLY): New macro.
gas/
* config/tc-mips.c (is_size_valid_16): Disallow a `.e' suffix
instruction size override for INSN2_SHORT_ONLY opcode table
entries.
* testsuite/gas/mips/mips16-extend-swap.d: Adjust output.
* testsuite/gas/mips/mips16-macro-e.l: Adjust error messages.
* testsuite/gas/mips/mips16-32@mips16-macro-e.l: Adjust error
messages.
* testsuite/gas/mips/mips16e-32@mips16-macro-e.l: Adjust error
messages.
* testsuite/gas/mips/mips16-insn-e.d: New test.
* testsuite/gas/mips/mips16-insn-t.d: New test.
* testsuite/gas/mips/mips16-32@mips16-insn-e.d: New test.
* testsuite/gas/mips/mips16-64@mips16-insn-e.d: New test.
* testsuite/gas/mips/mips16e-32@mips16-insn-e.d: New test.
* testsuite/gas/mips/mips16-32@mips16-insn-t.d: New test.
* testsuite/gas/mips/mips16-64@mips16-insn-t.d: New test.
* testsuite/gas/mips/mips16e-32@mips16-insn-t.d: New test.
* testsuite/gas/mips/mips16-insn-e.l: New stderr output.
* testsuite/gas/mips/mips16-insn-t.l: New stderr output.
* testsuite/gas/mips/mips16-32@mips16-insn-e.l: New stderr
output.
* testsuite/gas/mips/mips16-64@mips16-insn-e.l: New stderr
output.
* testsuite/gas/mips/mips16e-32@mips16-insn-e.l: New stderr
output.
* testsuite/gas/mips/mips16-32@mips16-insn-t.l: New stderr
output.
* testsuite/gas/mips/mips16-64@mips16-insn-t.l: New stderr
output.
* testsuite/gas/mips/mips16e-32@mips16-insn-t.l: New stderr
output.
* testsuite/gas/mips/mips16-insn-e.s: New test source.
* testsuite/gas/mips/mips16-insn-t.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
opcodes/
* mips-dis.c (print_insn_mips16): Disallow EXTEND prefix
matching for INSN2_SHORT_ONLY opcode table entries.
* mips16-opc.c (SH): New macro.
(mips16_opcodes): Set SH in `pinfo2' for non-extensible
instruction entries: "nop", "addu", "and", "break", "cmp",
"daddu", "ddiv", "ddivu", "div", "divu", "dmult", "dmultu",
"drem", "dremu", "dsllv", "dsll", "dsrav", "dsra", "dsrlv",
"dsrl", "dsubu", "exit", "entry", "jalr", "jal", "jr", "j",
"jalrc", "jrc", "mfhi", "mflo", "move", "mult", "multu", "neg",
"not", "or", "rem", "remu", "sllv", "sll", "slt", "sltu",
"srav", "sra", "srlv", "srl", "subu", "xor", "sdbbp", "seb",
"seh", "sew", "zeb", "zeh", "zew" and "extend".
binutils/
* testsuite/binutils-all/mips/mips16-extend-insn.d: New test.
* testsuite/binutils-all/mips/mips16-extend-insn.s: New test
source.
* testsuite/binutils-all/mips/mips.exp: Run the new tests.
Limit MIPS16 instruction disassembly according to the ISA level and ASE
set selected, as with the regular MIPS and microMIPS instruction sets.
Retain the property of `objdump -m mips:16' disassembling all MIPS16
instructions however, regardless of any ISA level recorded in the binary
examined.
To validate the disassembler use the GAS test suite for its convenience
of running tests across multiple ISAs, even though placing the tests in
the binutils test suite would be more appropriate. Adjust the single
binutils test which depends on 64-bit instruction disassembly to have
the ISA level required actually recorded in the binary examined.
opcodes/
* mips-dis.c (mips_arch_choices): Use ISA_MIPS64 rather than
ISA_MIPS3 as the `isa' selection in the `bfd_mach_mips16' entry.
(print_insn_mips16): Check opcode entries for validity against
the ISA level and ASE set selected.
binutils/
* testsuite/binutils-all/mips/mips16-undecoded.s: Use `.module'
rather than `.set' to set the ISA level.
gas/
* testsuite/gas/mips/mips16-sub.d: New test.
* testsuite/gas/mips/mips16-32@mips16-sub.d: New test.
* testsuite/gas/mips/mips16e-32@mips16-sub.d: New test.
* testsuite/gas/mips/mips16e-sub.d: New test.
* testsuite/gas/mips/mips16-32@mips16e-sub.d: New test.
* testsuite/gas/mips/mips16-64@mips16e-sub.d: New test.
* testsuite/gas/mips/mips16e-64-sub.d: New test.
* testsuite/gas/mips/mips16-32@mips16e-64-sub.d: New test.
* testsuite/gas/mips/mips16-64@mips16e-64-sub.d: New test.
* testsuite/gas/mips/mips16e-32@mips16e-64-sub.d: New test.
* testsuite/gas/mips/mips16-sub.s: New test source.
* testsuite/gas/mips/mips16e-sub.s: New test source.
* testsuite/gas/mips/mips16e-64-sub.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Switch to 32-bit MIPS16 opcode table entry interpretation, similar to
how the microMIPS opcode table is handled, for both the `match' and
`mask' fields, removing special casing for JAL and JALX instructions and
their `a' and `i' operand codes throughout, while retaining automatic
processing of extendable opcodes in assembly and disassembly.
In assembly disallow size enforcement suffixes as appropriate: `.t' for
both 32-bit instructions and macros and `.e' for macros only, making
macro handling consistent with the microMIPS instruction set.
In disassembly fully decode EXTEND prefixes prepended to unsupported
instruction encodings (according to the ISA selection) rather than
dumping them as hexadecimal data along with the following instruction,
removing all special casing for the EXTEND prefix and making its
handling rely on its opcode table entry, except where it is considered a
part of an extendable instruction.
include/
* opcode/mips.h (mips_opcode_32bit_p): New inline function.
gas/
* config/tc-mips.c (micromips_insn_length): Use
`mips_opcode_32bit_p'.
(is_size_valid): Adjust description.
(is_size_valid_16): New function.
(validate_mips_insn): Use `mips_opcode_32bit_p' in MIPS16
operand decoding.
(validate_mips16_insn): Remove `a' and `i' operand code special
casing, use `mips_opcode_32bit_p' to determine instruction
width.
(append_insn): Adjust forced MIPS16 instruction size
determination.
(match_mips16_insn): Likewise. Don't shift the instruction's
opcode with the `a' and `i' operand codes. Use
`mips_opcode_32bit_p' in operand decoding.
(match_mips16_insns): Check for forced instruction size's
validity.
(mips16_ip): Don't force instruction size in the `noautoextend'
mode.
* testsuite/gas/mips/mips16-jal-e.d: New test.
* testsuite/gas/mips/mips16-jal-t.d: New test.
* testsuite/gas/mips/mips16-macro-e.d: New test.
* testsuite/gas/mips/mips16-macro-t.d: New test.
* testsuite/gas/mips/mips16-jal-t.l: New stderr output.
* testsuite/gas/mips/mips16-macro-e.l: New stderr output.
* testsuite/gas/mips/mips16-macro-t.l: New stderr output.
* testsuite/gas/mips/mips16-jal-e.s: New test source.
* testsuite/gas/mips/mips16-jal-t.s: New test source.
* testsuite/gas/mips/mips16-macro-e.s: New test source.
* testsuite/gas/mips/mips16-macro-t.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
opcodes/
* mips-dis.c (print_mips16_insn_arg): Always handle `extend' and
`insn' together, with `extend' as the high-order 16 bits.
(match_kind): New enum.
(print_insn_mips16): Rework for 32-bit instruction matching.
Do not dump EXTEND prefixes here.
* mips16-opc.c (mips16_opcodes): Move "extend" entry to the end.
Recode `match' and `mask' fields as 32-bit in absolute "jal" and
"jalx" entries.
binutils/
* testsuite/binutils-all/mips/mips16-extend-noinsn.d: Adjust
test for separate EXTEND prefix disassembly.
Respect any ASE flags recorded in ELF file structures for the purpose of
selecting instructions to be disassembled, preventing code from being
hex-dumped even though having been clearly indicated as valid at the
assembly time. Use date from the MIPS ABI flags structure if present,
and otherwise there may be an MDMX ASE flag set in the ELF file header.
For backwards compatibility only set extra flags and do not clear any,
preserving all previously set by the architecture selected to be
disassembled for.
include/
* elf/mips.h (Elf_Internal_ABIFlags_v0): Also declare struct
typedef as `elf_internal_abiflags_v0'.
bfd/
* bfd-in.h (elf_internal_abiflags_v0): New struct declaration.
(bfd_mips_elf_get_abiflags): New prototype.
* elfxx-mips.c (bfd_mips_elf_get_abiflags): New function.
* bfd-in2.h: Regenerate.
opcodes/
* mips-dis.c (mips_convert_abiflags_ases): New function.
(set_default_mips_dis_options): Also infer ASE flags from ELF
file structures.
binutils/
* testsuite/binutils-all/mips/mips-ase-1.d: New test.
* testsuite/binutils-all/mips/mips-ase-2.d: New test.
* testsuite/binutils-all/mips/mips-ase-3.d: New test.
* testsuite/binutils-all/mips/mips-ase-1.s: New test source.
* testsuite/binutils-all/mips/mips-ase-2.s: New test source.
* testsuite/binutils-all/mips/mips.exp: Run the new tests.
Use a tab rather than a space to separate `extend' and its uninterpreted
argument output, like with regular instructions. Separate hexadecimal
halves of undecoded extended instructions output with a space instead of
presenting them concatenated.
opcodes/
* mips-dis.c (print_insn_mips16): Use a tab rather than a space
to separate `extend' and its uninterpreted argument output.
Separate hexadecimal halves of undecoded extended instructions
output.
binutils/
* testsuite/binutils-all/mips/mips16-extend-noinsn.d: New test.
* testsuite/binutils-all/mips/mips16-extend-noinsn.s: New test
source.
* testsuite/binutils-all/mips/mips.exp: Run the new test.
Complement commit dd8b7c222e0e ("MIPS: mips16e jalrc/jrc opcodes"),
<https://sourceware.org/ml/binutils/2005-07/msg00349.html>, and stop the
disassembler making a delay-slot adjustment for PC-relative operations
following either MIPS16e compact jumps, or undefined RR/J(AL)R(C)
encodings that have the `l' (link) and `ra' (source register is `ra')
bits set both at a time. Adjust code description for accuracy. Add a
suitable test case.
opcodes/
* mips-dis.c (print_mips16_insn_arg): Avoid delay-slot
adjustment for PC-relative operations following MIPS16e compact
jumps or undefined RR/J(AL)R(C) encodings.
binutils/
* testsuite/binutils-all/mips/mips16-pcrel.d: New test.
* testsuite/binutils-all/mips/mips16-pcrel.s: New test source.
* testsuite/binutils-all/mips/mips.exp: Run the new test.
Mixing MIPS16 and microMIPS code in a single binary isn't usually
supported but GAS happily produces such code if requested. However it
is not correctly disassembled even if a symbol table is available and
function symbols are correctly anotated with the ISA mode. This is
because the ELF-header global microMIPS ASE flag takes precedence over
MIPS16 function annotation, causing them to be treated as regular MIPS
code.
Correct the problem by respecting function symbol anotation regardless
of the ELF-header flag.
binutils/
* testsuite/binutils-all/mips/mixed-mips16-micromips.d: New test.
* testsuite/binutils-all/mips/mixed-mips16-micromips.s: New test
source.
* testsuite/binutils-all/mips/mips.exp: Run the new test.
opcodes/
* mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
replacing references to `micromips_ase' throughout.
(_print_insn_mips): Don't use file-level microMIPS annotation to
determine the disassembly mode with the symbol table.
* mips-dis.c (is_compressed_mode_p): Only match symbols from the
section disassembled.
binutils/testsuite/
* binutils-all/mips/mixed-micromips.d: New test.
* binutils-all/mips/mixed-mips16.d: New test.
* binutils-all/mips/mixed-micromips.s: New test source.
* binutils-all/mips/mixed-mips16.s: New test source.
* binutils-all/mips/mips.exp: New file.
