Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
Contributors:
Mary Bennett <mary.bennett682@gmail.com>
Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Pietra Ferreira <pietra.ferreira@embecosm.com>
Charlie Keaney
Jessica Mills
Craig Blackmore <craig.blackmore@embecosm.com>
Simon Cook <simon.cook@embecosm.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
Helene Chelin <helene.chelin@embecosm.com>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvmem`
instruction class.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* doc/c-riscv.texi: Note XCVmem as an additional ISA extension
for CORE-V.
* testsuite/gas/riscv/cv-mem-fail-march.d: New test.
* testsuite/gas/riscv/cv-mem-fail-march.l: New test.
* testsuite/gas/riscv/cv-mem-fail-march.s: New test.
* testsuite/gas/riscv/cv-mem-fail-operand-01.d: New test.
* testsuite/gas/riscv/cv-mem-fail-operand-01.l: New test.
* testsuite/gas/riscv/cv-mem-fail-operand-01.s: New test.
* testsuite/gas/riscv/cv-mem-fail-operand-02.d: New test.
* testsuite/gas/riscv/cv-mem-fail-operand-02.l: New test.
* testsuite/gas/riscv/cv-mem-fail-operand-02.s: New test.
* testsuite/gas/riscv/cv-mem-fail-operand-03.d: New test.
* testsuite/gas/riscv/cv-mem-fail-operand-03.l: New test.
* testsuite/gas/riscv/cv-mem-fail-operand-03.s: New test.
* testsuite/gas/riscv/cv-mem-fail-operand-04.d: New test.
* testsuite/gas/riscv/cv-mem-fail-operand-04.l: New test.
* testsuite/gas/riscv/cv-mem-fail-operand-04.s: New test.
* testsuite/gas/riscv/cv-mem-fail-operand-05.d: New test.
* testsuite/gas/riscv/cv-mem-fail-operand-05.l: New test.
* testsuite/gas/riscv/cv-mem-fail-operand-05.s: New test.
* testsuite/gas/riscv/cv-mem-lbpost.d: New test.
* testsuite/gas/riscv/cv-mem-lbpost.s: New test.
* testsuite/gas/riscv/cv-mem-lbrr.d: New test.
* testsuite/gas/riscv/cv-mem-lbrr.s: New test.
* testsuite/gas/riscv/cv-mem-lbrrpost.d: New test.
* testsuite/gas/riscv/cv-mem-lbrrpost.s: New test.
* testsuite/gas/riscv/cv-mem-lbupost.d: New test.
* testsuite/gas/riscv/cv-mem-lbupost.s: New test.
* testsuite/gas/riscv/cv-mem-lburr.d: New test.
* testsuite/gas/riscv/cv-mem-lburr.s: New test.
* testsuite/gas/riscv/cv-mem-lburrpost.d: New test.
* testsuite/gas/riscv/cv-mem-lburrpost.s: New test.
* testsuite/gas/riscv/cv-mem-lhpost.d: New test.
* testsuite/gas/riscv/cv-mem-lhpost.s: New test.
* testsuite/gas/riscv/cv-mem-lhrr.d: New test.
* testsuite/gas/riscv/cv-mem-lhrr.s: New test.
* testsuite/gas/riscv/cv-mem-lhrrpost.d: New test.
* testsuite/gas/riscv/cv-mem-lhrrpost.s: New test.
* testsuite/gas/riscv/cv-mem-lhupost.d: New test.
* testsuite/gas/riscv/cv-mem-lhupost.s: New test.
* testsuite/gas/riscv/cv-mem-lhurr.d: New test.
* testsuite/gas/riscv/cv-mem-lhurr.s: New test.
* testsuite/gas/riscv/cv-mem-lhurrpost.d: New test.
* testsuite/gas/riscv/cv-mem-lhurrpost.s: New test.
* testsuite/gas/riscv/cv-mem-lwpost.d: New test.
* testsuite/gas/riscv/cv-mem-lwpost.s: New test.
* testsuite/gas/riscv/cv-mem-lwrr.d: New test.
* testsuite/gas/riscv/cv-mem-lwrr.s: New test.
* testsuite/gas/riscv/cv-mem-lwrrpost.d: New test.
* testsuite/gas/riscv/cv-mem-lwrrpost.s: New test.
* testsuite/gas/riscv/cv-mem-sbpost.d: New test.
* testsuite/gas/riscv/cv-mem-sbpost.s: New test.
* testsuite/gas/riscv/cv-mem-sbrr.d: New test.
* testsuite/gas/riscv/cv-mem-sbrr.s: New test.
* testsuite/gas/riscv/cv-mem-sbrrpost.d: New test.
* testsuite/gas/riscv/cv-mem-sbrrpost.s: New test.
* testsuite/gas/riscv/cv-mem-shpost.d: New test.
* testsuite/gas/riscv/cv-mem-shpost.s: New test.
* testsuite/gas/riscv/cv-mem-shrr.d: New test.
* testsuite/gas/riscv/cv-mem-shrr.s: New test.
* testsuite/gas/riscv/cv-mem-shrrpost.d: New test.
* testsuite/gas/riscv/cv-mem-shrrpost.s: New test.
* testsuite/gas/riscv/cv-mem-swpost.d: New test.
* testsuite/gas/riscv/cv-mem-swpost.s: New test.
* testsuite/gas/riscv/cv-mem-swrr.d: New test.
* testsuite/gas/riscv/cv-mem-swrr.s: New test.
* testsuite/gas/riscv/cv-mem-swrrpost.d: New test.
* testsuite/gas/riscv/cv-mem-swrrpost.s: New test.
* testsuite/gas/riscv/march-help.l: Add xcvmem string.
include/ChangeLog:
* opcode/riscv-opc.h: Add corresponding MATCH and MASK macros
for XCVmem.
* opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros
for XCVmem.
(enum riscv_insn_class): Add the XCVmem instruction class.
opcodes/ChangeLog:
* riscv-opc.c: Add XCVmem instructions.
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
Contributors:
Mary Bennett <mary.bennett682@gmail.com>
Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Pietra Ferreira <pietra.ferreira@embecosm.com>
Charlie Keaney
Jessica Mills
Craig Blackmore <craig.blackmore@embecosm.com>
Simon Cook <simon.cook@embecosm.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
Helene Chelin <helene.chelin@embecosm.com>
Nazareno Bruschi <nazareno.bruschi@embecosm.com>
Lin Sinan
include/ChangeLog:
* opcode/riscv-opc.h: Add corresponding MATCH and MASK
macros for XCVbi.
* opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros
for XCVbi.
(enum riscv_insn_class): Add the XCVbi instruction class.
gas/ChangeLog:
* config/tc-riscv.c (validate_riscv_insn): Add the necessary
operands for the extension.
(riscv_ip): Likewise.
* doc/c-riscv.texi: Note XCVbi as an additional ISA extension
for CORE-V.
* testsuite/gas/riscv/cv-bi-beqimm.d: New test.
* testsuite/gas/riscv/cv-bi-beqimm.s: New test.
* testsuite/gas/riscv/cv-bi-bneimm.d: New test.
* testsuite/gas/riscv/cv-bi-bneimm.s: New test.
* testsuite/gas/riscv/cv-bi-fail-march.d: New test.
* testsuite/gas/riscv/cv-bi-fail-march.l: New test.
* testsuite/gas/riscv/cv-bi-fail-march.s: New test.
* testsuite/gas/riscv/cv-bi-fail-operand-01.d: New test.
* testsuite/gas/riscv/cv-bi-fail-operand-01.l: New test.
* testsuite/gas/riscv/cv-bi-fail-operand-01.s: New test.
* testsuite/gas/riscv/cv-bi-fail-operand-02.d: New test.
* testsuite/gas/riscv/cv-bi-fail-operand-02.l: New test.
* testsuite/gas/riscv/cv-bi-fail-operand-02.s: New test.
* testsuite/gas/riscv/cv-bi-fail-operand-03.d: New test.
* testsuite/gas/riscv/cv-bi-fail-operand-03.l: New test.
* testsuite/gas/riscv/cv-bi-fail-operand-03.s: New test.
* testsuite/gas/riscv/march-help.l: Add xcvbi string.
include/ChangeLog:
* opcode/riscv-opc.h: Add corresponding MATCH and MASK
macros for XCVbi.
* opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros
for XCVbi.
(enum riscv_insn_class): Add the XCVbi instruction class.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Add disassembly for new operand.
* riscv-opc.c: Add XCVbi instructions.
R_LARCH_ALIGN (psABI v2.30) requires a symbol index. The symbol is only
created at the first time to handle alignment directive. This means that
all other sections may use this symbol. If the section of this symbol is
discarded, there may be problems. Search it in its own section.
Remove elf_backend_data.is_rela_normal() function added at commit daeda14191.
Co-authored-by: Jinyang He <hejinyang@loongson.cn>
Reported-by: WANG Xuerui <git@xen0n.name>
Link: https://lore.kernel.org/loongarch/2abbb633-a10e-71cc-a5e1-4d9e39074066@loongson.cn/T/#t
The logic to decide if an input relocation for a symbol becomes a
particular kind of output relocation is one of the hard to maintain
parts of the bfd ld backend, since it is partially repeated across
elfNN_aarch64_check_relocs (where dynamic relocations are counted per
symbol and input section),
elfNN_aarch64_late_size_sections (where relocation sections are sized
and GOT offsets assigned),
elfNN_aarch64_relocate_section (where most relocations are applied and
output to a relocation section),
elfNN_aarch64_finish_dynamic_symbol (where some of the GOT
relocations are applied and output).
The DT_RELR support adds another layer to this complexity: after the
output relocation sections are sized, so all dynamic relocations are
accounted (in elfNN_aarch64_late_size_sections), we scan the symbols
and input relocations again to decide which ones become relative
relocations that can be packed. The sizes of the relocation sections
are updated accordingly. This logic must be consistent with the code
that applies the relocs later so each relative relocation is emitted
exactly once: either in .rela.* or packed in .relr.dyn.
Sizing of .relr.dyn is done via elfNN_aarch64_size_relative_relocs that
may be called repeatedly whenever the layout changes since an address
change can affect the size of the packed format. Then the final content
is emitted in elfNN_aarch64_finish_relative_relocs, that is called
after the layout is final and before relocations are applied and
emitted. These hooks are only called if DT_RELR is enabled.
We only pack relative relocs that are known to be aligned in the output
during .relr.dyn sizing, the potentially unaligned relative relocs are
emitted normally (in .rela.*, not packed), because the format requires
aligned addresses.
This was originally reported by Hau Hsu <hau.hsu@sifive.com>.
Similar to commit 51a8a7c2e3
We shouldn't use riscv_elf_append_rela to add dynamic relocs into .rela.iplt
in the riscv_elf_relocate_section when handling ifunc data reloc R_RISCV_32/64.
This just like what did in the riscv_elf_finish_dynamic_symbol.
bfd/
* elfnn-riscv.c (riscv_elf_relocate_section): We shouldn't use
riscv_elf_append_rela to add dynamic relocs into .rela.iplt in the
riscv_elf_relocate_section when handling ifunc data reloc.
ld/
* testsuite/ld-riscv-elf/ifunc-overwrite.s: Updated and renamed.
* testsuite/ld-riscv-elf/ifunc-overwrite-exe.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-overwrite-pic.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-overwrite-pie.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-overwrite.d: Renamed.
This was originally reported by Ard Biesheuvel <ardb@kernel.org>.
The followings are reproduce steps,
https://lore.kernel.org/all/202404260640.9GQVTmrw-lkp@intel.com/T/#u
The segment fault happens in the riscv_elf_finish_dynamic_sections when the
output got section is an ABS. Refer to MIPS code, they added an extra
bfd_is_abs_section check to avoid ABS got, so this seems the right and easier
way to go in the short-term.
bfd/
* elfnn-riscv.c (riscv_elf_finish_dynamic_sections): Set sh_entsize
and fill the got entries only when the got isn't an ABS section, and
the size of got is larger than zero. The similar goes for gotplt,
except we already reported error when the gotplt is an ABS.
ld -z separate-code let .text and .rodata in two different but read only
segment. If the symbol and pc in two segment, the offset from pc to
symbol need to consider segment alignment.
Add a function 'loongarch_two_sections_in_same_segment' to determine
whether two sections are in the same segment.
* https://github.com/riscv/riscv-b/tags
Added standard B extension back, which implies Zba, Zbb and Zbs extensions.
* https://github.com/riscv/riscv-zaamo-zalrsc/tags
Splited standard A extension into two new extensions, Zaamo and Zalrsc.
The A extension implies Zaamo and Zalrsc extensions.
Not sure if we need to do the similar check as i and zicsr/zifencei.
Passed riscv[32|64]-[elf/linux] binutils testcases.
bfd/
* elfxx-riscv.c (riscv_implicit_subsets): Added imply rules
for A and B extensions. The A implies Zaamo and Zalrsc, the
B implies Zba, Zbb and Zbs.
(riscv_supported_std_ext): Supported B extension with v1.0.
(riscv_supported_std_z_ext): Supported Zaamo and Zalrsc with v1.0.
(riscv_multi_subset_supports, riscv_multi_subset_supports_ext): Updated.
include/
* opcode/riscv.h (riscv_insn_class): Removed INSN_CLASS_A, Added
INSN_CLASS_ZAAMO and INSN_CLASS_ZALRSC.
opcodes/
* riscv-opc.c (riscv_opcodes): Splited standard A extension into two
new extensions, Zaamo and Zalrsc.
gas/
* testsuite/gas/riscv/march-imply-a.d: New testcase.
* testsuite/gas/riscv/march-imply-b.d: New testcase.
* testsuite/gas/riscv/attribute-01.d: Updated.
* testsuite/gas/riscv/attribute-02.d: Updated.
* testsuite/gas/riscv/attribute-03.d: Updated.
* testsuite/gas/riscv/attribute-04.d: Updated.
* testsuite/gas/riscv/attribute-05.d: Updated.
* testsuite/gas/riscv/attribute-10.d: Updated.
* testsuite/gas/riscv/mapping-symbols.d: Updated.
* testsuite/gas/riscv/march-imply-g.d: Updated.
* testsuite/gas/riscv/march-imply-unsupported.d: Updated.
* testsuite/gas/riscv/march-ok-reorder.d: Updated.
ld/
* testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated.
* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Updated.
* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Updated.
* testsuite/ld-riscv-elf/attr-merge-user-ext-01.d: Updated.
