Commit Graph

122646 Commits

Author SHA1 Message Date
Alice Carlotti
db36339860 aarch64: Add new test original-missing-misc.d
This test file includes all the remaining untested instructions that
weren't part of a larger group of new or existing tests.
2025-05-09 20:27:21 +01:00
Alice Carlotti
e82ff7a581 aarch64: Add new test mov-wide.d
Only movn was previously untested.
2025-05-09 20:27:21 +01:00
Alice Carlotti
f495cce645 aarch64: Add new test exception-generation.d
svc and dcps* were already tested, but are included here as part of the
same encoding group.
2025-05-09 20:27:21 +01:00
Alice Carlotti
87d10eecf9 aarch64: Add new test conditional-compare.d
The register form of ccmp was already tested.
2025-05-09 20:27:21 +01:00
Alice Carlotti
a240a27f3a aarch64: Add new test branch-cond-pseudos.d
beq, bne, bcs and bcc were already tested, and bge and ble are also used
in scfi tests.
2025-05-09 20:27:21 +01:00
Alice Carlotti
37c162f51a aarch64: Add new test ldst-unpriv.d
All instructions were previously untested.
2025-05-09 20:27:21 +01:00
Alice Carlotti
a56def47ec aarch64: Add new test ldst-extend-general.d
All instructions were previously untested.
2025-05-09 20:27:21 +01:00
Alice Carlotti
c7fa4b95bb aarch64: Add new test dp-general-two-source.d
lsl was already tested but is included here as part of the same encoding
group.
2025-05-09 20:27:21 +01:00
Alice Carlotti
0d0437c738 aarch64: Add new test dp-general-one-source.d
rev16 and the 64-bit rev/rev64 instructions were already tested, but are
included here as part of the same encoding group.
2025-05-09 20:27:21 +01:00
Alice Carlotti
7e5de6cc92 aarch64: Add new test addsub-carry.d
All instructions were previously untested.
2025-05-09 20:27:20 +01:00
Alice Carlotti
4b80ebc02f aarch64: Add new test advsimd-scalar-doubling-mul.d
All instructions were previously untested.
2025-05-09 20:27:20 +01:00
Alice Carlotti
0a5c7a15d5 aarch64: Add new test advsimd-scalar-two-reg-misc.d
sqabs, sqneg, abs and neg were already tested, but are included here as
part of the same encoding group.
2025-05-09 20:27:20 +01:00
Alice Carlotti
c9b4c14636 aarch64: Add new test advsimd-scalar-shift-immediate.d
All instructions were previously untested.
2025-05-09 20:27:20 +01:00
Alice Carlotti
20a594d430 aarch64: Add new test advsimd-scalar-three-same.d
All instructions were previously untested.
2025-05-09 20:27:20 +01:00
Alice Carlotti
6fb41cbeeb aarch64: Add new test advsimd-copy.d
Only smov and the second dup variant were previously untested.  However,
the only test for umov was a disassembly test with -M no-aliases, and
the first dup variant was only tested in assembly in diagnostic.d with
the non-architectural syntax `dup v0.2d, v1.2d[0]`.
2025-05-09 20:27:20 +01:00
Alice Carlotti
5ec5c4e0f4 aarch64: Add new test advsimd-permute.d
All instructions were previously untested.
2025-05-09 20:27:20 +01:00
Alice Carlotti
42ebdfe15d aarch64: Add new test advsimd-modified-immediate.d
All instructions (7 opcode table entries) were previously untested.
2025-05-09 20:27:20 +01:00
Alice Carlotti
1e4e46b650 aarch64: Add new test advsimd-two-reg-misc-hilo.d
All instructions were previously untested.
2025-05-09 20:27:20 +01:00
Alice Carlotti
1bd53f5409 aarch64: Add new test advsimd-two-reg-misc.d
sqabs, abs, not, mvn, sqneg and neg were already tested, and cmeq was
already assembled in an error test (sve-reg-diagnostic.d), but they are
all included here as part of the same encoding group.
2025-05-09 20:27:19 +01:00
Alice Carlotti
75fb645880 aarch64: Add new test advsimd-mul-element.d
All instructions were previously untested.
2025-05-09 20:27:19 +01:00
Alice Carlotti
60d6304505 aarch64: Add new test advsimd-widening-narrowing.d
All instructions were previously untested.
2025-05-09 20:27:19 +01:00
Alice Carlotti
9c4a56f1db aarch64: Add new test advsimd-three-same.d
All instructions except orr/mov were previously untested.
2025-05-09 20:27:19 +01:00
Alice Carlotti
f319a7fcaf aarch64: Add missing widening fmops test
Also remove the valid instructions from the test for invalid
instructions - this meant that the instruction was previously being
tested for assembly but not disassembly.
2025-05-09 20:27:19 +01:00
Alice Carlotti
d34b54505b aarch64: Add tests for fabd, urecpe and ursqrt
Other instructions in the encoding group are tested in advsimd-fp16.d,
so add these instructions to the existing test file.
2025-05-09 20:27:19 +01:00
Alice Carlotti
b8fab5284e aarch64: Add tests for fcvt, fcvtzs and fcvtzu
Other instructions in the encoding group are tested in float-fp16.d, so
add these instructions to the existing test file.
2025-05-09 20:27:19 +01:00
Alice Carlotti
727964dd52 aarch64: Add tests for csdb and eret to system.d 2025-05-09 20:27:19 +01:00
Alice Carlotti
66d60fe883 aarch64: Add test for ands and bics
The other instructions in the encoding group are tested in shifted.d, so
add these to the existing test file.
2025-05-09 20:27:19 +01:00
Alice Carlotti
bf08089443 aarch64: Adjust float-fp16.d test patterns
Adjust the test to match instruction addresses of any length.
2025-05-09 20:27:18 +01:00
Alice Carlotti
7ae0c8a3ea aarch64: Adjust advsimd-fp16.d test patterns
Adjust the test to match instruction addresses of any length, and escape
literal '.' characters for a stricter match.
2025-05-09 20:26:57 +01:00
Alice Carlotti
4c492054d5 aarch64: Adjust shifted.d test patterns
Adjust the test to match any instruction addresses, so that the test can
be extended more easily.
2025-05-09 20:19:30 +01:00
Alice Carlotti
92f7d4ddde aarch64: Eliminate AARCH64_OPND_SVE_ADDR_R
Adjust parsing for AARCH64_OPND_SVE_ADDR_RR{_LSL*} operands to accept
implicit XZR offsets.  Add new AARCH64_OPND_SVE_ADDR_RM{_LSL*} operands
to support instructions where an XZR offset is allowed but must be
specified explicitly.  This allows the removal of the duplicate opcode
table entries using AARCH64_OPND_SVE_ADDR_R.
2025-05-09 20:19:30 +01:00
Alice Carlotti
4250bea744 aarch64: Disallow invalid SVE addressing modes
The fix for PR22988 in 2018 added a new operand AARCH64_OPND_SVE_ADDR_R
to support implicit XZR offsets, but this fix had several flaws that
meant it accepted several invalid addressing modes:

1. The base register type wasn't properly checked when the optional
register offset was omitted.  This meant that
  ldff1b {z1.s}, p1/z,[z1.d]
was parsed as if it were
  ldff1b z1.d, p1/z, [x1.d, xzr].

2. The explicit offset parsing didn't include a shift type, so the new
operand would incorrectly parse
  ldff1h{z0.s}, p0/z, [x0, x0]
as if it were
  ldff1h{z0.s}, p0/z, [x0, x0, lsl #1].

3. Regardless of the above correctness issues, support for implicit
offsets should have been added by amending the operands in the existing
opcode table entries, instead of adding new duplicate table entires.

Issue 1 can be fixed by using an "if" instead of an "else if" in
parse_operands, while issue 2 can be fixed by failing when the first
condition is false.  This patch applies just these two fixes, leaving
issue 3 to be addressed in a subsequent more invasive patch.

The instructions removed from the test sme-5.d are architecturally
invalid. The new tests cover all of the affected ldff1 variants; the
issue also affected SME ZA ld1*/st1* instructions using the same operand
type.
2025-05-09 18:04:37 +01:00
Jerry Zhang Jian
b304edbeb6 RISC-V: Support Zce 1.0
Zce is the extension defined in code-size-reduction

Ref: https://github.com/riscvarchive/riscv-code-size-reduction

Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
2025-05-09 17:53:00 +08:00
Tsukasa OI
ddc654da1a RISC-V: Base for complex extension implications
Thanks to the commit 48558a5e54 ("RISC-V: Allow nested implications for
extensions"), we can write complex extension implications in theory.
However, to actually do that, we need to pass more information to
check_func.

For example, we want to imply 'Zcf' from 'F' if and only if the 'Zce'
extension is also enabled and XLEN is 32.  Passing rps is a way to
enable this.

This commit prepares for such complex extension implications.
2025-05-09 17:52:47 +08:00
Jiawei
0b0e00271c RISC-V: Add augmented hypervisor extension 'sha' support.
The augmented hypervisor extension 'sha'[1] is a new profile-defined extension
that captures the full set of features that are mandated to be supported along
with the H extension.

https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc#rva23s64-profile

bfd/ChangeLog:

		* elfxx-riscv.c: New extension and implies.

gas/ChangeLog:

		* NEWS: New extension.
		* testsuite/gas/riscv/imply.d: New test for sha.
		* testsuite/gas/riscv/imply.s: Ditto.
		* testsuite/gas/riscv/march-help.l: New extension.
2025-05-09 12:30:52 +08:00
Jiawei
433372af69 RISC-V: Add Privileged Architecture 1.13 CSRs.
This patch support RISC-V Privileged Architecture 1.13 CSRs 'medelegh' and
'hedelegh'. More details between 1.12 and 1.13 see [1].

[1] https://github.com/riscv/riscv-isa-manual/blob/main/src/priv-preface.adoc

Version log: Remove gas/po changes.

bfd/ChangeLog:

        * cpu-riscv.c: New option.
        * cpu-riscv.h (enum riscv_spec_class): Ditto.

binutils/ChangeLog:

        * doc/binutils.texi: New option.

gas/ChangeLog:

        * NEWS: Add priv-1.13 support.
        * config/tc-riscv.c: New option.
        * configure: Ditto.
        * configure.ac: Ditto.
        * testsuite/gas/riscv/csr-version-1p10.d: New CSR.
        * testsuite/gas/riscv/csr-version-1p10.l: New warning.
        * testsuite/gas/riscv/csr-version-1p11.d: New CSR.
        * testsuite/gas/riscv/csr-version-1p11.l: New warning.
        * testsuite/gas/riscv/csr-version-1p12.d: New CSR.
        * testsuite/gas/riscv/csr-version-1p12.l: New warning.
        * testsuite/gas/riscv/csr.s: New CSR.
        * testsuite/gas/riscv/attribute-15.d: New test.
        * testsuite/gas/riscv/attribute-16.d: New test.
        * testsuite/gas/riscv/csr-version-1p13.d: New test.
        * testsuite/gas/riscv/csr-version-1p13.l: New test.

include/ChangeLog:

        * opcode/riscv-opc.h (CSR_MEDELEGH): New CSR.
        (CSR_HEDELEGH): Ditto.
        (DECLARE_CSR): Ditto.
2025-05-09 12:28:42 +08:00
Chao-ying Fu
617ead3c20 RISC-V: Added vendor extensions, xmipscbop, xmipscmov, xmipsexectl and xmipslsp
Spec:
https://mips.com/wp-content/uploads/2025/03/P8700-F_Programmers_Reference_Manual_Rev1.82_3-19-2025.pdf

Added MIPS vendor extensions, xmipscbop, xmipscmov, xmipsexectl and xmipslsp
with verison 1.0.

Passed binutils testsuites of targets elf32/elf64/linux32/linux64.

Signed-off-by: Jovan Dmitrović <jovan.dmitrovic@htecgroup.com>
Signed-off-by: Chao-ying Fu <cfu@wavecomp.com>
2025-05-09 12:24:15 +08:00
GDB Administrator
4480aaee57 Automatic date update in version.in 2025-05-09 00:00:09 +00:00
Tom Tromey
09828ac2f1 Change substitute_path_component to use std::string
This changes substitute_path_component to use std::string and
std::string_view, simplifying it greatly and removing some manual
memory management.

Approved-By: Simon Marchi <simon.marchi@efficios.com>
2025-05-08 11:13:28 -06:00
Tom Tromey
440b7ed4a4 Move substitute_path_component
This moves substitute_path_component out of utils.c.  I considered
making a new file for this (still could if someone wants that), but
since the only caller is in auto-load.c, I moved it there instead.

I've also moved the tests into auto-load.c as well.  This way
substitute_path_component can be static.

Approved-By: Simon Marchi <simon.marchi@efficios.com>
2025-05-08 11:13:28 -06:00
GDB Administrator
88d0753018 Automatic date update in version.in 2025-05-08 00:00:11 +00:00
Alan Modra
4aaf663ded windres: buffer overflow
bin_to_res_menuexitems can be called with random data offsets (and thus
remaining lengths), confusing code that expects 4-byte aligned data.
Prevent an item length adjustment for alignment exceeding the
remaining length and then overflowing.
2025-05-08 09:26:56 +09:30
Alan Modra
76fd7455e3 Remove unnecessary use of pragma once in pr25618 test 2025-05-08 09:26:56 +09:30
Jens Remus
bc1b43ef7a s390: Fix format specifier for VR in disassembler
Vector register (VR) numbers are unsigned.  Use format specifier %u
instead of %i.

Reported-by: Florian Krohm <flo2030@eich-krohm.de>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2025-05-07 17:17:10 +02:00
GDB Administrator
7659033dee Automatic date update in version.in 2025-05-07 00:00:33 +00:00
Tom Tromey
1edb555c59 Do not set yydebug in cp-name-parser.y
This reverts the change to cp-name-parser.y, avoiding a TSan report.

Approved-By: Simon Marchi <simon.marchi@efficios.com>
2025-05-06 14:58:56 -06:00
Tom Tromey
5479d3d404 Remove kfail from templates.exp
templates.exp has one remaining kfail.  However, the output in
question has been stabilized ever since the cp-name-parser.y work --
the test just wasn't updated.

Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=8617
Reviewed-By: Keith Seitz <keiths@redhat.com>
2025-05-06 14:48:57 -06:00
Tom Tromey
f2bd3d64ae Rewrite bug references in templates.exp
templates.exp has many kfails that refer to old GNATS bug numbers.
This patch updates them to refer to Bugzilla instead.

Reviewed-By: Keith Seitz <keiths@redhat.com>
2025-05-06 14:48:57 -06:00
Andrew Burgess
998165ba99 Revert "gdb: support zero inode in generate-core-file command"
This reverts commit 1e21c846c2.

This change was causing unexpected mappings to be included in the core
files generated by GDB, which was triggering warnings when GDB opened
a core file, like this:

  warning: Can't open file [stack] during file-backed mapping note processing

  warning: Can't open file [vvar] during file-backed mapping note processing

For now I'm reverting the above commit and will come to the list again
when I have a solution that addresses the original issue without also
including the unexpected mappings.
2025-05-06 16:55:44 +01:00
Tom Tromey
420d030e88 Handle field with dynamic bit offset
I discovered that GCC emitted incorrect DWARF for the test case
included in this patch.  Eric wrote a fix for GCC, but then he found
that gdb crashed on the resulting file.

This test has a field that is at a non-constant bit offset from the
start of the type.  DWARF 5 does not allow for this situation (I've
sent a report to the DWARF list), but DWARF 3 did allow for this via a
combination of an expression for the byte offset and then the use of
DW_AT_bit_offset.  This looks like:

 <5><117a>: Abbrev Number: 17 (DW_TAG_member)
    <117b>   DW_AT_name        : (indirect string, offset: 0x1959): another_field
...
    <1188>   DW_AT_bit_offset  : 6
    <1189>   DW_AT_data_member_location: 6 byte block: 99 3d 1 0 0 22 	(DW_OP_call4: <0x1193>; DW_OP_plus)
...
 <3><1193>: Abbrev Number: 2 (DW_TAG_dwarf_procedure)
    <1194>   DW_AT_location    : 15 byte block: 97 94 1 37 1a 32 1e 23 7 38 1b 31 1c 23 3 	(DW_OP_push_object_address; DW_OP_deref_size: 1; DW_OP_lit7; DW_OP_and; DW_OP_lit2; DW_OP_mul; DW_OP_plus_uconst: 7; DW_OP_lit8; DW_OP_div; DW_OP_lit1; DW_OP_minus; DW_OP_plus_uconst: 3)

Now, that combination is not fully general, in that the bit offset
must be a constant -- only the byte offset may really vary.  However,
I couldn't come up with a situation where full generality is needed,
mainly because GNAT won't seem to pack fields into the padding of a
variable-length array.

Meanwhile, the reason for the gdb crash is that the code handling
DW_AT_bit_offset assumes that the byte offset is a constant.  This
causes an assertion failure.

This patch arranges for DW_AT_bit_offset to be applied during field
resolution, when needed.
2025-05-06 09:01:55 -06:00