This commit adds 'Ssstateen' extension, which is a supervisor-visible view
of the 'Smstateen' extension. It means, this extension implements sstateen*
and hstateen* CSRs of the 'Smstateen' extension.
Note that 'Smstateen' extension itself is unchanged but due to
implementation simplicity, it is implemented so that 'Smstateen' implies
'Ssstateen' (just like 'M' implies 'Zmmul').
This is based on the latest version of RISC-V Profiles
(version 0.9-draft, Frozen):
<226b7f6430>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_implicit_subsets): Update implication rules.
(riscv_supported_std_s_ext) Add 'Ssstateen' extension.
gas/ChangeLog:
* config/tc-riscv.c (enum riscv_csr_class): Rename
CSR_CLASS_SMSTATEEN_AND_H{,_32} to CSR_CLASS_SSSTATEEN_...
Add CSR_CLASS_SSSTATEEN.
(riscv_csr_address): Support new/renamed CSR classes.
* testsuite/gas/riscv/csr.s: Add 'Ssstateen' extension to comment.
* testsuite/gas/riscv/csr-version-1p9p1.l: Reflect changes to
error messages.
* testsuite/gas/riscv/csr-version-1p10.l: Likewise.
* testsuite/gas/riscv/csr-version-1p11.l: Likewise.
* testsuite/gas/riscv/csr-version-1p12.l: Likewise.
* testsuite/gas/riscv/ssstateen-csr.s: Test for 'Ssstateen' CSRs.
* testsuite/gas/riscv/ssstateen-csr.d: Likewise.
* testsuite/gas/riscv/smstateen-csr-s.d: Test to make sure that
supervisor/hypervisor part of 'Smstateen' CSRs are accessible from
'RV32IH_Smstateen', not just from 'RV32IH_Ssstateen' that is tested
in ssstateen-csr.d.
include/ChangeLog:
* opcode/riscv-opc.h: Update DECLARE_CSR declarations with
new CSR classes.
This patch adds the XTheadInt extension, which provides interrupt
stack management instructions.
The XTheadFmv extension is documented in the RISC-V toolchain
contentions:
https://github.com/riscv-non-isa/riscv-toolchain-conventions
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
This patch adds the XTheadFmv extension, which allows to access the
upper 32 bits of a double-precision floating-point register in RV32.
The XTheadFmv extension is documented in the RISC-V toolchain
contentions:
https://github.com/riscv-non-isa/riscv-toolchain-conventions
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
This patch adds support for SFrame in readelf and objdump. The arguments
of --sframe are optional for both readelf and objdump.
include/ChangeLog:
* sframe-api.h (dump_sframe): New function declaration.
ChangeLog:
* binutils/Makefile.am: Add dependency on libsframe for
readelf and objdump.
* binutils/Makefile.in: Regenerate.
* binutils/doc/binutils.texi: Document --sframe=[section].
* binutils/doc/sframe.options.texi: New file.
* binutils/objdump.c: Add support for SFrame format.
* binutils/readelf.c: Likewise.
* include/sframe-api.h: Add new API for dumping .sframe
section.
* libsframe/Makefile.am: Add sframe-dump.c.
* libsframe/Makefile.in: Regenerate.
* libsframe/sframe-dump.c: New file.
The linker merges all the input .sframe sections. When merging, the
linker verifies that all the input .sframe sections have the same
abi/arch.
The linker uses libsframe library to perform key actions on the
.sframe sections - decode, read, and create output data. This
implies buildsystem changes to make and install libsframe before
libbfd.
The linker places the output .sframe section in a new segment of its
own: PT_GNU_SFRAME. A new segment is not added, however, if the
generated .sframe section is empty.
When a section is discarded from the final link, the corresponding
entries in the .sframe section for those functions are also deleted.
The linker sorts the SFrame FDEs on start address by default and sets
the SFRAME_F_FDE_SORTED flag in the .sframe section.
This patch also adds support for generation of SFrame unwind
information for the .plt* sections on x86_64. SFrame unwind info is
generated for IBT enabled PLT, lazy/non-lazy PLT.
The existing linker option --no-ld-generated-unwind-info has been
adapted to include the control of whether .sframe unwind information
will be generated for the linker generated sections like PLT.
Changes to the linker script have been made as necessary.
ChangeLog:
* Makefile.def: Add install dependency on libsframe for libbfd.
* Makefile.in: Regenerated.
* bfd/Makefile.am: Add elf-sframe.c
* bfd/Makefile.in: Regenerated.
* bfd/bfd-in2.h (SEC_INFO_TYPE_SFRAME): Regenerated.
* bfd/configure: Regenerate.
* bfd/configure.ac: Add elf-sframe.lo.
* bfd/elf-bfd.h (struct sframe_func_bfdinfo): New struct.
(struct sframe_dec_info): Likewise.
(struct sframe_enc_info): Likewise.
(struct elf_link_hash_table): New member for encoded .sframe
object.
(struct output_elf_obj_tdata): New member.
(elf_sframe): New access macro.
(_bfd_elf_set_section_sframe): New declaration.
* bfd/elf.c (get_segment_type): Handle new segment
PT_GNU_SFRAME.
(bfd_section_from_phdr): Likewise.
(get_program_header_size): Likewise.
(_bfd_elf_map_sections_to_segments): Likewise.
* bfd/elf64-x86-64.c (elf_x86_64_link_setup_gnu_properties): Add
contents to the .sframe sections or .plt* entries.
* bfd/elflink.c (elf_section_ignore_discarded_relocs): Handle
SEC_INFO_TYPE_SFRAME.
(_bfd_elf_default_action_discarded): Handle .sframe section.
(elf_link_input_bfd): Merge .sframe section.
(bfd_elf_final_link): Write the output .sframe section.
(bfd_elf_discard_info): Handle discarding .sframe section.
* bfd/elfxx-x86.c (_bfd_x86_elf_size_dynamic_sections): Create
.sframe section for .plt and .plt.sec.
(_bfd_x86_elf_finish_dynamic_sections): Handle .sframe from
.plt* sections.
* bfd/elfxx-x86.h (PLT_SFRAME_FDE_START_OFFSET): New
definition.
(SFRAME_PLT0_MAX_NUM_FRES): Likewise.
(SFRAME_PLTN_MAX_NUM_FRES): Likewise.
(struct elf_x86_sframe_plt): New structure.
(struct elf_x86_link_hash_table): New member.
(struct elf_x86_init_table): New members for .sframe
creation.
* bfd/section.c: Add new definition SEC_INFO_TYPE_SFRAME.
* binutils/readelf.c (get_segment_type): Handle new segment
PT_GNU_SFRAME.
* ld/ld.texi: Update documentation for
--no-ld-generated-unwind-info.
* ld/scripttempl/elf.sc: Support .sframe sections.
* ld/Makefile.am (TESTSFRAMELIB): Use it.
(check-DEJAGNU): Likewise.
* ld/Makefile.in: Regenerated.
* ld/configure.ac (TESTSFRAMELIB): Set to the .so or .a like TESTBFDLIB.
* ld/configure: Regenerated.
* bfd/elf-sframe.c: New file.
include/ChangeLog:
* elf/common.h (PT_GNU_SFRAME): New definition.
* elf/internal.h (struct elf_segment_map): Handle new segment
type PT_GNU_SFRAME.
ld/testsuite/ChangeLog:
* ld/testsuite/ld-bootstrap/bootstrap.exp: Add SFRAMELIB.
* ld/testsuite/ld-aarch64/aarch64-elf.exp: Add new test
sframe-simple-1.
* ld/testsuite/ld-aarch64/sframe-bar.s: New file.
* ld/testsuite/ld-aarch64/sframe-foo.s: Likewise.
* ld/testsuite/ld-aarch64/sframe-simple-1.d: Likewise.
* ld/testsuite/ld-sframe/sframe-empty.d: New test.
* ld/testsuite/ld-sframe/sframe-empty.s: New file.
* ld/testsuite/ld-sframe/sframe.exp: New testsuite.
* ld/testsuite/ld-x86-64/sframe-bar.s: New file.
* ld/testsuite/ld-x86-64/sframe-foo.s: Likewise.
* ld/testsuite/ld-x86-64/sframe-simple-1.d: Likewise.
* ld/testsuite/ld-x86-64/sframe-plt-1.d: Likewise.
* ld/testsuite/ld-x86-64/sframe-simple-1.d: Likewise.
* ld/testsuite/ld-x86-64/x86-64.exp: Add new tests -
sframe-simple-1, sframe-plt-1.
* ld/testsuite/lib/ld-lib.exp: Add new proc to check if
assembler supports SFrame section.
* ld/testsuite/ld-sframe/discard.d: New file.
* ld/testsuite/ld-sframe/discard.ld: Likewise.
* ld/testsuite/ld-sframe/discard.s: Likewise.
libsframe is a library that allows you to:
- decode a .sframe section
- probe and inspect a .sframe section
- encode (and eventually write) a .sframe section.
This library is currently being used by the linker, readelf, objdump.
This library will also be used by the SFrame unwinder which is still
to be upstream'd.
The file include/sframe-api.h defines the user-facing APIs for decoding,
encoding and probing .sframe sections. A set of error codes together
with their error message strings are also defined.
Endian flipping is performed automatically at read and write time, if
cross-endianness is detected.
ChangeLog:
* Makefile.def: Add libsframe as new module with its
dependencies.
* Makefile.in: Regenerated.
* binutils/Makefile.am: Add libsframe.
* binutils/Makefile.in: Regenerated.
* configure: Regenerated
* configure.ac: Add libsframe to host_libs.
* libsframe/Makefile.am: New file.
* libsframe/Makefile.in: New file.
* libsframe/aclocal.m4: New file.
* libsframe/config.h.in: New file.
* libsframe/configure: New file.
* libsframe/configure.ac: New file.
* libsframe/sframe-error.c: New file.
* libsframe/sframe-impl.h: New file.
* libsframe/sframe.c: New file.
include/ChangeLog:
* sframe-api.h: New file.
testsuite/ChangeLog:
* libsframe/testsuite/Makefile.am: New file.
* libsframe/testsuite/Makefile.in: Regenerated.
* libsframe/testsuite/libsframe.decode/Makefile.am: New
file.
* libsframe/testsuite/libsframe.decode/Makefile.in:
Regenerated.
* libsframe/testsuite/libsframe.decode/decode.exp: New file.
* libsframe/testsuite/libsframe.encode/Makefile.am:
Likewise.
* libsframe/testsuite/libsframe.encode/Makefile.in:
Regenerated.
* libsframe/testsuite/libsframe.encode/encode.exp: New file.
* libsframe/testsuite/libsframe.encode/encode-1.c: Likewise.
* libsframe/testsuite/libsframe.decode/be-flipping.c: Likewise.
* libsframe/testsuite/libsframe.decode/frecnt-1.c: Likewise.
* libsframe/testsuite/libsframe.decode/frecnt-2.c: Likewise.
* libsframe/testsuite/libsframe.decode/DATA-BE: New file.
* libsframe/testsuite/libsframe.decode/DATA1: Likewise.
* libsframe/testsuite/libsframe.decode/DATA2: Likewise.
The header sframe.h defines the SFrame format.
The SFrame format is the Simple Frame format. It can be used to
represent the minimal necessary unwind information required for
backtracing. The current version supports AMD64 and AARCH64.
More details of the SFrame format are included in the documentation
of the header file in this patch.
include/ChangeLog:
* sframe.h: New file.
This hasn't been used by gdb in decades, and doesn't make sense with
a standalone sim program/library where the ABI is fixed. So punt it
to simplify the code.
When reading/writing arbitrary data to the system's memory, the unsigned
char pointer type doesn't make that much sense. Switch it to void so we
align a bit with standard C library read/write functions, and to avoid
having to sprinkle casts everywhere.
When reading/writing arbitrary data to the system's memory, the unsigned
char pointer type doesn't make that much sense. Switch it to void so we
align a bit with standard C library read/write functions, and to avoid
having to sprinkle casts everywhere.
"-Wdeprecated-declarations" warning option can be helpful to track
deprecated function delarations but sometimes we need to disable this
warning for a good reason.
DIAGNOSTIC_IGNORE_DEPRECATED_DECLARATIONS is an existing macro but only
defined on Clang. Since "-Wdeprecated-declarations" is also available on
GCC (>= 3.4.0), this commit adds equivalent definition as Clang.
__GNUC__ and __GNUC_MINOR__ are not checked because this header file seems
to assume GCC >= 4.6 (with "GCC diagnostic push/pop").
include/ChangeLog:
* diagnostics.h (DIAGNOSTIC_IGNORE_DEPRECATED_DECLARATIONS):
Define also on GCC.
Allows aarch64-pe to be targeted natively, not having to use objcopy to convert it from ELF to PE.
Based on initial work by Jedidiah Thompson
Co-authored-by: Jedidiah Thompson <wej22007@outlook.com>
Co-authored-by: Zac Walker <zac.walker@linaro.org>
It has bothered me for a long time that we have disabled LSP (and SPE)
tests. Also the LSP test comment indicating there is something wrong
with get_powerpc_dialect. I don't think there is. Decoding of a VLE
instruction depends on whether the processor is in VLE mode (some
processors support both VLE and standard PPC) which we flag per
section with SHF_PPC_VLE for decoding when disassembling.
Background: Some versions of powerpc e200 have "Lightweight Signal
Processing" support, examples being e200z215 and e200z425. As far as
I can tell, LSP and SPE are mutually exclusive. This seems to be
borne out by insn encoding, for example LSP "zvaddih" and SPE "evaddw"
have the same encoding. So none of the processor descriptions in
ppc_opts ought to have both PPC_OPCODE_LSP and PPC_OPCODE_SPE/2, if we
want disassembly to work. I also could not find anything to suggest
that the LSP insns are enabled only in VLE mode, which means the LSP
insns should not be in vle_opcodes.
Fix all this by moving the LSP insns to their own table, and add a new
e200z2 cpu entry with LSP support, removing LSP from -me200z4 and from
-mvle. (Yes, I know, as I said above some of the e200z4 processors
have LSP. Others have SPE. It's hard to choose good options. Think
of z2 as meaning earlier, z4 as later.) Also add -mlsp to allow
adding the LSP insn set.
include/
* opcode/ppc.h (lsp_opcodes, lsp_num_opcodes): Declare.
(LSP_OP_TO_SEG): Define.
binutils/
* doc/binutils.texi: Update ppc docs.
gas/
* config/tc-ppc.c (ppc_setup_opcodes): Add lsp opcodes to ppc_hash.
* doc/c-ppc.texi: Document e200 and lsp.
* testsuite/gas/ppc/lsp-checks.d: Assemble with -me200z2.
* testsuite/gas/ppc/lsp.d: Likewise, disassembly too.
* testsuite/gas/ppc/ppc.exp: Don't xfail lsp test.
opcodes/
* ppc-dis.c (ppc_opts): Add e200z2 and lsp. Don't set
PPC_OPCODE_LSP for e200z4 or vle.
(ppc_parse_cpu): Mutually exclude LSP and SPE.
(LSP_OPCD_SEGS): Define.
(lsp_opcd_indices): New array.
(disassemble_init_powerpc): Init lsp_opcd_indices.
(lookup_lsp): New function.
(print_insn_powerpc): Call it.
* ppc-opc.c: Include libiberty.h for ARRAY_SIZE and use throughout.
(vle_opcodes): Move LSP opcodes to..
(lsp_opcodes): ..here, and sort.
(lsp_num_opcodes): New.
This is a part of small tidying (declare tables in riscv-opc.c).
include/ChangeLog:
* opcode/riscv.h (riscv_rm, riscv_pred_succ): Move declarations to
opcodes/riscv-opc.c. New non-static definitions.
opcodes/ChangeLog:
* riscv-opc.c (riscv_rm, riscv_pred_succ): Move from
include/opcode/riscv.h. Add description.
Because riscv_insn_length started to support instructions up to 176-bit,
we need to increase packet buffer size to 176-bit in size.
include/ChangeLog:
* opcode/riscv.h (RISCV_MAX_INSN_LEN): Max instruction length for
use in buffer size.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_riscv): Increase buffer size for max
176-bit length instructions.
FreeBSD's kernel has recently added two new ELF auxiliary vector
entries to describe the location of the user stack for the initial
thread in a process.
This change displays the proper name and description of these entries
in 'info auxv'.
This patch adds support for the Zawrs ISA extension
("wrs.nto" and "wrs.sto" instructions).
The specification can be found here:
https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadMemPair extension, a collection of T-Head specific
two-GP-register memory operations.
The 'th' prefix and the "XTheadMemPair" extension are documented in a PR
for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadMemIdx extension, a collection of T-Head specific
GPR memory access instructions.
The 'th' prefix and the "XTheadMemIdx" extension are documented in a PR
for the RISC-V toolchain conventions ([1]).
In total XTheadCmo introduces the following 44 instructions
(BU,HU,WU only for loads (zero-extend instead of sign-extend)):
* {L,S}{D,W,WU,H,HU,B,BU}{IA,IB} rd, rs1, imm5, imm2
* {L,S}R{D,W,WU,H,HU,B,BU} rd, rs1, rs2, imm2
* {L,S}UR{D,W,WU,H,HU,B,BU} rd, rs1, rs2, imm2
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadFMemIdx extension, a collection of
T-Head-specific floating-point memory access instructions.
The 'th' prefix and the "XTheadFMemIdx" extension are documented
in a PR for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadMac extension, a collection of
T-Head-specific multiply-accumulate instructions.
The 'th' prefix and the "XTheadMac" extension are documented
in a PR for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadCondMov extension, a collection of
T-Head-specific conditional move instructions.
The 'th' prefix and the "XTheadCondMov" extension are documented
in a PR for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XThead{Ba,Bb,Bs} extensions, a collection of
T-Head-specific bitmanipulation instructions.
The 'th' prefix and the "XThead{Ba,Bb,Bs}" extension are documented
in a PR for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
This patch introduces support for arbitrary signed or unsigned immediate
encoding formats. The formats have the form "XsN@S" and "XuN@S" with N
being the number of bits and S the LSB position.
For example an immediate field of 5 bytes that encodes a signed value
and is stored in the bits 24-20 of the instruction word can use the
format specifier "Xs5@20".
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadSync extension, a collection of
T-Head-specific multi-processor synchronization instructions.
The 'th' prefix and the "XTheadSync" extension are documented in a PR
for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadCmo extension, a collection of T-Head specific
cache management operations.
The 'th' prefix and the "XTheadCmo" extension are documented in a PR
for the RISC-V toolchain conventions ([1]).
In total XTheadCmo introduces the following 21 instructions:
* DCACHE.{C,CI,I}ALL
* DCACHE.{C,CI,I}{PA,VA,SW} rs1
* DCACHE.C{PAL1,VAL1} rs1
* ICACHE.I{ALL,ALLS}
* ICACHE.I{PA,VA} rs1
* L2CACHE.{C,CI,I}ALL
Contrary to Zicbom, the XTheadCmo instructions don't have a constant
displacement, therefore we have a different syntax for the arguments.
To clarify this is intended behaviour, there is a set of negative test
for Zicbom-style arguments in x-thead-cmo-fail.s.
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
v2:
- Add missing DECLARE_INSN() list
- Fix ordering
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
"-Wunused-but-set-variable" warning option can be helpful to track variables
that are written but not read thereafter. But it can be harmful if some of
the code is auto-generated and we have no ways to deal with it.
The particular example is Bison-generated code.
The new DIAGNOSTIC_IGNORE_UNUSED_BUT_SET_VARIABLE macro can be helpful on
such cases. A typical use of this macro is to place this macro before the
end of user prologues on Bison (.y) files.
include/ChangeLog:
* diagnostics.h (DIAGNOSTIC_IGNORE_UNUSED_BUT_SET_VARIABLE): New.
User-defined warnings (on Clang, "-Wuser-defined-warnings") can be harmful
if we have specified "-Werror" and we have no control to disable the warning
ourself. The particular example is Gnulib.
Gnulib generates a warning if the system version of certain functions
are used (to redirect the developer to use Gnulib version). However,
it can be harmful if we cannot easily replace them (e.g. the target is in
the standard C++ library).
The new DIAGNOSTIC_IGNORE_USER_DEFINED_WARNINGS macro can be helpful on such
cases. A typical use of this macro is to place this macro before including
certain system headers.
include/ChangeLog:
* diagnostics.h (DIAGNOSTIC_IGNORE_USER_DEFINED_WARNINGS): New.
I don't see why include/gdb/fileio.h is placed there. It's not
installed by "make install", and it's not included by anything outside
of gdb/gdbserver/gdbsupport.
Move its content back to gdbsupport/fileio.h. I have omitted the bits
inside an `#if 0`, since it's obviously not used, as well as the
"limits" constants, which are also unused.
Change-Id: I6fbc2ea10fbe4cfcf15f9f76006b31b99c20e5a9
This patch support ZTSO extension. It will turn on the tso flag for elf_flags
once we have enabled Ztso extension. This is intended to implement v0.1 of
the proposed specification which can be found in Chapter 25 of,
https://github.com/riscv/riscv-isa-manual/releases/download/draft-20220723-10eea63/riscv-spec.pdf.
bfd\ChangeLog:
* elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Set TSO flag.
* elfxx-riscv.c: Add Ztso's arch.
binutils\ChangeLog:
* readelf.c (get_machine_flags): Set TSO flag.
gas\ChangeLog:
* config/tc-riscv.c (riscv_set_tso): Ditto.
(riscv_set_arch): Ditto.
* testsuite/gas/riscv/ztso.d: New test.
include\ChangeLog:
* elf/riscv.h (EF_RISCV_TSO): Ditto.
The -mfuture and -Mfuture options which are used for adding potential
new ISA instructions were not documented. They also lacked a bitmask
so new instructions could not be enabled by those options. Fixed.
binutils/
* doc/binutils.texi: Document -Mfuture.
gas/
* config/tc-ppc.c: Document -mfuture
* doc/c-ppc.texi: Likewise.
include/
* opcode/ppc.h (PPC_OPCODE_FUTURE): Define.
opcodes/
* ppc-dis.c (ppc_opts) <future>: Use it.
* ppc-opc.c (FUTURE): Define.
This is paired with "gdb: Add non-enum disassembler options".
There is a portable mechanism for disassembler options and used on some
architectures:
- ARC
- Arm
- MIPS
- PowerPC
- RISC-V
- S/390
However, it only supports following forms:
- [NAME]
- [NAME]=[ENUM_VALUE]
Valid values for [ENUM_VALUE] must be predefined in
disasm_option_arg_t.values. For instance, for -M cpu=[CPU] in ARC
architecture, opcodes/arc-dis.c builds valid CPU model list from
include/elf/arc-cpu.def.
In this commit, it adds following format:
- [NAME]=[ARBITRARY_VALUE] (cannot contain "," though)
This is identified by NULL value of disasm_option_arg_t.values
(normally, this is a non-NULL pointer to a NULL-terminated list).
include/ChangeLog:
* dis-asm.h (disasm_option_arg_t): Update comment of values
to allow non-enum disassembler options.
opcodes/ChangeLog:
* riscv-dis.c (print_riscv_disassembler_options): Support
non-enum disassembler options on printing disassembler help.
* arc-dis.c (print_arc_disassembler_options): Likewise.
* mips-dis.c (print_mips_disassembler_options): Likewise.
Three-part patch set from Tsukasa OI to support zmmul in assembler.
The 'Zmmul' is a RISC-V extension consisting of only multiply instructions
(a subset of 'M' which has multiply and divide instructions).
bfd/
* elfxx-riscv.c (riscv_implicit_subsets): Add 'Zmmul' implied by 'M'.
(riscv_supported_std_z_ext): Add 'Zmmul' extension.
(riscv_multi_subset_supports): Add handling for new instruction class.
gas/
* testsuite/gas/riscv/attribute-09.d: Updated implicit 'Zmmul' by 'M'.
* testsuite/gas/riscv/option-arch-02.d: Likewise.
* testsuite/gas/riscv/m-ext.s: New test.
* testsuite/gas/riscv/m-ext-32.d: New test (RV32).
* testsuite/gas/riscv/m-ext-64.d: New test (RV64).
* testsuite/gas/riscv/zmmul-32.d: New expected output.
* testsuite/gas/riscv/zmmul-64.d: Likewise.
* testsuite/gas/riscv/m-ext-fail-xlen-32.d: New test (failure
by using RV64-only instructions in RV32).
* testsuite/gas/riscv/m-ext-fail-xlen-32.l: Likewise.
* testsuite/gas/riscv/m-ext-fail-zmmul-32.d: New failure test
(RV32 + Zmmul but with no M).
* testsuite/gas/riscv/m-ext-fail-zmmul-32.l: Likewise.
* testsuite/gas/riscv/m-ext-fail-zmmul-64.d: New failure test
(RV64 + Zmmul but with no M).
* testsuite/gas/riscv/m-ext-fail-zmmul-64.l: Likewise.
* testsuite/gas/riscv/m-ext-fail-noarch-64.d: New failure test
(no Zmmul or M).
* testsuite/gas/riscv/m-ext-fail-noarch-64.l: Likewise.
include/
* opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_ZMMUL.
ld/
* testsuite/ld-riscv-elf/attr-merge-arch-01.d: We don't care zmmul in
these testcases, so just replaced m by a.
* testsuite/ld-riscv-elf/attr-merge-arch-01a.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-01b.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-02a.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-03a.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-user-ext-01.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i2p1_a2p0.s: Renamed.
* testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i2p1_a2p1.s: Renamed.
opcodes/
* riscv-opc.c (riscv_opcodes): Updated multiply instructions to zmmul.
svstep and svshape instructions subtract 1 before encoding some of the
operands. Obviously zero is not supported for these operands. Whilst
PPC_OPERAND_PLUS1 fits perfectly to mark that maximal value should be
incremented, there is no flag which marks the fact that zero values are
not allowed. This patch adds a new flag, PPC_OPERAND_NONZERO, for this
purpose.
This patch adds support for LibreSOC machine and SVP64 extension flag
for PowerPC architecture. SV (Simple-V) is a strict RISC-paradigm
Scalable Vector Extension for the Power ISA. SVP64 is the 64-bit
Prefixed instruction format implementing SV. Funded by NLnet through EU
Grants No: 825310 and 825322, SV is in DRAFT form and is to be publicly
submitted via the OpenPOWER Foundation ISA Working Group via the
newly-created External RFC Process.
For more details, visit https://libre-soc.org.
They were legacy relocation types copied from other ports. The related
-fvtable-gc was removed from GCC in 2003.
The associated assembler directives (.vtable_inherit and .vtable_entry)
have never been supported by the RISC-V port. Remove related ld code.
Link: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/323
This adds support for efi-loongarch64 by virtue of adding a new PEI target
pei-loongarch64. This is not a full target and only exists to support EFI at
this time.
This means that this target does not support relocation processing and is mostly
a container format. This format has been added to elf based loongarch64 targets
such that efi images can be made natively on Linux.
However this target is not valid for use with gas but only with objcopy.
We should't limit addresses to 32-bits for 64-bit vma, otherwise there will be
"RVA truncated" error when using objcopy on loongarch64.
With these changes the resulting file is recognized as an efi image.
Any magic number is based on the Microsoft PE specification [1].
The test results are as follows:
$ make check-binutils RUNTESTFLAGS='loongarch64.exp'
PASS: Check if efi app format is recognized
$ objdump -h -f tmpdir/loongarch64copy.o
tmpdir/loongarch64copy.o: file format pei-loongarch64
architecture: Loongarch64, flags 0x00000132:
EXEC_P, HAS_SYMS, HAS_LOCALS, D_PAGED
start address 0x0000000000000000
Sections:
Idx Name Size VMA LMA File off Algn
0 .text 0000003c 00000000200000b0 00000000200000b0 00000200 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
[1] https://docs.microsoft.com/en-us/windows/win32/debug/pe-format
bfd:
* .gitignore (pe-loongarch64igen.c): New.
* Makefile.am (pei-loongarch64.lo, pe-loongarch64igen.lo, pei-loongarch64.c,
pe-loongarch64igen.c): Add support.
* Makefile.in: Likewise.
* bfd.c (bfd_get_sign_extend_vma): Add pei-loongarch64.
* coff-loongarch64.c: New file.
* coffcode.h (coff_set_arch_mach_hook, coff_set_flags,
coff_write_object_contents) Add loongarch64 (loongarch64_pei_vec) support.
* config.bfd: Likewise.
* configure: Likewise.
* configure.ac: Likewise.
* libpei.h (GET_OPTHDR_IMAGE_BASE, PUT_OPTHDR_IMAGE_BASE,
GET_OPTHDR_SIZE_OF_STACK_RESERVE, PUT_OPTHDR_SIZE_OF_STACK_RESERVE,
GET_OPTHDR_SIZE_OF_STACK_COMMIT, PUT_OPTHDR_SIZE_OF_STACK_COMMIT,
GET_OPTHDR_SIZE_OF_HEAP_RESERVE, PUT_OPTHDR_SIZE_OF_HEAP_RESERVE,
GET_OPTHDR_SIZE_OF_HEAP_COMMIT, PUT_OPTHDR_SIZE_OF_HEAP_COMMIT,
GET_PDATA_ENTRY, _bfd_peLoongArch64_bfd_copy_private_bfd_data_common,
_bfd_peLoongArch64_bfd_copy_private_section_data,
_bfd_peLoongArch64_get_symbol_info, _bfd_peLoongArch64_only_swap_filehdr_out,
_bfd_peLoongArch64_print_private_bfd_data_common,
_bfd_peLoongArch64i_final_link_postscript,
_bfd_peLoongArch64i_only_swap_filehdr_out, _bfd_peLoongArch64i_swap_aouthdr_in,
_bfd_peLoongArch64i_swap_aouthdr_out, _bfd_peLoongArch64i_swap_aux_in,
_bfd_peLoongArch64i_swap_aux_out, _bfd_peLoongArch64i_swap_lineno_in,
_bfd_peLoongArch64i_swap_lineno_out, _bfd_peLoongArch64i_swap_scnhdr_out,
_bfd_peLoongArch64i_swap_sym_in, _bfd_peLoongArch64i_swap_sym_out,
_bfd_peLoongArch64i_swap_debugdir_in, _bfd_peLoongArch64i_swap_debugdir_out,
_bfd_peLoongArch64i_write_codeview_record,
_bfd_peLoongArch64i_slurp_codeview_record,
_bfd_peLoongArch64_print_ce_compressed_pdata): New.
* peXXigen.c (_bfd_XXi_swap_aouthdr_in, _bfd_XXi_swap_aouthdr_out,
_bfd_XXi_swap_scnhdr_out, pe_print_pdata, _bfd_XX_print_private_bfd_data_common,
_bfd_XX_bfd_copy_private_section_data, _bfd_XXi_final_link_postscript):
Support COFF_WITH_peLoongArch64,
* pei-loongarch64.c: New file.
* peicode.h (coff_swap_scnhdr_in, pe_ILF_build_a_bfd, pe_ILF_object_p):
Support COFF_WITH_peLoongArch64.
(jtab): Add dummy entry that traps.
* targets.c (loongarch64_pei_vec): New.
binutils
* testsuite/binutils-all/loongarch64/loongarch64.exp: New file.
* testsuite/binutils-all/loongarch64/pei-loongarch64.d: New test.
* testsuite/binutils-all/loongarch64/pei-loongarch64.s: New test.
include
* coff/loongarch64.h: New file.
* coff/pe.h (IMAGE_FILE_MACHINE_LOONGARCH64): New.
Signed-off-by: Youling Tang <tangyouling@loongson.cn>
This commit enables disassembler styling for AArch64. After this
commit it is possible to have objdump style AArch64 disassembler
output (using --disassembler-color option). Once the required GDB
patches are merged, GDB will also style the disassembler output.
The changes to support styling are mostly split between two files
opcodes/aarch64-dis.c and opcodes/aarch64-opc.c.
The entry point for the AArch64 disassembler can be found in
aarch64-dis.c, this file handles printing the instruction mnemonics,
and assembler directives (e.g. '.byte', '.word', etc). Some operands,
mostly relating to assembler directives are also printed from this
file. This commit changes all of this to pass through suitable
styling information.
However, for most "normal" instructions, the instruction operands are
printed using a two step process. From aarch64-dis.c, in the
print_operands function, the function aarch64_print_operand is called,
this function is in aarch64-opc.c, and converts an instruction operand
into a string. Then, back in print_operands (aarch64-dis.c), the
operand string is printed.
Unfortunately, the string returned by aarch64_print_operand can be
quite complex, it will include syntax elements, like '[' and ']', in
addition to register names and immediate values. In some cases, a
single operand will expand into what will appear (to the user) as
multiple operands separated with a ','.
This makes the task of styling more complex, all these different
components need to by styled differently, so we need to get the
styling information out of aarch64_print_operand in some way.
The solution that I propose here is similar to the solution that I
used for the i386 disassembler.
Currently, aarch64_print_operand uses snprintf to write the operand
text into a buffer provided by the caller.
What I propose is that we pass an extra argument to the
aarch64_print_operand function, this argument will be a structure, the
structure contains a callback function and some state.
When aarch64_print_operand needs to format part of its output this can
be done by using the callback function within the new structure, this
callback returns a string with special embedded markers that indicate
which mode should be used for each piece of text. Back in
aarch64-dis.c we can spot these special style markers and use this to
split the disassembler output up and apply the correct style to each
piece.
To make aarch64-opc.c clearer a series of new static functions have
been added, e.g. 'style_reg', 'style_imm', etc. Each of these
functions formats a piece of text in a different style, 'register' and
'immediate' in this case.
Here's an example taken from aarch64-opc.c of the new functions in
use:
snprintf (buf, size, "[%s, %s]!",
style_reg (styler, base),
style_imm (styler, "#%d", opnd->addr.offset.imm));
The aarch64_print_operand function is also called from the assembler
to aid in printing diagnostic messages. Right now I have no plans to
add styling to the assembler output, and so, the callback function
used in the assembler ignores the styling information and just returns
an plain string.
I've used the source files in gas/testsuite/gas/aarch64/ for testing,
and have manually gone through and checked that the styling looks
reasonable, however, I'm not an AArch64 expert, so it is possible that
the odd piece is styled incorrectly. Please point out any mistakes
I've made.
With objdump disassembler color turned off, there should be no change
in the output after this commit.
When adding libopcodes disassembler styling support for AArch64, it
feels like the results would be improved by having a new sub-mnemonic
style. This will be used in cases like:
add w16, w7, w1, uxtb #2
^^^^----- Here
And:
cinc w0, w1, ne
^^----- Here
This commit just adds the new style, and prepares objdump to handle
the style. A later commit will add AArch64 styling, and will actually
make use of the style.
As this style is currently unused, there should be no user visible
changes after this commit.
Some R_LARCH_64 in section .eh_frame will to generate
R_LARCH_NONE, we change relocation to R_LARCH_32_PCREL
from R_LARCH_64 in setction .eh_frame and not generate
dynamic relocation for R_LARCH_32_PCREL.
Add New relocate type R_LARCH_32_PCREL for .eh_frame.
include/elf/
loongarch.h
bfd/
bfd/bfd-in2.h
libbfd.h
reloc.c
elfxx-loongarch.c
elfnn-loongarch.c
gas/config/
tc-loongarch.c
binutils/
readelf.c
ld/testsuite/ld-elf/
eh5.d
