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x86: drop NoAVX insn attribute

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To avoid issues like that addressed by 6e3e5c9e4181 ("x86: extend SSE
check to PCLMULQDQ, AES, and GFNI insns"), base the check on opcode
attributes and operand types.
This commit is contained in:
Jan Beulich
2022-01-06 14:19:56 +01:00
parent f0db6fb6d9
commit ffb864501e
5 changed files with 4536 additions and 4536 deletions
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36
gas/config/tc-i386.c
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@ -4986,23 +4986,27 @@ md_assemble (char *line)
return;
if (sse_check != check_none
&& !i.tm.opcode_modifier.noavx
&& !i.tm.cpu_flags.bitfield.cpuavx
&& !i.tm.cpu_flags.bitfield.cpuavx512f
&& (i.tm.cpu_flags.bitfield.cpusse
|| i.tm.cpu_flags.bitfield.cpusse2
|| i.tm.cpu_flags.bitfield.cpusse3
|| i.tm.cpu_flags.bitfield.cpussse3
|| i.tm.cpu_flags.bitfield.cpusse4_1
|| i.tm.cpu_flags.bitfield.cpusse4_2
|| i.tm.cpu_flags.bitfield.cpupclmul
|| i.tm.cpu_flags.bitfield.cpuaes
|| i.tm.cpu_flags.bitfield.cpusha
|| i.tm.cpu_flags.bitfield.cpugfni))
/* The opcode space check isn't strictly needed; it's there only to
bypass the logic below when easily possible. */
&& t->opcode_modifier.opcodespace >= SPACE_0F
&& t->opcode_modifier.opcodespace <= SPACE_0F3A
&& !i.tm.cpu_flags.bitfield.cpusse4a
&& !is_any_vex_encoding (t))
{
(sse_check == check_warning
? as_warn
: as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
bool simd = false;
for (j = 0; j < t->operands; ++j)
{
if (t->operand_types[j].bitfield.class == RegMMX)
break;
if (t->operand_types[j].bitfield.class == RegSIMD)
simd = true;
}
if (j >= t->operands && simd)
(sse_check == check_warning
? as_warn
: as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
}
if (i.tm.opcode_modifier.fwait)