espressif/binutils-gdb
1
0
Fork 0
mirror of https://github.com/espressif/binutils-gdb.git synced 2025-06-23 03:29:47 +08:00
Code Issues Packages Projects Releases Wiki Activity

sim: frv: fix ambiguous else compiler warnings

Browse Source 
Add explicit braces to if bodies when the body is another if/else
to fix a bunch of compiler warnings.
This commit is contained in:
Mike Frysinger
2021-06-26 23:59:03 -04:00
parent 9df51d7c47
commit ff68b4b5b1
4 changed files with 43 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
sim/frv/ChangeLog
View File

@ -1,3 +1,9 @@
2021-06-27 Mike Frysinger <vapier@gentoo.org>
* frv.c (frvbf_shift_left_arith_saturate): Add braces to if statement.
* profile-fr500.c (adjust_float_register_busy): Likewise.
* profile-fr550.c (adjust_float_register_busy): Likewise.
2021-06-22 Mike Frysinger <vapier@gentoo.org> 2021-06-22 Mike Frysinger <vapier@gentoo.org>
* configure: Regenerate. * configure: Regenerate.

2
sim/frv/frv.c
View File

@ -1182,10 +1182,12 @@ frvbf_shift_left_arith_saturate (SIM_CPU *current_cpu, SI arg1, SI arg2)
/* Signed shift by 31 or greater saturates by definition. */ /* Signed shift by 31 or greater saturates by definition. */
if (arg2 >= 31) if (arg2 >= 31)
{
if (arg1 > 0) if (arg1 > 0)
return (SI) 0x7fffffff; return (SI) 0x7fffffff;
else else
return (SI) 0x80000000; return (SI) 0x80000000;
}
/* OK, arg2 is between 1 and 31. */ /* OK, arg2 is between 1 and 31. */
neg_arg1 = (arg1 < 0); neg_arg1 = (arg1 < 0);

6
sim/frv/profile-fr500.c
View File

@ -158,23 +158,29 @@ adjust_float_register_busy (SIM_CPU *cpu, INT in_FRi, INT in_FRj, INT out_FRk,
then their latency will be less than previously recorded. then their latency will be less than previously recorded.
See Table 13-13 in the LSI. */ See Table 13-13 in the LSI. */
if (in_FRi >= 0) if (in_FRi >= 0)
{
if (use_is_fpop (cpu, in_FRi)) if (use_is_fpop (cpu, in_FRi))
decrease_FR_busy (cpu, in_FRi, cycles); decrease_FR_busy (cpu, in_FRi, cycles);
else else
enforce_full_fr_latency (cpu, in_FRi); enforce_full_fr_latency (cpu, in_FRi);
}
if (in_FRj >= 0 && in_FRj != in_FRi) if (in_FRj >= 0 && in_FRj != in_FRi)
{
if (use_is_fpop (cpu, in_FRj)) if (use_is_fpop (cpu, in_FRj))
decrease_FR_busy (cpu, in_FRj, cycles); decrease_FR_busy (cpu, in_FRj, cycles);
else else
enforce_full_fr_latency (cpu, in_FRj); enforce_full_fr_latency (cpu, in_FRj);
}
if (out_FRk >= 0 && out_FRk != in_FRi && out_FRk != in_FRj) if (out_FRk >= 0 && out_FRk != in_FRi && out_FRk != in_FRj)
{
if (use_is_fpop (cpu, out_FRk)) if (use_is_fpop (cpu, out_FRk))
decrease_FR_busy (cpu, out_FRk, cycles); decrease_FR_busy (cpu, out_FRk, cycles);
else else
enforce_full_fr_latency (cpu, out_FRk); enforce_full_fr_latency (cpu, out_FRk);
} }
}
/* Latency of floating point registers may be less than recorded when followed /* Latency of floating point registers may be less than recorded when followed
by another floating point insn. */ by another floating point insn. */

4
sim/frv/profile-fr550.c
View File

@ -225,12 +225,14 @@ adjust_float_register_busy (SIM_CPU *cpu,
for (i = 0; i < iwidth; ++i) for (i = 0; i < iwidth; ++i)
{ {
if (! REG_OVERLAP (in_FRi + i, 1, out_FRk, kwidth)) if (! REG_OVERLAP (in_FRi + i, 1, out_FRk, kwidth))
{
if (use_is_fr_load (cpu, in_FRi + i)) if (use_is_fr_load (cpu, in_FRi + i))
decrease_FR_busy (cpu, in_FRi + i, 1); decrease_FR_busy (cpu, in_FRi + i, 1);
else else
enforce_full_fr_latency (cpu, in_FRi + i); enforce_full_fr_latency (cpu, in_FRi + i);
} }
} }
}
if (in_FRj >= 0) if (in_FRj >= 0)
{ {
@ -238,12 +240,14 @@ adjust_float_register_busy (SIM_CPU *cpu,
{ {
if (! REG_OVERLAP (in_FRj + i, 1, in_FRi, iwidth) if (! REG_OVERLAP (in_FRj + i, 1, in_FRi, iwidth)
&& ! REG_OVERLAP (in_FRj + i, 1, out_FRk, kwidth)) && ! REG_OVERLAP (in_FRj + i, 1, out_FRk, kwidth))
{
if (use_is_fr_load (cpu, in_FRj + i)) if (use_is_fr_load (cpu, in_FRj + i))
decrease_FR_busy (cpu, in_FRj + i, 1); decrease_FR_busy (cpu, in_FRj + i, 1);
else else
enforce_full_fr_latency (cpu, in_FRj + i); enforce_full_fr_latency (cpu, in_FRj + i);
} }
} }
}
if (out_FRk >= 0) if (out_FRk >= 0)
{ {