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gdb/riscv: Extend instruction decode to cover more instructions

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Extends the instruction decoder used during prologue scan and software
single step to cover more instructions.  These instructions are
encountered when running the current GDB testsuite with the DWARF
stack unwinders turned off.

gdb/ChangeLog:

	* riscv-tdep.c (riscv_insn::decode): Decode c.addi4spn, c.sd,
	c.sw, c.swsp, and c.sdsp.
This commit is contained in:
Andrew Burgess
2018-08-16 14:56:19 +01:00
parent 0b3f9efc04
commit ff3a05b3f8
2 changed files with 43 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
gdb/ChangeLog
View File

@ -1,3 +1,8 @@
2018-08-30 Andrew Burgess <andrew.burgess@embecosm.com>
* riscv-tdep.c (riscv_insn::decode): Decode c.addi4spn, c.sd,
c.sw, c.swsp, and c.sdsp.
2018-08-30 Andrew Burgess <andrew.burgess@embecosm.com> 2018-08-30 Andrew Burgess <andrew.burgess@embecosm.com>
* riscv-tdep.c (struct riscv_inferior_data): Delete. * riscv-tdep.c (struct riscv_inferior_data): Delete.

40
gdb/riscv-tdep.c
View File

@ -972,6 +972,31 @@ private:
m_imm.s = EXTRACT_STYPE_IMM (ival); m_imm.s = EXTRACT_STYPE_IMM (ival);
} }
/* Helper for DECODE, decode 16-bit CS-type instruction. The immediate
encoding is different for each CS format instruction, so extracting
the immediate is left up to the caller, who should pass the extracted
immediate value through in IMM. */
void decode_cs_type_insn (enum opcode opcode, ULONGEST ival, int imm)
{
m_opcode = opcode;
m_imm.s = imm;
m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S);
m_rs2 = decode_register_index_short (ival, OP_SH_CRS2S);
}
/* Helper for DECODE, decode 16-bit CSS-type instruction. The immediate
encoding is different for each CSS format instruction, so extracting
the immediate is left up to the caller, who should pass the extracted
immediate value through in IMM. */
void decode_css_type_insn (enum opcode opcode, ULONGEST ival, int imm)
{
m_opcode = opcode;
m_imm.s = imm;
m_rs1 = RISCV_SP_REGNUM;
/* Not a compressed register number in this case. */
m_rs2 = decode_register_index (ival, OP_SH_CRS2);
}
/* Helper for DECODE, decode 32-bit U-type instruction. */ /* Helper for DECODE, decode 32-bit U-type instruction. */
void decode_u_type_insn (enum opcode opcode, ULONGEST ival) void decode_u_type_insn (enum opcode opcode, ULONGEST ival)
{ {
@ -1165,14 +1190,25 @@ riscv_insn::decode (struct gdbarch *gdbarch, CORE_ADDR pc)
m_rd = m_rs1 = decode_register_index (ival, OP_SH_RD); m_rd = m_rs1 = decode_register_index (ival, OP_SH_RD);
m_imm.s = EXTRACT_RVC_ADDI16SP_IMM (ival); m_imm.s = EXTRACT_RVC_ADDI16SP_IMM (ival);
} }
else if (is_c_addi4spn_insn (ival))
{
m_opcode = ADDI;
m_rd = decode_register_index_short (ival, OP_SH_CRS2S);
m_rs1 = RISCV_SP_REGNUM;
m_imm.s = EXTRACT_RVC_ADDI4SPN_IMM (ival);
}
else if (is_c_lui_insn (ival)) else if (is_c_lui_insn (ival))
m_opcode = OTHER; m_opcode = OTHER;
/* C_SD and C_FSW have the same opcode. C_SD is RV64 and RV128 only, /* C_SD and C_FSW have the same opcode. C_SD is RV64 and RV128 only,
and C_FSW is RV32 only. */ and C_FSW is RV32 only. */
else if (xlen != 4 && is_c_sd_insn (ival)) else if (xlen != 4 && is_c_sd_insn (ival))
m_opcode = OTHER; decode_cs_type_insn (SD, ival, EXTRACT_RVC_LD_IMM (ival));
else if (is_c_sw_insn (ival)) else if (is_c_sw_insn (ival))
m_opcode = OTHER; decode_cs_type_insn (SW, ival, EXTRACT_RVC_LW_IMM (ival));
else if (is_c_swsp_insn (ival))
decode_css_type_insn (SW, ival, EXTRACT_RVC_SWSP_IMM (ival));
else if (xlen != 4 && is_c_sdsp_insn (ival))
decode_css_type_insn (SW, ival, EXTRACT_RVC_SDSP_IMM (ival));
/* C_JR and C_MV have the same opcode. If RS2 is 0, then this is a C_JR. /* C_JR and C_MV have the same opcode. If RS2 is 0, then this is a C_JR.
So must try to match C_JR first as it ahs more bits in mask. */ So must try to match C_JR first as it ahs more bits in mask. */
else if (is_c_jr_insn (ival)) else if (is_c_jr_insn (ival))