espressif/binutils-gdb
1
0
Fork 0
mirror of https://github.com/espressif/binutils-gdb.git synced 2025-06-18 08:38:10 +08:00
Code Issues Packages Projects Releases Wiki Activity

aarch64: Add DSB instruction Armv8.7-a variant

Browse Source 
This patch adds new variant (nXS) of DSB memory barrier instruction
available in Armv8.7-a. New nXS variant has different encoding in
comparison with pre Armv8.7-a DSB memory barrier variant thus new
instruction and new operand was added.

DSB memory nXS barrier variant specifies the limitation on the barrier
operation. Allowed values are:

	DSB SYnXS|#28
	DSB ISHnXS|#24
	DSB NSHnXS|#20
	DSB OSHnXS|#16

Please note that till now,  for barriers, barrier operation was encoded in
4-bit unsigned immediate CRm field (in the range 0 to 15).
For DSB memory nXS barrier variant, barrier operation is a 5-bit unsigned
assembly instruction immediate, encoded in instruction in two bits CRm<3:2>:

		CRm<3:2>  #imm
		  00       16
		  01       20
		  10       24
		  11       28

This patch extends current AArch64 barrier instructions with above mapping.

Notable patch changes include:
+ New DSB memory barrier variant encoding for Armv8.7-a.
+ New operand BARRIER_DSB_NXS for above instruction in order to
distinguish between existing and new DSB instruction flavour.
+ New set of DSB nXS barrier options.
+ New instruction inserter and extractor map between instruction
immediate 5-bit value and 2-bit CRm field of the instruction itself (see
FLD_CRm_dsb_nxs).
+ Regeneration of aarch64-[asm|dis|opc]-2.c files.
+ Test cases to cover new instruction assembling and disassembling.

For more details regarding DSB memory barrier instruction and its
Armv8.7-a flavour please refer to Arm A64 Instruction set documentation
for Armv8-A architecture profile, see document pages 132-133 of [0].

	[0]: https://developer.arm.com/docs/ddi0596/i

gas/ChangeLog:

2020-10-23  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>

	* NEWS: Docs update.
	* config/tc-aarch64.c (parse_operands): Add
	AARCH64_OPND_BARRIER_DSB_NXS handler.
	(md_begin): Add content of aarch64_barrier_dsb_nxs_options to
	aarch64_barrier_opt_hsh hash.
	* testsuite/gas/aarch64/system-4-invalid.d: New test.
	* testsuite/gas/aarch64/system-4-invalid.l: New test.
	* testsuite/gas/aarch64/system-4-invalid.s: New test.
	* testsuite/gas/aarch64/system-4.d: New test.
	* testsuite/gas/aarch64/system-4.s: New test.

include/ChangeLog:

2020-10-23  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>

	* opcode/aarch64.h (enum aarch64_opnd): New operand
	AARCH64_OPND_BARRIER_DSB_NXS.
	(aarch64_barrier_dsb_nxs_options): Declare DSB nXS options.

opcodes/ChangeLog:

2020-10-23  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>

	* aarch64-asm.c (aarch64_ins_barrier_dsb_nxs): New inserter.
	* aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): New inserter
	ins_barrier_dsb_nx.
	* aarch64-dis.c (aarch64_ext_barrier_dsb_nxs): New extractor.
	* aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): New extractor
	ext_barrier_dsb_nx.
	* aarch64-opc.c (aarch64_print_operand): New options table
	aarch64_barrier_dsb_nxs_options.
	* aarch64-opc.h (enum aarch64_field_kind): New field name FLD_CRm_dsb_nxs.
	* aarch64-tbl.h (struct aarch64_opcode): Define DSB nXS barrier
	Armv8.7-a instruction.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.
This commit is contained in:
Przemyslaw Wirkus
2020-10-28 14:01:36 +00:00
parent 8926e54e3a
commit fd195909ce
18 changed files with 1623 additions and 1456 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
gas/NEWS
View File

@ -21,6 +21,8 @@
* Add support for Armv8-R and Armv8.7-A AArch64. * Add support for Armv8-R and Armv8.7-A AArch64.
* Add support for DSB memory nXS barrier instruction for Armv8.7 AArch64.
* Add support for Intel TDX instructions. * Add support for Intel TDX instructions.
* Add support for Intel Key Locker instructions. * Add support for Intel Key Locker instructions.

47
gas/config/tc-aarch64.c
View File

@ -6686,12 +6686,49 @@ parse_operands (char *str, const aarch64_opcode *opcode)
backtrack_pos = 0; backtrack_pos = 0;
goto failure; goto failure;
} }
if (val != PARSE_FAIL
&& operands[i] == AARCH64_OPND_BARRIER)
{
/* Regular barriers accept options CRm (C0-C15).
DSB nXS barrier variant accepts values > 15. */
po_imm_or_fail (0, 15);
}
/* This is an extension to accept a 0..15 immediate. */ /* This is an extension to accept a 0..15 immediate. */
if (val == PARSE_FAIL) if (val == PARSE_FAIL)
po_imm_or_fail (0, 15); po_imm_or_fail (0, 15);
info->barrier = aarch64_barrier_options + val; info->barrier = aarch64_barrier_options + val;
break; break;
case AARCH64_OPND_BARRIER_DSB_NXS:
val = parse_barrier (&str);
if (val != PARSE_FAIL)
{
/* DSB nXS barrier variant accept only <option>nXS qualifiers. */
if (!(val == 16 || val == 20 || val == 24 || val == 28))
{
set_syntax_error (_("the specified option is not accepted in DSB"));
/* Turn off backtrack as this optional operand is present. */
backtrack_pos = 0;
goto failure;
}
}
else
{
/* DSB nXS barrier variant accept 5-bit unsigned immediate, with
possible values 16, 20, 24 or 28 , encoded as val<3:2>. */
if (! parse_constant_immediate (&str, &val, imm_reg_type))
goto failure;
if (!(val == 16 || val == 20 || val == 24 || val == 28))
{
set_syntax_error (_("immediate value must be 16, 20, 24, 28"));
goto failure;
}
}
/* Option index is encoded as 2-bit value in val<3:2>. */
val = (val >> 2) - 4;
info->barrier = aarch64_barrier_dsb_nxs_options + val;
break;
case AARCH64_OPND_PRFOP: case AARCH64_OPND_PRFOP:
val = parse_pldop (&str); val = parse_pldop (&str);
/* This is an extension to accept a 0..31 immediate. */ /* This is an extension to accept a 0..31 immediate. */
@ -8782,6 +8819,16 @@ md_begin (void)
(void *) (aarch64_barrier_options + i)); (void *) (aarch64_barrier_options + i));
} }
for (i = 0; i < ARRAY_SIZE (aarch64_barrier_dsb_nxs_options); i++)
{
const char *name = aarch64_barrier_dsb_nxs_options[i].name;
checked_hash_insert (aarch64_barrier_opt_hsh, name,
(void *) (aarch64_barrier_dsb_nxs_options + i));
/* Also hash the name in the upper case. */
checked_hash_insert (aarch64_barrier_opt_hsh, get_upper_str (name),
(void *) (aarch64_barrier_dsb_nxs_options + i));
}
for (i = 0; i < ARRAY_SIZE (aarch64_prfops); i++) for (i = 0; i < ARRAY_SIZE (aarch64_prfops); i++)
{ {
const char* name = aarch64_prfops[i].name; const char* name = aarch64_prfops[i].name;

3
gas/testsuite/gas/aarch64/system-4-invalid.d Normal file
View File

@ -0,0 +1,3 @@
#name: Invalid DSB memory nXS barrier variant
#source: system-4-invalid.s
#error_output: system-4-invalid.l

11
gas/testsuite/gas/aarch64/system-4-invalid.l Normal file
View File

@ -0,0 +1,11 @@
.*: Assembler messages:
.*: Error: immediate value out of range 0 to 15 at operand 1 -- `dsb #17'
.*: Error: immediate value out of range 0 to 15 at operand 1 -- `dsb #18'
.*: Error: immediate value out of range 0 to 15 at operand 1 -- `dsb #19'
.*: Error: immediate value out of range 0 to 15 at operand 1 -- `dsb #21'
.*: Error: immediate value out of range 0 to 15 at operand 1 -- `dsb #22'
.*: Error: immediate value out of range 0 to 15 at operand 1 -- `dsb #23'
.*: Error: immediate value out of range 0 to 15 at operand 1 -- `dsb #25'
.*: Error: immediate value out of range 0 to 15 at operand 1 -- `dsb #26'
.*: Error: immediate value out of range 0 to 15 at operand 1 -- `dsb #27'
.*: Error: immediate value out of range 0 to 15 at operand 1 -- `dsb #29'

16
gas/testsuite/gas/aarch64/system-4-invalid.s Normal file
View File

@ -0,0 +1,16 @@
/* Armv8.7-a DSB memory nXS barrier variant. */
.arch armv8.7-a
dsb #17
dsb #18
dsb #19
dsb #21
dsb #22
dsb #23
dsb #25
dsb #26
dsb #27
dsb #29

16
gas/testsuite/gas/aarch64/system-4.d Normal file
View File

@ -0,0 +1,16 @@
#name: DSB memory nXS barrier variant
#objdump: -dr
.*: file format .*
Disassembly of section \.text:
0+ <.*>:
.*: d503323f dsb oshnxs
.*: d503363f dsb nshnxs
.*: d5033a3f dsb ishnxs
.*: d5033e3f dsb synxs
.*: d503323f dsb oshnxs
.*: d503363f dsb nshnxs
.*: d5033a3f dsb ishnxs
.*: d5033e3f dsb synxs

12
gas/testsuite/gas/aarch64/system-4.s Normal file
View File

@ -0,0 +1,12 @@
/* Armv8.7-a DSB memory nXS barrier variant. */
.arch armv8.7-a
dsb #16
dsb #20
dsb #24
dsb #28
dsb oshnxs
dsb nshnxs
dsb ishnxs
dsb synxs

2
include/opcode/aarch64.h
View File

@ -317,6 +317,7 @@ enum aarch64_opnd
AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */ AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */
AARCH64_OPND_SYSREG_SR, /* System register RCTX operand. */ AARCH64_OPND_SYSREG_SR, /* System register RCTX operand. */
AARCH64_OPND_BARRIER, /* Barrier operand. */ AARCH64_OPND_BARRIER, /* Barrier operand. */
AARCH64_OPND_BARRIER_DSB_NXS, /* Barrier operand for DSB nXS variant. */
AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */ AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
AARCH64_OPND_PRFOP, /* Prefetch operation. */ AARCH64_OPND_PRFOP, /* Prefetch operation. */
AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */ AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */
@ -949,6 +950,7 @@ struct aarch64_name_value_pair
extern const struct aarch64_name_value_pair aarch64_operand_modifiers []; extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
extern const struct aarch64_name_value_pair aarch64_barrier_options [16]; extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
extern const struct aarch64_name_value_pair aarch64_barrier_dsb_nxs_options [4];
extern const struct aarch64_name_value_pair aarch64_prfops [32]; extern const struct aarch64_name_value_pair aarch64_prfops [32];
extern const struct aarch64_name_value_pair aarch64_hint_options []; extern const struct aarch64_name_value_pair aarch64_hint_options [];

289
opcodes/aarch64-asm-2.c
View File

@ -426,14 +426,14 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 1184: /* movz */ case 1184: /* movz */
value = 1184; /* --> movz. */ value = 1184; /* --> movz. */
break; break;
case 1239: /* autibsp */ case 1240: /* autibsp */
case 1238: /* autibz */ case 1239: /* autibz */
case 1237: /* autiasp */ case 1238: /* autiasp */
case 1236: /* autiaz */ case 1237: /* autiaz */
case 1235: /* pacibsp */ case 1236: /* pacibsp */
case 1234: /* pacibz */ case 1235: /* pacibz */
case 1233: /* paciasp */ case 1234: /* paciasp */
case 1232: /* paciaz */ case 1233: /* paciaz */
case 1211: /* tsb */ case 1211: /* tsb */
case 1210: /* psb */ case 1210: /* psb */
case 1209: /* esb */ case 1209: /* esb */
@ -453,141 +453,144 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 1194: /* hint */ case 1194: /* hint */
value = 1194; /* --> hint. */ value = 1194; /* --> hint. */
break; break;
case 1216: /* pssbb */ case 1217: /* pssbb */
case 1215: /* ssbb */ case 1216: /* ssbb */
case 1214: /* dfb */ case 1215: /* dfb */
case 1213: /* dsb */ case 1213: /* dsb */
value = 1213; /* --> dsb. */ value = 1213; /* --> dsb. */
break; break;
case 1227: /* cpp */ case 1214: /* dsb */
case 1226: /* dvp */ value = 1214; /* --> dsb. */
case 1225: /* cfp */
case 1224: /* tlbi */
case 1223: /* ic */
case 1222: /* dc */
case 1221: /* at */
case 1220: /* sys */
value = 1220; /* --> sys. */
break; break;
case 2037: /* bic */ case 1228: /* cpp */
case 1287: /* and */ case 1227: /* dvp */
value = 1287; /* --> and. */ case 1226: /* cfp */
case 1225: /* tlbi */
case 1224: /* ic */
case 1223: /* dc */
case 1222: /* at */
case 1221: /* sys */
value = 1221; /* --> sys. */
break; break;
case 1270: /* mov */ case 2038: /* bic */
case 1289: /* and */ case 1288: /* and */
value = 1289; /* --> and. */ value = 1288; /* --> and. */
break; break;
case 1274: /* movs */ case 1271: /* mov */
case 1290: /* ands */ case 1290: /* and */
value = 1290; /* --> ands. */ value = 1290; /* --> and. */
break; break;
case 2038: /* cmple */ case 1275: /* movs */
case 1325: /* cmpge */ case 1291: /* ands */
value = 1325; /* --> cmpge. */ value = 1291; /* --> ands. */
break; break;
case 2041: /* cmplt */ case 2039: /* cmple */
case 1328: /* cmpgt */ case 1326: /* cmpge */
value = 1328; /* --> cmpgt. */ value = 1326; /* --> cmpge. */
break; break;
case 2039: /* cmplo */ case 2042: /* cmplt */
case 1330: /* cmphi */ case 1329: /* cmpgt */
value = 1330; /* --> cmphi. */ value = 1329; /* --> cmpgt. */
break; break;
case 2040: /* cmpls */ case 2040: /* cmplo */
case 1333: /* cmphs */ case 1331: /* cmphi */
value = 1333; /* --> cmphs. */ value = 1331; /* --> cmphi. */
break; break;
case 1267: /* mov */ case 2041: /* cmpls */
case 1355: /* cpy */ case 1334: /* cmphs */
value = 1355; /* --> cpy. */ value = 1334; /* --> cmphs. */
break; break;
case 1269: /* mov */ case 1268: /* mov */
case 1356: /* cpy */ case 1356: /* cpy */
value = 1356; /* --> cpy. */ value = 1356; /* --> cpy. */
break; break;
case 2048: /* fmov */ case 1270: /* mov */
case 1272: /* mov */
case 1357: /* cpy */ case 1357: /* cpy */
value = 1357; /* --> cpy. */ value = 1357; /* --> cpy. */
break; break;
case 1262: /* mov */ case 2049: /* fmov */
case 1369: /* dup */ case 1273: /* mov */
value = 1369; /* --> dup. */ case 1358: /* cpy */
value = 1358; /* --> cpy. */
break; break;
case 1264: /* mov */ case 1263: /* mov */
case 1261: /* mov */
case 1370: /* dup */ case 1370: /* dup */
value = 1370; /* --> dup. */ value = 1370; /* --> dup. */
break; break;
case 2047: /* fmov */ case 1265: /* mov */
case 1266: /* mov */ case 1262: /* mov */
case 1371: /* dup */ case 1371: /* dup */
value = 1371; /* --> dup. */ value = 1371; /* --> dup. */
break; break;
case 1265: /* mov */ case 2048: /* fmov */
case 1372: /* dupm */ case 1267: /* mov */
value = 1372; /* --> dupm. */ case 1372: /* dup */
value = 1372; /* --> dup. */
break; break;
case 2042: /* eon */ case 1266: /* mov */
case 1374: /* eor */ case 1373: /* dupm */
value = 1374; /* --> eor. */ value = 1373; /* --> dupm. */
break; break;
case 1275: /* not */ case 2043: /* eon */
case 1376: /* eor */ case 1375: /* eor */
value = 1376; /* --> eor. */ value = 1375; /* --> eor. */
break; break;
case 1276: /* nots */ case 1276: /* not */
case 1377: /* eors */ case 1377: /* eor */
value = 1377; /* --> eors. */ value = 1377; /* --> eor. */
break; break;
case 2043: /* facle */ case 1277: /* nots */
case 1382: /* facge */ case 1378: /* eors */
value = 1382; /* --> facge. */ value = 1378; /* --> eors. */
break; break;
case 2044: /* faclt */ case 2044: /* facle */
case 1383: /* facgt */ case 1383: /* facge */
value = 1383; /* --> facgt. */ value = 1383; /* --> facge. */
break; break;
case 2045: /* fcmle */ case 2045: /* faclt */
case 1396: /* fcmge */ case 1384: /* facgt */
value = 1396; /* --> fcmge. */ value = 1384; /* --> facgt. */
break; break;
case 2046: /* fcmlt */ case 2046: /* fcmle */
case 1398: /* fcmgt */ case 1397: /* fcmge */
value = 1398; /* --> fcmgt. */ value = 1397; /* --> fcmge. */
break;
case 2047: /* fcmlt */
case 1399: /* fcmgt */
value = 1399; /* --> fcmgt. */
break;
case 1260: /* fmov */
case 1405: /* fcpy */
value = 1405; /* --> fcpy. */
break; break;
case 1259: /* fmov */ case 1259: /* fmov */
case 1404: /* fcpy */ case 1428: /* fdup */
value = 1404; /* --> fcpy. */ value = 1428; /* --> fdup. */
break; break;
case 1258: /* fmov */ case 1261: /* mov */
case 1427: /* fdup */
value = 1427; /* --> fdup. */
break;
case 1260: /* mov */
case 1758: /* orr */
value = 1758; /* --> orr. */
break;
case 2049: /* orn */
case 1759: /* orr */ case 1759: /* orr */
value = 1759; /* --> orr. */ value = 1759; /* --> orr. */
break; break;
case 1263: /* mov */ case 2050: /* orn */
case 1761: /* orr */ case 1760: /* orr */
value = 1761; /* --> orr. */ value = 1760; /* --> orr. */
break; break;
case 1273: /* movs */ case 1264: /* mov */
case 1762: /* orrs */ case 1762: /* orr */
value = 1762; /* --> orrs. */ value = 1762; /* --> orr. */
break; break;
case 1268: /* mov */ case 1274: /* movs */
case 1824: /* sel */ case 1763: /* orrs */
value = 1824; /* --> sel. */ value = 1763; /* --> orrs. */
break; break;
case 1271: /* mov */ case 1269: /* mov */
case 1825: /* sel */ case 1825: /* sel */
value = 1825; /* --> sel. */ value = 1825; /* --> sel. */
break; break;
case 1272: /* mov */
case 1826: /* sel */
value = 1826; /* --> sel. */
break;
default: return NULL; default: return NULL;
} }
@ -630,7 +633,6 @@ aarch64_insert_operand (const aarch64_operand *self,
case 28: case 28:
case 29: case 29:
case 30: case 30:
case 164:
case 165: case 165:
case 166: case 166:
case 167: case 167:
@ -640,7 +642,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 171: case 171:
case 172: case 172:
case 173: case 173:
case 188: case 174:
case 189: case 189:
case 190: case 190:
case 191: case 191:
@ -649,8 +651,9 @@ aarch64_insert_operand (const aarch64_operand *self,
case 194: case 194:
case 195: case 195:
case 196: case 196:
case 202: case 197:
case 205: case 203:
case 206:
return aarch64_ins_regno (self, info, code, inst, errors); return aarch64_ins_regno (self, info, code, inst, errors);
case 14: case 14:
return aarch64_ins_reg_extended (self, info, code, inst, errors); return aarch64_ins_reg_extended (self, info, code, inst, errors);
@ -662,7 +665,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 32: case 32:
case 33: case 33:
case 34: case 34:
case 208: case 209:
return aarch64_ins_reglane (self, info, code, inst, errors); return aarch64_ins_reglane (self, info, code, inst, errors);
case 35: case 35:
return aarch64_ins_reglist (self, info, code, inst, errors); return aarch64_ins_reglist (self, info, code, inst, errors);
@ -697,9 +700,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 81: case 81:
case 82: case 82:
case 83: case 83:
case 161: case 162:
case 163: case 164:
case 180:
case 181: case 181:
case 182: case 182:
case 183: case 183:
@ -707,7 +709,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 185: case 185:
case 186: case 186:
case 187: case 187:
case 207: case 188:
case 208:
return aarch64_ins_imm (self, info, code, inst, errors); return aarch64_ins_imm (self, info, code, inst, errors);
case 43: case 43:
case 44: case 44:
@ -717,10 +720,10 @@ aarch64_insert_operand (const aarch64_operand *self,
case 47: case 47:
return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors); return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors);
case 51: case 51:
case 151: case 152:
return aarch64_ins_fpimm (self, info, code, inst, errors); return aarch64_ins_fpimm (self, info, code, inst, errors);
case 69: case 69:
case 159: case 160:
return aarch64_ins_limm (self, info, code, inst, errors); return aarch64_ins_limm (self, info, code, inst, errors);
case 70: case 70:
return aarch64_ins_aimm (self, info, code, inst, errors); return aarch64_ins_aimm (self, info, code, inst, errors);
@ -730,11 +733,11 @@ aarch64_insert_operand (const aarch64_operand *self,
return aarch64_ins_fbits (self, info, code, inst, errors); return aarch64_ins_fbits (self, info, code, inst, errors);
case 74: case 74:
case 75: case 75:
case 156: case 157:
return aarch64_ins_imm_rotate2 (self, info, code, inst, errors); return aarch64_ins_imm_rotate2 (self, info, code, inst, errors);
case 76: case 76:
case 155: case 156:
case 157: case 158:
return aarch64_ins_imm_rotate1 (self, info, code, inst, errors); return aarch64_ins_imm_rotate1 (self, info, code, inst, errors);
case 77: case 77:
case 78: case 78:
@ -769,32 +772,33 @@ aarch64_insert_operand (const aarch64_operand *self,
case 102: case 102:
return aarch64_ins_sysins_op (self, info, code, inst, errors); return aarch64_ins_sysins_op (self, info, code, inst, errors);
case 103: case 103:
case 104:
return aarch64_ins_barrier (self, info, code, inst, errors);
case 105: case 105:
return aarch64_ins_prfop (self, info, code, inst, errors); return aarch64_ins_barrier (self, info, code, inst, errors);
case 104:
return aarch64_ins_barrier_dsb_nxs (self, info, code, inst, errors);
case 106: case 106:
return aarch64_ins_none (self, info, code, inst, errors); return aarch64_ins_prfop (self, info, code, inst, errors);
case 107: case 107:
return aarch64_ins_hint (self, info, code, inst, errors); return aarch64_ins_none (self, info, code, inst, errors);
case 108: case 108:
return aarch64_ins_hint (self, info, code, inst, errors);
case 109: case 109:
return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
case 110: case 110:
return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
case 111: case 111:
case 112: case 112:
case 113: case 113:
return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
case 114: case 114:
return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors); return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
case 115: case 115:
return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors); return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
case 116: case 116:
return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
case 117: case 117:
case 118: case 118:
case 119: case 119:
return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
case 120: case 120:
return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
case 121: case 121:
case 122: case 122:
case 123: case 123:
@ -808,8 +812,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 131: case 131:
case 132: case 132:
case 133: case 133:
return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
case 134: case 134:
return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
case 135: case 135:
case 136: case 136:
case 137: case 137:
@ -817,52 +821,53 @@ aarch64_insert_operand (const aarch64_operand *self,
case 139: case 139:
case 140: case 140:
case 141: case 141:
return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
case 142: case 142:
return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
case 143: case 143:
case 144: case 144:
case 145: case 145:
return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
case 146: case 146:
return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors); return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
case 147: case 147:
return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors); return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
case 148: case 148:
return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors); return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
case 149: case 149:
return aarch64_ins_sve_aimm (self, info, code, inst, errors); return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
case 150: case 150:
return aarch64_ins_sve_aimm (self, info, code, inst, errors);
case 151:
return aarch64_ins_sve_asimm (self, info, code, inst, errors); return aarch64_ins_sve_asimm (self, info, code, inst, errors);
case 152:
return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
case 153: case 153:
return aarch64_ins_sve_float_half_two (self, info, code, inst, errors); return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
case 154: case 154:
return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
case 155:
return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors); return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors);
case 158: case 159:
return aarch64_ins_inv_limm (self, info, code, inst, errors); return aarch64_ins_inv_limm (self, info, code, inst, errors);
case 160: case 161:
return aarch64_ins_sve_limm_mov (self, info, code, inst, errors); return aarch64_ins_sve_limm_mov (self, info, code, inst, errors);
case 162: case 163:
return aarch64_ins_sve_scale (self, info, code, inst, errors); return aarch64_ins_sve_scale (self, info, code, inst, errors);
case 174:
case 175: case 175:
case 176: case 176:
return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
case 177: case 177:
return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
case 178: case 178:
case 179: case 179:
case 180:
return aarch64_ins_sve_shrimm (self, info, code, inst, errors); return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
case 197:
case 198: case 198:
case 199: case 199:
case 200: case 200:
case 201: case 201:
case 202:
return aarch64_ins_sve_quad_index (self, info, code, inst, errors); return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
case 203:
return aarch64_ins_sve_index (self, info, code, inst, errors);
case 204: case 204:
case 206: return aarch64_ins_sve_index (self, info, code, inst, errors);
case 205:
case 207:
return aarch64_ins_sve_reglist (self, info, code, inst, errors); return aarch64_ins_sve_reglist (self, info, code, inst, errors);
default: assert (0); abort (); default: assert (0); abort ();
} }

15
opcodes/aarch64-asm.c
View File

@ -876,6 +876,21 @@ aarch64_ins_barrier (const aarch64_operand *self ATTRIBUTE_UNUSED,
return TRUE; return TRUE;
} }
/* Encode the memory barrier option operand for DSB <option>nXS|#<imm>. */
bfd_boolean
aarch64_ins_barrier_dsb_nxs (const aarch64_operand *self ATTRIBUTE_UNUSED,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
{
/* For the DSB nXS barrier variant: is a 5-bit unsigned immediate,
encoded in CRm<3:2>. */
aarch64_insn value = (info->barrier->value >> 2) - 4;
insert_field (FLD_CRm_dsb_nxs, code, value, 0);
return TRUE;
}
/* Encode the prefetch operation option operand for e.g. /* Encode the prefetch operation option operand for e.g.
PRFM <prfop>, [<Xn|SP>{, #<pimm>}]. */ PRFM <prfop>, [<Xn|SP>{, #<pimm>}]. */

1
opcodes/aarch64-asm.h
View File

@ -71,6 +71,7 @@ AARCH64_DECL_OPD_INSERTER (ins_sysreg);
AARCH64_DECL_OPD_INSERTER (ins_pstatefield); AARCH64_DECL_OPD_INSERTER (ins_pstatefield);
AARCH64_DECL_OPD_INSERTER (ins_sysins_op); AARCH64_DECL_OPD_INSERTER (ins_sysins_op);
AARCH64_DECL_OPD_INSERTER (ins_barrier); AARCH64_DECL_OPD_INSERTER (ins_barrier);
AARCH64_DECL_OPD_INSERTER (ins_barrier_dsb_nxs);
AARCH64_DECL_OPD_INSERTER (ins_hint); AARCH64_DECL_OPD_INSERTER (ins_hint);
AARCH64_DECL_OPD_INSERTER (ins_prfop); AARCH64_DECL_OPD_INSERTER (ins_prfop);
AARCH64_DECL_OPD_INSERTER (ins_reg_extended); AARCH64_DECL_OPD_INSERTER (ins_reg_extended);

2614
opcodes/aarch64-dis-2.c
View File

File diff suppressed because it is too large Load Diff

15
opcodes/aarch64-dis.c
View File

@ -1293,6 +1293,21 @@ aarch64_ext_barrier (const aarch64_operand *self ATTRIBUTE_UNUSED,
return TRUE; return TRUE;
} }
/* Decode the memory barrier option operand for DSB <option>nXS|#<imm>. */
bfd_boolean
aarch64_ext_barrier_dsb_nxs (const aarch64_operand *self ATTRIBUTE_UNUSED,
aarch64_opnd_info *info,
aarch64_insn code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
{
/* For the DSB nXS barrier variant immediate is encoded in 2-bit field. */
aarch64_insn field = extract_field (FLD_CRm_dsb_nxs, code, 0);
info->barrier = aarch64_barrier_dsb_nxs_options + field;
return TRUE;
}
/* Decode the prefetch operation option operand for e.g. /* Decode the prefetch operation option operand for e.g.
PRFM <prfop>, [<Xn|SP>{, #<pimm>}]. */ PRFM <prfop>, [<Xn|SP>{, #<pimm>}]. */

1
opcodes/aarch64-dis.h
View File

@ -94,6 +94,7 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_sysreg);
AARCH64_DECL_OPD_EXTRACTOR (ext_pstatefield); AARCH64_DECL_OPD_EXTRACTOR (ext_pstatefield);
AARCH64_DECL_OPD_EXTRACTOR (ext_sysins_op); AARCH64_DECL_OPD_EXTRACTOR (ext_sysins_op);
AARCH64_DECL_OPD_EXTRACTOR (ext_barrier); AARCH64_DECL_OPD_EXTRACTOR (ext_barrier);
AARCH64_DECL_OPD_EXTRACTOR (ext_barrier_dsb_nxs);
AARCH64_DECL_OPD_EXTRACTOR (ext_hint); AARCH64_DECL_OPD_EXTRACTOR (ext_hint);
AARCH64_DECL_OPD_EXTRACTOR (ext_prfop); AARCH64_DECL_OPD_EXTRACTOR (ext_prfop);
AARCH64_DECL_OPD_EXTRACTOR (ext_reg_extended); AARCH64_DECL_OPD_EXTRACTOR (ext_reg_extended);

17
opcodes/aarch64-opc-2.c
View File

@ -128,6 +128,7 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_SYSTEM, "SYSREG_TLBI", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a TBL invalidation operation specifier"}, {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_TLBI", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a TBL invalidation operation specifier"},
{AARCH64_OPND_CLASS_SYSTEM, "SYSREG_SR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a Speculation Restriction option name (RCTX)"}, {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_SR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a Speculation Restriction option name (RCTX)"},
{AARCH64_OPND_CLASS_SYSTEM, "BARRIER", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a barrier option name"}, {AARCH64_OPND_CLASS_SYSTEM, "BARRIER", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a barrier option name"},
{AARCH64_OPND_CLASS_SYSTEM, "BARRIER_DSB_NXS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the DSB nXS option qualifier name SY, ISH, NSH, OSH or an optional 5-bit unsigned immediate"},
{AARCH64_OPND_CLASS_SYSTEM, "BARRIER_ISB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the ISB option name SY or an optional 4-bit unsigned immediate"}, {AARCH64_OPND_CLASS_SYSTEM, "BARRIER_ISB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the ISB option name SY or an optional 4-bit unsigned immediate"},
{AARCH64_OPND_CLASS_SYSTEM, "PRFOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a prefetch operation specifier"}, {AARCH64_OPND_CLASS_SYSTEM, "PRFOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a prefetch operation specifier"},
{AARCH64_OPND_CLASS_SYSTEM, "BARRIER_PSB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the PSB/TSB option name CSYNC"}, {AARCH64_OPND_CLASS_SYSTEM, "BARRIER_PSB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the PSB/TSB option name CSYNC"},
@ -310,17 +311,17 @@ static const unsigned op_enum_table [] =
391, 391,
413, 413,
415, 415,
1263,
1268,
1261,
1260,
1264, 1264,
1271, 1269,
1273, 1262,
1261,
1265,
1272,
1274, 1274,
1270,
1276,
1275, 1275,
1271,
1277,
1276,
131, 131,
}; };

10
opcodes/aarch64-opc.c
View File

@ -328,6 +328,7 @@ const aarch64_field fields[] =
{ 12, 1 }, /* rotate3: FCADD immediate rotate. */ { 12, 1 }, /* rotate3: FCADD immediate rotate. */
{ 12, 2 }, /* SM3: Indexed element SM3 2 bits index immediate. */ { 12, 2 }, /* SM3: Indexed element SM3 2 bits index immediate. */
{ 22, 1 }, /* sz: 1-bit element size select. */ { 22, 1 }, /* sz: 1-bit element size select. */
{ 10, 2 }, /* CRm_dsb_nxs: 2-bit imm. encoded in CRm<3:2>. */
}; };
enum aarch64_operand_class enum aarch64_operand_class
@ -466,6 +467,14 @@ const struct aarch64_name_value_pair aarch64_barrier_options[16] =
{ "sy", 0xf }, { "sy", 0xf },
}; };
const struct aarch64_name_value_pair aarch64_barrier_dsb_nxs_options[4] =
{ /* CRm<3:2> #imm */
{ "oshnxs", 16 }, /* 00 16 */
{ "nshnxs", 20 }, /* 01 20 */
{ "ishnxs", 24 }, /* 10 24 */
{ "synxs", 28 }, /* 11 28 */
};
/* Table describing the operands supported by the aliases of the HINT /* Table describing the operands supported by the aliases of the HINT
instruction. instruction.
@ -3750,6 +3759,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
break; break;
case AARCH64_OPND_BARRIER: case AARCH64_OPND_BARRIER:
case AARCH64_OPND_BARRIER_DSB_NXS:
snprintf (buf, size, "%s", opnd->barrier->name); snprintf (buf, size, "%s", opnd->barrier->name);
break; break;

3
opcodes/aarch64-opc.h
View File

@ -154,7 +154,8 @@ enum aarch64_field_kind
FLD_rotate2, FLD_rotate2,
FLD_rotate3, FLD_rotate3,
FLD_SM3_imm2, FLD_SM3_imm2,
FLD_sz FLD_sz,
FLD_CRm_dsb_nxs
}; };
/* Field description. */ /* Field description. */

5
opcodes/aarch64-tbl.h
View File

@ -2561,6 +2561,8 @@ static const aarch64_feature_set aarch64_feature_v8_r =
{ NAME, OPCODE, MASK, CLASS, 0, F32MM_SVE, OPS, QUALS, FLAGS, CONSTRAINTS, TIED, NULL } { NAME, OPCODE, MASK, CLASS, 0, F32MM_SVE, OPS, QUALS, FLAGS, CONSTRAINTS, TIED, NULL }
#define V8_R_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ #define V8_R_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, ARMV8_R, OPS, QUALS, FLAGS, 0, 0, NULL } { NAME, OPCODE, MASK, CLASS, 0, ARMV8_R, OPS, QUALS, FLAGS, 0, 0, NULL }
#define V8_7_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, ARMV8_7, OPS, QUALS, FLAGS, 0, 0, NULL }
struct aarch64_opcode aarch64_opcode_table[] = struct aarch64_opcode aarch64_opcode_table[] =
{ {
@ -3853,6 +3855,7 @@ struct aarch64_opcode aarch64_opcode_table[] =
CORE_INSN ("tsb", 0xd503225f, 0xffffffff, ic_system, 0, OP1 (BARRIER_PSB), {}, F_ALIAS), CORE_INSN ("tsb", 0xd503225f, 0xffffffff, ic_system, 0, OP1 (BARRIER_PSB), {}, F_ALIAS),
CORE_INSN ("clrex", 0xd503305f, 0xfffff0ff, ic_system, 0, OP1 (UIMM4), {}, F_OPD0_OPT | F_DEFAULT (0xF)), CORE_INSN ("clrex", 0xd503305f, 0xfffff0ff, ic_system, 0, OP1 (UIMM4), {}, F_OPD0_OPT | F_DEFAULT (0xF)),
CORE_INSN ("dsb", 0xd503309f, 0xfffff0ff, ic_system, 0, OP1 (BARRIER), {}, F_HAS_ALIAS), CORE_INSN ("dsb", 0xd503309f, 0xfffff0ff, ic_system, 0, OP1 (BARRIER), {}, F_HAS_ALIAS),
V8_7_INSN ("dsb", 0xd503323f, 0xfffff3ff, ic_system, OP1 (BARRIER_DSB_NXS), {}, F_HAS_ALIAS),
V8_R_INSN ("dfb", 0xd5033c9f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS), V8_R_INSN ("dfb", 0xd5033c9f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
CORE_INSN ("ssbb", 0xd503309f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), CORE_INSN ("ssbb", 0xd503309f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
CORE_INSN ("pssbb", 0xd503349f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), CORE_INSN ("pssbb", 0xd503349f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
@ -5323,6 +5326,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
"a Speculation Restriction option name (RCTX)") \ "a Speculation Restriction option name (RCTX)") \
Y(SYSTEM, barrier, "BARRIER", 0, F(), \ Y(SYSTEM, barrier, "BARRIER", 0, F(), \
"a barrier option name") \ "a barrier option name") \
Y(SYSTEM, barrier_dsb_nxs, "BARRIER_DSB_NXS", 0, F(), \
"the DSB nXS option qualifier name SY, ISH, NSH, OSH or an optional 5-bit unsigned immediate") \
Y(SYSTEM, barrier, "BARRIER_ISB", 0, F(), \ Y(SYSTEM, barrier, "BARRIER_ISB", 0, F(), \
"the ISB option name SY or an optional 4-bit unsigned immediate") \ "the ISB option name SY or an optional 4-bit unsigned immediate") \
Y(SYSTEM, prfop, "PRFOP", 0, F(), \ Y(SYSTEM, prfop, "PRFOP", 0, F(), \