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gas/testsuite/

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2006-12-15  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/x86-64-inval.s: cmpxchg16b needs oword ptr, instead
	of xmmword ptr.
	* gas/i386/x86_64.s: Likewise.
	* gas/i386/x86-64-inval.l: Updated.

opcodes/

2006-12-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (o_mode): New for 16-byte operand.
	(intel_operand_size): Generate "OWORD PTR " for o_mode.
	(CMPXCHG8B_Fixup): Set bytemode to o_mode instead of x_mode.
This commit is contained in:
H.J. Lu
2006-12-15 13:11:56 +00:00
parent a6c73b34d0
commit fb9c77c70e
6 changed files with 21 additions and 4 deletions
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7
gas/testsuite/ChangeLog
View File

@ -1,3 +1,10 @@
2006-12-15 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/x86-64-inval.s: cmpxchg16b needs oword ptr, instead
of xmmword ptr.
* gas/i386/x86_64.s: Likewise.
* gas/i386/x86-64-inval.l: Updated.
2006-12-14 H.J. Lu <hongjiu.lu@intel.com> 2006-12-14 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/x86-64-inval.s: Add cmpxchg16b. * gas/i386/x86-64-inval.s: Add cmpxchg16b.

2
gas/testsuite/gas/i386/x86-64-inval.l
View File

@ -106,4 +106,4 @@ GAS LISTING .*
51 [ ]*retl # can't have 32-bit stack operands 51 [ ]*retl # can't have 32-bit stack operands
52 [ ]*insertq \$4,\$2,%xmm2,%ebx # The last operand must be XMM register. 52 [ ]*insertq \$4,\$2,%xmm2,%ebx # The last operand must be XMM register.
53 [ ]*.intel_syntax noprefix 53 [ ]*.intel_syntax noprefix
54 [ ]*cmpxchg16b dword ptr \[rax\] # Must be xmmword 54 [ ]*cmpxchg16b dword ptr \[rax\] # Must be oword

2
gas/testsuite/gas/i386/x86-64-inval.s
View File

@ -51,4 +51,4 @@ foo: jcxz foo # No prefix exists to select CX as a counter
retl # can't have 32-bit stack operands retl # can't have 32-bit stack operands
insertq $4,$2,%xmm2,%ebx # The last operand must be XMM register. insertq $4,$2,%xmm2,%ebx # The last operand must be XMM register.
.intel_syntax noprefix .intel_syntax noprefix
cmpxchg16b dword ptr [rax] # Must be xmmword cmpxchg16b dword ptr [rax] # Must be oword

2
gas/testsuite/gas/i386/x86_64.s
View File

@ -191,7 +191,7 @@ movq %rax,0xffffffffff332211
cmpxchg16b (%rax) cmpxchg16b (%rax)
.intel_syntax noprefix .intel_syntax noprefix
cmpxchg16b xmmword ptr [rax] cmpxchg16b oword ptr [rax]
# Get a good alignment. # Get a good alignment.
.p2align 4,0 .p2align 4,0

6
opcodes/ChangeLog
View File

@ -1,3 +1,9 @@
2006-12-15 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (o_mode): New for 16-byte operand.
(intel_operand_size): Generate "OWORD PTR " for o_mode.
(CMPXCHG8B_Fixup): Set bytemode to o_mode instead of x_mode.
2006-12-14 H.J. Lu <hongjiu.lu@intel.com> 2006-12-14 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (CMPXCHG8B_Fixup): New. * i386-dis.c (CMPXCHG8B_Fixup): New.

6
opcodes/i386-dis.c
View File

@ -356,6 +356,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
#define const_1_mode 14 #define const_1_mode 14
#define stack_v_mode 15 /* v_mode for stack-related opcodes. */ #define stack_v_mode 15 /* v_mode for stack-related opcodes. */
#define z_mode 16 /* non-quad operand size depends on prefixes */ #define z_mode 16 /* non-quad operand size depends on prefixes */
#define o_mode 17 /* 16-byte operand */
#define es_reg 100 #define es_reg 100
#define cs_reg 101 #define cs_reg 101
@ -4183,6 +4184,9 @@ intel_operand_size (int bytemode, int sizeflag)
case x_mode: case x_mode:
oappend ("XMMWORD PTR "); oappend ("XMMWORD PTR ");
break; break;
case o_mode:
oappend ("OWORD PTR ");
break;
default: default:
break; break;
} }
@ -5778,7 +5782,7 @@ CMPXCHG8B_Fixup (int bytemode, int sizeflag)
/* Change cmpxchg8b to cmpxchg16b. */ /* Change cmpxchg8b to cmpxchg16b. */
char *p = obuf + strlen (obuf) - 2; char *p = obuf + strlen (obuf) - 2;
strcpy (p, "16b"); strcpy (p, "16b");
bytemode = x_mode; bytemode = o_mode;
} }
OP_M (bytemode, sizeflag); OP_M (bytemode, sizeflag);
} }