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RISC-V: Fix disassemble for c.li, c.andi and c.addiw

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ChangeLog

2017-05-03  Kito Cheng  <kito.cheng@gmail.com>

        * riscv-dis.c (print_insn_args): Handle 'Co' operands.
This commit is contained in:
Kito Cheng
2017-04-05 20:58:28 +08:00
committed by Palmer Dabbelt
parent 45eba0ab7d
commit f91d48deb2
2 changed files with 5 additions and 0 deletions
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4
opcodes/ChangeLog
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@ -1,3 +1,7 @@
2017-05-03 Kito Cheng <kito.cheng@gmail.com>
* riscv-dis.c (print_insn_args): Handle 'Co' operands.
2017-05-01 Michael Clark <michaeljclark@mac.com> 2017-05-01 Michael Clark <michaeljclark@mac.com>
* riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary

1
opcodes/riscv-dis.c
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@ -153,6 +153,7 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
case 'i': case 'i':
print (info->stream, "%d", (int)EXTRACT_RVC_SIMM3 (l)); print (info->stream, "%d", (int)EXTRACT_RVC_SIMM3 (l));
break; break;
case 'o':
case 'j': case 'j':
print (info->stream, "%d", (int)EXTRACT_RVC_IMM (l)); print (info->stream, "%d", (int)EXTRACT_RVC_IMM (l));
break; break;