diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index dfb2d686a5d..d6267562314 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -1,7 +1,7 @@ stages: - build - - test - deploy + - test - release_stage1 - release_submit @@ -34,8 +34,11 @@ variables: # Customization of jobs DIST_ART_DIR: "dist" + DIST_ART_DIR_S2: "dist_s2" DIST_NAME: "esp32ulp-elf-binutils" + DIST_NAME_S2: "esp32s2ulp-elf-binutils" DIST_INSTALLED_DIR: "${DIST_NAME}" + DIST_INSTALLED_DIR_S2: "${DIST_NAME_S2}" ARCHIVE_TOOL: "tar czvf" # UNARCHIVE_TOOL: "tar xvf" ARCHIVE_EXT: "tar.gz" @@ -72,6 +75,12 @@ variables: mv ${ARCHIVE_NAME} ${DIST_ART_DIR} echo "${ARCHIVE_NAME}" > ${DIST_ART_DIR}/dist_name_${PLATFORM_NAME} +.dist_archive_s2: &dist_archive_s2 | + ${ARCHIVE_TOOL} ${ARCHIVE_NAME} ${DIST_INSTALLED_DIR_S2} + mkdir -p ${DIST_ART_DIR_S2} + mv ${ARCHIVE_NAME} ${DIST_ART_DIR_S2} + echo "${ARCHIVE_NAME}" > ${DIST_ART_DIR_S2}/dist_name_s2_${PLATFORM_NAME} + .add_gh_key_remote: &add_gh_key_remote | command -v ssh-agent >/dev/null || exit 1 eval $(ssh-agent -s) @@ -105,7 +114,8 @@ before_script: - set -o errexit; set -o pipefail; set -o nounset - test ${DEBUG_SHELL:-""} && set -x -build_linux: +# ===== Main Stages for esp32-ulp ========================== +build_linux_esp32-ulp: stage: build image: $CI_DOCKER_REGISTRY/esp32-toolchain tags: @@ -125,7 +135,7 @@ build_linux: - MAKEFLAGS= make install-strip - *dist_archive -test_linux: +test_linux_esp32-ulp: stage: test image: $CI_DOCKER_REGISTRY/esp32-toolchain tags: @@ -137,7 +147,7 @@ test_linux: variables: PLATFORM_NAME: "linux64" dependencies: - - build_linux + - build_linux_esp32-ulp script: - *get_release_name - *set_displayed_version @@ -149,8 +159,7 @@ test_linux: - git diff --exit-code -- . || (echo 'Differences found. Please check changes and commit new check files.'; exit 1) - echo "Compare test done" - -build_windows: +build_windows_esp32-ulp: stage: build image: $CI_DOCKER_REGISTRY/esp32-toolchain-win-cross tags: @@ -178,7 +187,7 @@ build_windows: - MAKEFLAGS= make install-strip - *dist_archive -build_macos: +build_macos_esp32-ulp: stage: build image: $CI_DOCKER_REGISTRY/osxcross tags: @@ -197,6 +206,102 @@ build_macos: - make - MAKEFLAGS= make install-strip - *dist_archive +# ============================================================== + +# ===== Main Stages for esp32s2-ulp ========================== +build_linux_esp32s2-ulp: + stage: build + image: $CI_DOCKER_REGISTRY/esp32-toolchain + tags: + - build + artifacts: + paths: + - ${DIST_ART_DIR_S2} + expire_in: 2 weeks + variables: + PLATFORM_NAME: "linux64" + script: + - *get_release_name + - *set_displayed_version + - MAKEFLAGS= ./configure --target=esp32s2ulp-elf --prefix=$PWD/$DIST_INSTALLED_DIR_S2 ${BINUTILS_CONFIGURE_OPTS} + - echo "MAKEINFO = :" >> Makefile + - make + - MAKEFLAGS= make install-strip + - *dist_archive_s2 + +test_linux_esp32s2-ulp: + stage: test + image: $CI_DOCKER_REGISTRY/esp32-toolchain + tags: + - build + artifacts: + paths: + - ${DIST_ART_DIR_S2} + expire_in: 2 weeks + variables: + PLATFORM_NAME: "linux64" + dependencies: + - build_linux_esp32s2-ulp + script: + - *get_release_name + - *set_displayed_version + - MAKEFLAGS= ./configure --target=esp32s2ulp-elf --prefix=$PWD/$DIST_INSTALLED_DIR_S2 ${BINUTILS_CONFIGURE_OPTS} + - echo "MAKEINFO = :" >> Makefile + - make + - ./gas/testsuite/gas/esp32s2ulp/check_all.sh + - cd gas/testsuite/gas/esp32s2ulp/compare + - git diff --exit-code -- . || (echo 'Differences found. Please check changes and commit new check files.'; exit 1) + - echo "Compare test done" + +build_windows_esp32s2-ulp: + stage: build + image: $CI_DOCKER_REGISTRY/esp32-toolchain-win-cross + tags: + - build + artifacts: + paths: + - ${DIST_ART_DIR_S2} + expire_in: 2 weeks + variables: + PLATFORM_NAME: "win32" + ARCHIVE_TOOL: "zip -r" + ARCHIVE_EXT: "zip" + script: + - *get_release_name + - *set_displayed_version + - export CC= + - export CPP= + - export CXX= + - export LD= + - export AS= + - export AR= + - MAKEFLAGS= ./configure --host=i686-w64-mingw32 --target=esp32s2ulp-elf --prefix=$PWD/$DIST_INSTALLED_DIR_S2 ${BINUTILS_CONFIGURE_OPTS} CC=i686-w64-mingw32-gcc + - echo "MAKEINFO = :" >> Makefile + - make + - MAKEFLAGS= make install-strip + - *dist_archive_s2 + +build_macos_esp32s2-ulp: + stage: build + image: $CI_DOCKER_REGISTRY/osxcross + tags: + - build + artifacts: + paths: + - ${DIST_ART_DIR_S2} + expire_in: 2 weeks + variables: + PLATFORM_NAME: "macos" + script: + - *get_release_name + - *set_displayed_version + - MAKEFLAGS= ./configure --host=x86_64-apple-darwin12 --target=esp32s2ulp-elf --prefix=$PWD/esp32s2ulp-elf-binutils ${BINUTILS_CONFIGURE_OPTS} CC=x86_64-apple-darwin12-cc + - echo "MAKEINFO = :" >> Makefile + - make + - MAKEFLAGS= make install-strip + - *dist_archive_s2 + +# ============================================================== push_master_to_github: stage: deploy diff --git a/bfd/Makefile.am b/bfd/Makefile.am index 384555afd14..a5cb34f6589 100644 --- a/bfd/Makefile.am +++ b/bfd/Makefile.am @@ -98,6 +98,7 @@ ALL_MACHINES = \ cpu-bfin.lo \ cpu-bpf.lo \ cpu-esp32ulp.lo \ + cpu-esp32s2ulp.lo \ cpu-cr16.lo \ cpu-cris.lo \ cpu-crx.lo \ @@ -183,6 +184,7 @@ ALL_MACHINES_CFILES = \ cpu-bfin.c \ cpu-bpf.c \ cpu-esp32ulp.c \ + cpu-esp32s2ulp.c \ cpu-cr16.c \ cpu-cris.c \ cpu-crx.c \ @@ -298,6 +300,7 @@ BFD32_BACKENDS = \ elf32-avr.lo \ elf32-bfin.lo \ elf32-esp32ulp.lo \ + elf32-esp32s2ulp.lo \ elf32-cr16.lo \ elf32-cris.lo \ elf32-crx.lo \ @@ -434,6 +437,7 @@ BFD32_BACKENDS_CFILES = \ elf32-avr.c \ elf32-bfin.c \ elf32-esp32ulp.c \ + elf32-esp32s2ulp.c \ elf32-cr16.c \ elf32-cris.c \ elf32-crx.c \ diff --git a/bfd/Makefile.in b/bfd/Makefile.in index cea31396c64..60c921eb225 100644 --- a/bfd/Makefile.in +++ b/bfd/Makefile.in @@ -522,6 +522,7 @@ ALL_MACHINES = \ cpu-bfin.lo \ cpu-bpf.lo \ cpu-esp32ulp.lo \ + cpu-esp32s2ulp.lo \ cpu-cr16.lo \ cpu-cris.lo \ cpu-crx.lo \ @@ -607,6 +608,7 @@ ALL_MACHINES_CFILES = \ cpu-bfin.c \ cpu-bpf.c \ cpu-esp32ulp.c \ + cpu-esp32s2ulp.c \ cpu-cr16.c \ cpu-cris.c \ cpu-crx.c \ @@ -723,6 +725,7 @@ BFD32_BACKENDS = \ elf32-avr.lo \ elf32-bfin.lo \ elf32-esp32ulp.lo \ + elf32-esp32s2ulp.lo \ elf32-cr16.lo \ elf32-cris.lo \ elf32-crx.lo \ @@ -859,6 +862,7 @@ BFD32_BACKENDS_CFILES = \ elf32-avr.c \ elf32-bfin.c \ elf32-esp32ulp.c \ + elf32-esp32s2ulp.c \ elf32-cr16.c \ elf32-cris.c \ elf32-crx.c \ @@ -1336,6 +1340,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-bfin.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-bpf.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-esp32ulp.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-esp32s2ulp.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-cr16.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-cris.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-crx.Plo@am__quote@ @@ -1432,6 +1437,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-avr.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-bfin.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-esp32ulp.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-esp32s2ulp.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-cr16.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-cris.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-crx.Plo@am__quote@ diff --git a/bfd/archures.c b/bfd/archures.c index 402a4265313..1d82d68d10f 100644 --- a/bfd/archures.c +++ b/bfd/archures.c @@ -616,6 +616,7 @@ extern const bfd_arch_info_type bfd_arm_arch; extern const bfd_arch_info_type bfd_avr_arch; extern const bfd_arch_info_type bfd_bfin_arch; extern const bfd_arch_info_type bfd_esp32ulp_arch; +extern const bfd_arch_info_type bfd_esp32s2ulp_arch; extern const bfd_arch_info_type bfd_cr16_arch; extern const bfd_arch_info_type bfd_cris_arch; extern const bfd_arch_info_type bfd_crx_arch; diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index 27f22c04c2e..0138058a0be 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -1843,6 +1843,8 @@ enum bfd_architecture #define bfd_mach_bfin 1 bfd_arch_esp32ulp, /* Espressif Incorporated - esp32ulp*/ #define bfd_mach_esp32ulp 1 + bfd_arch_esp32s2ulp,/* Espressif Incorporated - esp32s2ulp*/ +#define bfd_mach_esp32s2ulp 1 bfd_arch_cr16, /* National Semiconductor CompactRISC (ie CR16). */ #define bfd_mach_cr16 1 bfd_arch_crx, /* National Semiconductor CRX. */ @@ -3634,6 +3636,108 @@ pc-relative or some form of GOT-indirect relocation. */ /* arithmetic relocation. */ BFD_ARELOC_ESP32ULP_ADDR, /* --------------- End of esp dummy ----------------------------------*/ + /* ================ ESP32-S2ULP Processor ==========================*/ + BFD_RELOC_ESP32S2ULP_16_IMM, + BFD_RELOC_ESP32S2ULP_JUMPR, + BFD_RELOC_ESP32S2ULP_16_LOAD, + BFD_RELOC_ESP32S2ULP_WR_MEM, + BFD_RELOC_ESP32S2ULP_ALUI, + BFD_RELOC_ESP32S2ULP_WAIT, + BFD_RELOC_ESP32S2ULP_TSENS_CYCLE, + BFD_RELOC_ESP32S2ULP_TSENS_DELAY, + + BFD_RELOC_ESP32S2ULP_ADC_CYCLE, + BFD_RELOC_ESP32S2ULP_ADC_SEL, + BFD_RELOC_ESP32S2ULP_ADC_MUX, + BFD_RELOC_ESP32S2ULP_WAKE, + BFD_RELOC_ESP32S2ULP_SLEEP, + BFD_RELOC_ESP32S2ULP_STAGE, + + BFD_RELOC_ESP32S2ULP_JUMPR_STEP, + BFD_RELOC_ESP32S2ULP_JUMPR_THRESH, + BFD_RELOC_ESP32S2ULP_JUMPS_THRESH, + + BFD_RELOC_ESP32S2ULP_REG_RW_HIGH, + BFD_RELOC_ESP32S2ULP_REG_RW_LOW, + BFD_RELOC_ESP32S2ULP_REG_RW_ADDR, + BFD_RELOC_ESP32S2ULP_REG_RW_DATA, + + BFD_RELOC_ESP32S2ULP_I2C_RW_HIGH, + BFD_RELOC_ESP32S2ULP_I2C_RW_LOW, + BFD_RELOC_ESP32S2ULP_I2C_RW_ADDR, + BFD_RELOC_ESP32S2ULP_I2C_RW_DATA, + BFD_RELOC_ESP32S2ULP_I2C_RW_SEL, + + BFD_RELOC_ESP32S2ULP_WR_MEM_LABEL, + + BFD_RELOC_ESP32S2ULP_RESERVE, + /* GOT relocation. */ + BFD_RELOC_ESP32S2ULP_GOT, + + /* PLTPC relocation. */ + BFD_RELOC_ESP32S2ULP_PLTPC, + + /* arithmetic relocation. */ + BFD_ARELOC_ESP32S2ULP_PUSH, + + /* arithmetic relocation. */ + BFD_ARELOC_ESP32S2ULP_CONST, + + /* arithmetic relocation. */ + BFD_ARELOC_ESP32S2ULP_ADD, + + /* arithmetic relocation. */ + BFD_ARELOC_ESP32S2ULP_SUB, + + /* arithmetic relocation. */ + BFD_ARELOC_ESP32S2ULP_MULT, + + /* arithmetic relocation. */ + BFD_ARELOC_ESP32S2ULP_DIV, + + /* arithmetic relocation. */ + BFD_ARELOC_ESP32S2ULP_MOD, + + /* arithmetic relocation. */ + BFD_ARELOC_ESP32S2ULP_LSHIFT, + + /* arithmetic relocation. */ + BFD_ARELOC_ESP32S2ULP_RSHIFT, + + /* arithmetic relocation. */ + BFD_ARELOC_ESP32S2ULP_AND, + + /* arithmetic relocation. */ + BFD_ARELOC_ESP32S2ULP_OR, + + /* arithmetic relocation. */ + BFD_ARELOC_ESP32S2ULP_XOR, + + /* arithmetic relocation. */ + BFD_ARELOC_ESP32S2ULP_LAND, + + /* arithmetic relocation. */ + BFD_ARELOC_ESP32S2ULP_LOR, + + /* arithmetic relocation. */ + BFD_ARELOC_ESP32S2ULP_LEN, + + /* arithmetic relocation. */ + BFD_ARELOC_ESP32S2ULP_NEG, + + /* arithmetic relocation. */ + BFD_ARELOC_ESP32S2ULP_COMP, + + /* arithmetic relocation. */ + BFD_ARELOC_ESP32S2ULP_PAGE, + + /* arithmetic relocation. */ + BFD_ARELOC_ESP32S2ULP_HWPAGE, + + /* arithmetic relocation. */ + BFD_ARELOC_ESP32S2ULP_ADDR, + /* --------------- End of esp32s2 dummy ----------------------------------*/ + /* Mitsubishi D10V relocs. This is a 10-bit reloc with the right 2 bits diff --git a/bfd/config.bfd b/bfd/config.bfd index c90cf127807..74a9e500a60 100644 --- a/bfd/config.bfd +++ b/bfd/config.bfd @@ -169,6 +169,7 @@ arc*) targ_archs=bfd_arc_arch ;; arm*) targ_archs=bfd_arm_arch ;; bfin*) targ_archs=bfd_bfin_arch ;; esp32ulp*) targ_archs=bfd_esp32ulp_arch ;; +esp32s2ulp*) targ_archs=bfd_esp32s2ulp_arch ;; c30*) targ_archs=bfd_tic30_arch ;; c4x*) targ_archs=bfd_tic4x_arch ;; c54x*) targ_archs=bfd_tic54x_arch ;; @@ -412,18 +413,18 @@ case "${targ}" in targ_underscore=yes ;; -<<<<<<< HEAD -======= esp32ulp-*-*) targ_defvec=esp32ulp_elf32_vec targ_selvecs=esp32ulp_elf32_fdpic_vec targ_underscore=yes ;; - c30-*-*aout* | tic30-*-*aout*) - targ_defvec=tic30_aout_vec + esp32s2ulp-*-*) + targ_defvec=esp32s2ulp_elf32_vec + targ_selvecs=esp32s2ulp_elf32_fdpic_vec + targ_underscore=yes ;; ->>>>>>> e9c4dfb4c1 (Added changes for existing files of binutils.) + c30-*-*coff* | tic30-*-*coff*) targ_defvec=tic30_coff_vec ;; diff --git a/bfd/configure b/bfd/configure old mode 100755 new mode 100644 index c30a92477e9..4eb9397b0ce --- a/bfd/configure +++ b/bfd/configure @@ -14747,6 +14747,8 @@ do bfin_elf32_fdpic_vec) tb="$tb elf32-bfin.lo elf32.lo $elf" ;; esp32ulp_elf32_vec) tb="$tb elf32-esp32ulp.lo elf32.lo $elf" ;; esp32ulp_elf32_fdpic_vec) tb="$tb elf32-esp32ulp.lo elf32.lo $elf" ;; + esp32s2ulp_elf32_vec) tb="$tb elf32-esp32s2ulp.lo elf32.lo $elf" ;; + esp32s2ulp_elf32_fdpic_vec) tb="$tb elf32-esp32s2ulp.lo elf32.lo $elf" ;; cr16_elf32_vec) tb="$tb elf32-cr16.lo elf32.lo $elf" ;; cris_aout_vec) tb="$tb aout-cris.lo" ;; cris_elf32_vec) tb="$tb elf32-cris.lo elf32.lo $elf" ;; diff --git a/bfd/configure.ac b/bfd/configure.ac index be2a2c6ffd7..46a593ee694 100644 --- a/bfd/configure.ac +++ b/bfd/configure.ac @@ -483,6 +483,8 @@ do bfin_elf32_fdpic_vec) tb="$tb elf32-bfin.lo elf32.lo $elf" ;; esp32ulp_elf32_vec) tb="$tb elf32-esp32ulp.lo elf32.lo $elf" ;; esp32ulp_elf32_fdpic_vec) tb="$tb elf32-esp32ulp.lo elf32.lo $elf" ;; + esp32s2ulp_elf32_vec) tb="$tb elf32-esp32s2ulp.lo elf32.lo $elf" ;; + esp32s2ulp_elf32_fdpic_vec) tb="$tb elf32-esp32s2ulp.lo elf32.lo $elf" ;; cr16_elf32_vec) tb="$tb elf32-cr16.lo elf32.lo $elf" ;; cris_aout_vec) tb="$tb aout-cris.lo" ;; cris_elf32_vec) tb="$tb elf32-cris.lo elf32.lo $elf" ;; diff --git a/bfd/cpu-esp32s2ulp.c b/bfd/cpu-esp32s2ulp.c new file mode 100644 index 00000000000..dec37b57682 --- /dev/null +++ b/bfd/cpu-esp32s2ulp.c @@ -0,0 +1,39 @@ +/* BFD Support for the ESP32-S2ULP processor. +Copyright (c) 2016-2017 Espressif Systems (Shanghai) PTE LTD. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, +Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#include "sysdep.h" +#include "bfd.h" +#include "libbfd.h" + +const bfd_arch_info_type bfd_esp32s2ulp_arch = +{ + 16, /* Bits in a word. */ + 32, /* Bits in an address. */ + 8, /* Bits in a byte. */ + bfd_arch_esp32s2ulp, + 0, /* Only one machine. */ + "esp32s2ulp", /* Arch name. */ + "esp32s2ulp", /* Arch printable name. */ + 4, /* Section align power. */ + TRUE, /* The one and only. */ + bfd_default_compatible, + bfd_default_scan, + bfd_arch_default_fill, + 0, +}; diff --git a/bfd/elf-bfd.h b/bfd/elf-bfd.h index 54834575135..f6cecc14165 100644 --- a/bfd/elf-bfd.h +++ b/bfd/elf-bfd.h @@ -493,6 +493,7 @@ enum elf_target_id AVR_ELF_DATA, BFIN_ELF_DATA, ESP32ULP_ELF_DATA, + ESP32S2ULP_ELF_DATA, CRIS_ELF_DATA, CSKY_ELF_DATA, FRV_ELF_DATA, diff --git a/bfd/elf32-esp32s2ulp.c b/bfd/elf32-esp32s2ulp.c new file mode 100644 index 00000000000..26eda5934a5 --- /dev/null +++ b/bfd/elf32-esp32s2ulp.c @@ -0,0 +1,4356 @@ +/* ESP32-S2ULP ELF-32 support for BFD. +Copyright (c) 2016-2017 Espressif Systems (Shanghai) PTE LTD. + +based on Copyright (C) 2005-2017 Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, +Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#include "sysdep.h" +#include "bfd.h" +#include "libbfd.h" +#include "elf-bfd.h" +#include "elf/esp32s2ulp.h" +#include "dwarf2.h" +#include "hashtab.h" + +static bfd_reloc_status_type esp32s2ulp_pltpc_reloc( + bfd *abfd ATTRIBUTE_UNUSED, arelent *reloc_entry ATTRIBUTE_UNUSED, asymbol *symbol ATTRIBUTE_UNUSED, + void * data ATTRIBUTE_UNUSED, asection *input_section ATTRIBUTE_UNUSED, bfd *output_bfd ATTRIBUTE_UNUSED, char **error_message ATTRIBUTE_UNUSED + ) +{ + bfd_reloc_status_type flag = bfd_reloc_ok; + return flag; +} + + +static bfd_reloc_status_type esp32s2ulp_jumprelr_reloc(bfd *abfd, arelent *reloc_entry, asymbol *symbol, void * data, asection *input_section, bfd *output_bfd, char **error_message ATTRIBUTE_UNUSED) +{ + bfd_vma relocation; + bfd_size_type addr = reloc_entry->address; + bfd_vma output_base = 0; + asection *output_section; + bfd_boolean relocatable = (output_bfd != NULL); + + //DEBUG_TRACE("dya_pass esp32s2ulp_jumprelr_reloc: relocatable=%i\n", (int)relocatable); + + /* Is the address of the relocation really within the section? */ + if (reloc_entry->address > bfd_get_section_limit(abfd, input_section)) + return bfd_reloc_outofrange; + + if (bfd_is_und_section(symbol->section) + && (symbol->flags & BSF_WEAK) == 0 + && !relocatable) + return bfd_reloc_undefined; + + output_section = symbol->section->output_section; + relocation = symbol->value; + /* Convert input-section-relative symbol value to absolute. */ + if (relocatable) + output_base = 0; + else + output_base = output_section->vma; + + if ((symbol->name + && symbol->section->name + && !strcmp(symbol->name, symbol->section->name)) + || !relocatable) + { + relocation += output_base + symbol->section->output_offset; + } + + relocation += reloc_entry->addend; + + if (relocatable) + { + /* This output will be relocatable ... like ld -r. */ + reloc_entry->address += input_section->output_offset; + reloc_entry->addend += symbol->section->output_offset; + //DEBUG_TRACE("dya_pass esp32s2ulp_jumprelr_reloc: address=%08x, addend=%08x, symbol->value=%08x\n", (int)reloc_entry->address, (int)reloc_entry->addend, (int)symbol->value); + } + else + { + reloc_entry->addend = 0; + } + + /* Here the variable relocation holds the final address of the + symbol we are relocating against, plus any addend. */ + unsigned int ddd = 0; + memcpy(&ddd, (unsigned char *)data + addr, 4); + relocation -= reloc_entry->address; + //DEBUG_TRACE("dya_pass esp32s2ulp_jumprelr_reloc: relocation=%08x, ddd=%08x\n", (unsigned int)relocation, ddd); + ddd &= ~(0x000000ff < 18); + int reloc = (int)relocation; + reloc = reloc >> 2; + //printf("relock=%i \n",reloc); + if ((reloc > 0x7f) || (reloc < -0x7f)) + { + return bfd_reloc_outofrange; + } + if (reloc >= 0) + { + ddd |= ((reloc & 0x7f) << 18); + } + else + { + reloc = -reloc; + ddd |= ((reloc & 0x7f) << 18) | (0x01 << 25); + } + memcpy((unsigned char *)data + addr, &ddd, 4); + //DEBUG_TRACE("dya_pass esp32s2ulp_jumprelr_reloc: final = reloc=%08x, ddd=%08x\n", (unsigned int)reloc, ddd); + return bfd_reloc_ok; +} + +static bfd_reloc_status_type esp32s2ulp_bfd_reloc(bfd *abfd, arelent *reloc_entry, asymbol *symbol, void * data, asection *input_section, bfd *output_bfd, char **error_message ATTRIBUTE_UNUSED) +{ + bfd_vma relocation; + bfd_size_type addr = reloc_entry->address; + bfd_vma output_base = 0; + reloc_howto_type *howto = reloc_entry->howto; + asection *output_section; + bfd_boolean relocatable = (output_bfd != NULL); + + /* Is the address of the relocation really within the section? */ + if (reloc_entry->address > bfd_get_section_limit(abfd, input_section)) + return bfd_reloc_outofrange; + + if (bfd_is_und_section(symbol->section) + && (symbol->flags & BSF_WEAK) == 0 + && !relocatable) + return bfd_reloc_undefined; + + /* Get symbol value. (Common symbols are special.) */ + if (bfd_is_com_section(symbol->section)) + relocation = 0; + else + relocation = symbol->value; + + output_section = symbol->section->output_section; + + /* Convert input-section-relative symbol value to absolute. */ + if (relocatable) + output_base = 0; + else + output_base = output_section->vma; + + if (!relocatable || !strcmp(symbol->name, symbol->section->name)) + relocation += output_base + symbol->section->output_offset; + + if (!relocatable && !strcmp(symbol->name, symbol->section->name)) + { + /* Add in supplied addend. */ + relocation += reloc_entry->addend; + } + + /* Here the variable relocation holds the final address of the + symbol we are relocating against, plus any addend. */ + + if (howto->pc_relative == TRUE) + { + relocation -= input_section->output_section->vma + input_section->output_offset; + + if (howto->pcrel_offset == TRUE) + relocation -= reloc_entry->address; + } + + if (relocatable) + { + reloc_entry->address += input_section->output_offset; + reloc_entry->addend += symbol->section->output_offset; + } + + if (howto->complain_on_overflow != complain_overflow_dont) + { + bfd_reloc_status_type status; + + status = bfd_check_overflow(howto->complain_on_overflow, + howto->bitsize, + howto->rightshift, + bfd_arch_bits_per_address(abfd), + relocation); + if (status != bfd_reloc_ok) + return status; + } + + /* If rightshift is 1 and the number odd, return error. */ + if (howto->rightshift && (relocation & 0x01)) + { + _bfd_error_handler(_("relocation should be even number")); + return bfd_reloc_overflow; + } + + relocation >>= (bfd_vma)howto->rightshift; + + /* Shift everything up to where it's going to be used. */ + + relocation <<= (bfd_vma)howto->bitpos; + +#define DOIT(x) \ + x = ( (x & ~howto->dst_mask) | (relocation & howto->dst_mask)) + + /* handle 8 and 16 bit relocations here. */ + switch (howto->size) + { + case 0: + { + char x = bfd_get_8(abfd, (char *)data + addr); + DOIT(x); + bfd_put_8(abfd, x, (unsigned char *)data + addr); + } + break; + + case 1: + { + unsigned short x = bfd_get_16(abfd, (bfd_byte *)data + addr); + DOIT(x); + bfd_put_16(abfd, (bfd_vma)x, (unsigned char *)data + addr); + } + break; + + default: + return bfd_reloc_other; + } + + return bfd_reloc_ok; +} + +/* HOWTO Table for esp ulp. + */ + +#define ESP32S2ULP_RELOC_MIN 0 +#define ESP32S2ULP_RELOC_MAX 0x21 +#define ESP32S2ULP_GNUEXT_RELOC_MIN 0x40 +#define ESP32S2ULP_GNUEXT_RELOC_MAX 0x43 +#define ESP32S2ULP_ARELOC_MIN 0xE0 +#define ESP32S2ULP_ARELOC_MAX 0xF3 + +static reloc_howto_type esp32s2ulp_howto_table[] = +{ + /* This reloc does nothing. . */ + HOWTO(R_ESP32S2ULP_UNUSED0, /* type. */ + 0, /* rightshift. */ + 3, /* size (0 = byte, 1 = short, 2 = long). */ + 0, /* bitsize. */ + FALSE, /* pc_relative. */ + 0, /* bitpos. */ + complain_overflow_dont, /* complain_on_overflow. */ + bfd_elf_generic_reloc, /* special_function. */ + "R_ESP32S2ULP_UNUSED0", /* name. */ + FALSE, /* partial_inplace. */ + 0, /* src_mask. */ + 0, /* dst_mask. */ + FALSE), /* pcrel_offset. */ + + + HOWTO(R_ESP32S2ULP_RIMM16, /* type. */ + 0, /* rightshift. */ + 2, /* size (0 = byte, 1 = short, 2 = long). */ + 11, /* bitsize. */ + FALSE, /* pc_relative. */ + 2, /* bitpos. */ + complain_overflow_unsigned, /* complain_on_overflow. */ + NULL, /* special_function. */ + "R_ESP32S2ULP_RIMM16", /* name. */ + FALSE, /* partial_inplace. */ + 0x00001FFC, /* src_mask. */ // dya-pass - 0 + 0x00001FFC, /* dst_mask. */ + FALSE), /* pcrel_offset. */ + + HOWTO(R_ESP32S2ULP_JUMPR, /* type. */ + 0, /* rightshift. */ + 2, /* size (0 = byte, 1 = short, 2 = long). */ + 8, /* bitsize. */ + TRUE, /* pc_relative. */ + 18, /* bitpos. */ + complain_overflow_signed, /* complain_on_overflow. */ + esp32s2ulp_jumprelr_reloc, /* special_function. */ + "R_ESP32S2ULP_JUMPR", /* name. */ + FALSE, /* partial_inplace. */ + (0xff << 18), /* src_mask. */ + (0xff << 18), /* dst_mask. */ + TRUE), /* pcrel_offset. */ + + HOWTO(R_ESP32S2ULP_LOAD16, /* type. */ + 0, /* rightshift. */ + 2, /* size (0 = byte, 1 = short, 2 = long). */ + 11, /* bitsize. */ + FALSE, /* pc_relative. */ + 2, /* bitpos. */ + complain_overflow_unsigned, /* complain_on_overflow. */ + NULL, /* special_function. */ + "R_ESP32S2ULP_LOAD16", /* name. */ + FALSE, /* partial_inplace. */ + 0x00001FFC, /* src_mask. */ // dya-pass - 0 + 0x00001FFC, /* dst_mask. */ + FALSE), /* pcrel_offset. */ + + HOWTO(R_ESP32S2ULP_WR_MEM, /* type. */ + 0, /* rightshift. */ + 2, /* size (0 = byte, 1 = short, 2 = long). */ + 16, /* bitsize. */ + FALSE, /* pc_relative. */ + 8, /* bitpos. */ + complain_overflow_unsigned, /* complain_on_overflow. */ + NULL, /* special_function. */ + "R_ESP32S2ULP_WR_MEM", /* name. */ + FALSE, /* partial_inplace. */ + (0x7ff << 10), /* src_mask. */ // dya-pass - 0 + (0x7ff << 10), /* dst_mask. */ + FALSE), /* pcrel_offset. */ + + HOWTO(R_ESP32S2ULP_ALUI, /* type. */ + 0, /* rightshift. */ + 2, /* size (0 = byte, 1 = short, 2 = long). */ + 16, /* bitsize. */ + FALSE, /* pc_relative. */ + 4, /* bitpos. */ + complain_overflow_signed, /* complain_on_overflow. */ + NULL, /* special_function. */ + "R_ESP32S2ULP_ALUI", /* name. */ + FALSE, /* partial_inplace. */ + (0x00ffff << 4), /* src_mask. */ // dya-pass - 0 + (0x00ffff << 4), /* dst_mask. */ + FALSE), /* pcrel_offset. */ + + HOWTO(R_ESP32S2ULP_WAIT, /* type. */ + 0, /* rightshift. */ + 2, /* size (0 = byte, 1 = short, 2 = long). */ + 16, /* bitsize. */ + FALSE, /* pc_relative. */ + 0, /* bitpos. */ + complain_overflow_unsigned, /* complain_on_overflow. */ + NULL, /* special_function. */ + "R_ESP32S2ULP_WAIT", /* name. */ + FALSE, /* partial_inplace. */ + (0x00ffff << 0), /* src_mask. */ // dya-pass - 0 + (0x00ffff << 0), /* dst_mask. */ + FALSE), /* pcrel_offset. */ + + HOWTO(R_ESP32S2ULP_TSENS_CYCLE, /* type. */ + 0, /* rightshift. */ + 2, /* size (0 = byte, 1 = short, 2 = long). */ + 12, /* bitsize. */ + FALSE, /* pc_relative. */ + 16, /* bitpos. */ + complain_overflow_unsigned, /* complain_on_overflow. */ + NULL, /* special_function. */ + "R_ESP32S2ULP_TSENS_CYCLE", /* name. */ + FALSE, /* partial_inplace. */ + (0xfff << 16), /* src_mask. */ // dya-pass - 0 + (0xfff << 16), /* dst_mask. */ + FALSE), /* pcrel_offset. */ + + HOWTO(R_ESP32S2ULP_TSENS_DELAY, /* type. */ + 0, /* rightshift. */ + 2, /* size (0 = byte, 1 = short, 2 = long). */ + 14, /* bitsize. */ + FALSE, /* pc_relative. */ + 2, /* bitpos. */ + complain_overflow_unsigned, /* complain_on_overflow. */ + NULL, /* special_function. */ + "R_ESP32S2ULP_TSENS_DELAY", /* name. */ + FALSE, /* partial_inplace. */ + (0x3fff << 2), /* src_mask. */ // dya-pass - 0 + (0x3fff << 2), /* dst_mask. */ + FALSE), /* pcrel_offset. */ + + + HOWTO(R_ESP32S2ULP_ADC_CYCLE, /* type. */ + 0, /* rightshift. */ + 2, /* size (0 = byte, 1 = short, 2 = long). */ + 16, /* bitsize. */ + FALSE, /* pc_relative. */ + 8, /* bitpos. */ + complain_overflow_unsigned, /* complain_on_overflow. */ + NULL, /* special_function. */ + "R_ESP32S2ULP_ADC_CYCLE", /* name. */ + FALSE, /* partial_inplace. */ + (0x00ffff << 8), /* src_mask. */ // dya-pass - 0 + (0x00ffff << 8), /* dst_mask. */ + FALSE), /* pcrel_offset. */ + + + HOWTO(R_ESP32S2ULP_ADC_SEL, /* type. */ + 0, /* rightshift. */ + 2, /* size (0 = byte, 1 = short, 2 = long). */ + 1, /* bitsize. */ + FALSE, /* pc_relative. */ + 6, /* bitpos. */ + complain_overflow_unsigned, /* complain_on_overflow. */ + NULL, /* special_function. */ + "R_ESP32S2ULP_ADC_SEL", /* name. */ + FALSE, /* partial_inplace. */ + (0x1 << 6), /* src_mask. */ // dya-pass - 0 + (0x1 << 6), /* dst_mask. */ + FALSE), /* pcrel_offset. */ + + + HOWTO(R_ESP32S2ULP_ADC_MUX, /* type. */ + 0, /* rightshift. */ + 2, /* size (0 = byte, 1 = short, 2 = long). */ + 4, /* bitsize. */ + FALSE, /* pc_relative. */ + 2, /* bitpos. */ + complain_overflow_unsigned, /* complain_on_overflow. */ + NULL, /* special_function. */ + "R_ESP32S2ULP_ADC_MUX", /* name. */ + FALSE, /* partial_inplace. */ + (0x0f << 2), /* src_mask. */ // dya-pass - 0 + (0x0f << 2), /* dst_mask. */ + FALSE), /* pcrel_offset. */ + + + HOWTO(R_ESP32S2ULP_WAKE, /* type. */ + 0, /* rightshift. */ + 2, /* size (0 = byte, 1 = short, 2 = long). */ + 1, /* bitsize. */ + FALSE, /* pc_relative. */ + 0, /* bitpos. */ + complain_overflow_unsigned, /* complain_on_overflow. */ + NULL, /* special_function. */ + "R_ESP32S2ULP_WAKE", /* name. */ + FALSE, /* partial_inplace. */ + (0x1 << 0), /* src_mask. */ // dya-pass - 0 + (0x1 << 0), /* dst_mask. */ + FALSE), /* pcrel_offset. */ + + + HOWTO(R_ESP32S2ULP_SLEEP, /* type. */ + 0, /* rightshift. */ + 2, /* size (0 = byte, 1 = short, 2 = long). */ + 16, /* bitsize. */ + FALSE, /* pc_relative. */ + 0, /* bitpos. */ + complain_overflow_unsigned, /* complain_on_overflow. */ + NULL, /* special_function. */ + "R_ESP32S2ULP_SLEEP", /* name. */ + FALSE, /* partial_inplace. */ + (0xffff << 0), /* src_mask. */ // dya-pass - 0 + (0xffff << 0), /* dst_mask. */ + FALSE), /* pcrel_offset. */ + + HOWTO(R_ESP32S2ULP_STAGE, /* type. */ + 0, /* rightshift. */ + 2, /* size (0 = byte, 1 = short, 2 = long). */ + 16, /* bitsize. */ + FALSE, /* pc_relative. */ + 4, /* bitpos. */ + complain_overflow_signed, /* complain_on_overflow. */ + NULL, /* special_function. */ + "R_ESP32S2ULP_STAGE", /* name. */ + FALSE, /* partial_inplace. */ + (0x00ff << 4), /* src_mask. */ // dya-pass - 0 + (0x00ff << 4), /* dst_mask. */ + FALSE), /* pcrel_offset. */ + + + HOWTO(R_ESP32S2ULP_JUMPR_STEP, /* type. */ + 0, /* rightshift. */ + 2, /* size (0 = byte, 1 = short, 2 = long). */ + 8, /* bitsize. */ + TRUE, /* pc_relative. */ + 18, /* bitpos. */ + complain_overflow_signed, /* complain_on_overflow. */ + esp32s2ulp_jumprelr_reloc, /* special_function. */ + "R_ESP32S2ULP_JUMPR_STEP", /* name. */ + FALSE, /* partial_inplace. */ + (0x00ff << 18), /* src_mask. */ + (0x00ff << 18), /* dst_mask. */ + TRUE), /* pcrel_offset. */ + + + HOWTO(R_ESP32S2ULP_JUMPR_THRESH, /* type. */ + 0, /* rightshift. */ + 2, /* size (0 = byte, 1 = short, 2 = long). */ + 16, /* bitsize. */ + FALSE, /* pc_relative. */ + 0, /* bitpos. */ + complain_overflow_signed, /* complain_on_overflow. */ + NULL, /* special_function. */ + "R_ESP32S2ULP_JUMPR_THRESH", /* name. */ + FALSE, /* partial_inplace. */ + (0x00ffff << 0), /* src_mask. */ // dya-pass - 0 + (0x00ffff << 0), /* dst_mask. */ + FALSE), /* pcrel_offset. */ + + HOWTO(R_ESP32S2ULP_JUMPS_THRESH, /* type. */ + 0, /* rightshift. */ + 2, /* size (0 = byte, 1 = short, 2 = long). */ + 8, /* bitsize. */ + FALSE, /* pc_relative. */ + 0, /* bitpos. */ + complain_overflow_signed, /* complain_on_overflow. */ + NULL, /* special_function. */ + "R_ESP32S2ULP_JUMPS_THRESH", /* name. */ + FALSE, /* partial_inplace. */ + (0x00ff << 0), /* src_mask. */ // dya-pass - 0 + (0x00ff << 0), /* dst_mask. */ + FALSE), /* pcrel_offset. */ + + HOWTO(R_ESP32S2ULP_REG_RW_HIGH, /* type. */ + 0, /* rightshift. */ + 2, /* size (0 = byte, 1 = short, 2 = long). */ + 5, /* bitsize. */ + FALSE, /* pc_relative. */ + 23, /* bitpos. */ + complain_overflow_unsigned, /* complain_on_overflow. */ + NULL, /* special_function. */ + "R_ESP32S2ULP_REG_RW_HIGH", /* name. */ + FALSE, /* partial_inplace. */ + (0x3f << 23), /* src_mask. */ // dya-pass - 0 + (0x3f << 23), /* dst_mask. */ + FALSE), /* pcrel_offset. */ + + HOWTO(R_ESP32S2ULP_REG_RW_LOW, /* type. */ + 0, /* rightshift. */ + 2, /* size (0 = byte, 1 = short, 2 = long). */ + 5, /* bitsize. */ + FALSE, /* pc_relative. */ + 18, /* bitpos. */ + complain_overflow_unsigned, /* complain_on_overflow. */ + NULL, /* special_function. */ + "R_ESP32S2ULP_REG_RW_LOW", /* name. */ + FALSE, /* partial_inplace. */ + (0x3f << 18), /* src_mask. */ // dya-pass - 0 + (0x3f << 18), /* dst_mask. */ + FALSE), /* pcrel_offset. */ + + HOWTO(R_ESP32S2ULP_REG_RW_ADDR, /* type. */ + 0, /* rightshift. */ + 2, /* size (0 = byte, 1 = short, 2 = long). */ + 10, /* bitsize. */ + FALSE, /* pc_relative. */ + 0, /* bitpos. */ + complain_overflow_unsigned, /* complain_on_overflow. */ + NULL, /* special_function. */ + "R_ESP32S2ULP_REG_RW_ADDR", /* name. */ + FALSE, /* partial_inplace. */ + (0x3ff << 0), /* src_mask. */ // dya-pass - 0 + (0x3ff << 0), /* dst_mask. */ + FALSE), /* pcrel_offset. */ + + HOWTO(R_ESP32S2ULP_REG_RW_DATA, /* type. */ + 0, /* rightshift. */ + 2, /* size (0 = byte, 1 = short, 2 = long). */ + 8, /* bitsize. */ + FALSE, /* pc_relative. */ + 10, /* bitpos. */ + complain_overflow_unsigned, /* complain_on_overflow. */ + NULL, /* special_function. */ + "R_ESP32S2ULP_REG_RW_DATA", /* name. */ + FALSE, /* partial_inplace. */ + (0x00ff << 10), /* src_mask. */ // dya-pass - 0 + (0x00ff << 10), /* dst_mask. */ + FALSE), /* pcrel_offset. */ + + HOWTO(R_ESP32S2ULP_I2C_RW_HIGH, /* type. */ + 0, /* rightshift. */ + 2, /* size (0 = byte, 1 = short, 2 = long). */ + 16, /* bitsize. */ + FALSE, /* pc_relative. */ + 19, /* bitpos. */ + complain_overflow_unsigned, /* complain_on_overflow. */ + NULL, /* special_function. */ + "R_ESP32S2ULP_I2C_RW_HIGH", /* name. */ + FALSE, /* partial_inplace. */ + (0x7 << 19), /* src_mask. */ // dya-pass - 0 + (0x7 << 19), /* dst_mask. */ + FALSE), /* pcrel_offset. */ + + HOWTO(R_ESP32S2ULP_I2C_RW_LOW, /* type. */ + 0, /* rightshift. */ + 2, /* size (0 = byte, 1 = short, 2 = long). */ + 16, /* bitsize. */ + FALSE, /* pc_relative. */ + 16, /* bitpos. */ + complain_overflow_unsigned, /* complain_on_overflow. */ + NULL, /* special_function. */ + "R_ESP32S2ULP_I2C_RW_LOW", /* name. */ + FALSE, /* partial_inplace. */ + (0x7 << 16), /* src_mask. */ // dya-pass - 0 + (0x7 << 16), /* dst_mask. */ + FALSE), /* pcrel_offset. */ + + HOWTO(R_ESP32S2ULP_I2C_RW_ADDR, /* type. */ + 0, /* rightshift. */ + 2, /* size (0 = byte, 1 = short, 2 = long). */ + 8, /* bitsize. */ + FALSE, /* pc_relative. */ + 0, /* bitpos. */ + complain_overflow_unsigned, /* complain_on_overflow. */ + NULL, /* special_function. */ + "R_ESP32S2ULP_I2C_RW_ADDR", /* name. */ + FALSE, /* partial_inplace. */ + (0xff << 0), /* src_mask. */ // dya-pass - 0 + (0xff << 0), /* dst_mask. */ + FALSE), /* pcrel_offset. */ + + HOWTO(R_ESP32S2ULP_I2C_RW_DATA, /* type. */ + 0, /* rightshift. */ + 2, /* size (0 = byte, 1 = short, 2 = long). */ + 16, /* bitsize. */ + FALSE, /* pc_relative. */ + 8, /* bitpos. */ + complain_overflow_unsigned, /* complain_on_overflow. */ + NULL, /* special_function. */ + "R_ESP32S2ULP_I2C_RW_DATA", /* name. */ + FALSE, /* partial_inplace. */ + (0x00ff << 8), /* src_mask. */ // dya-pass - 0 + (0x00ff << 8), /* dst_mask. */ + FALSE), /* pcrel_offset. */ + + HOWTO(R_ESP32S2ULP_I2C_RW_SEL, /* type. */ + 0, /* rightshift. */ + 2, /* size (0 = byte, 1 = short, 2 = long). */ + 16, /* bitsize. */ + FALSE, /* pc_relative. */ + 22, /* bitpos. */ + complain_overflow_unsigned, /* complain_on_overflow. */ + NULL, /* special_function. */ + "R_ESP32S2ULP_I2C_RW_SEL", /* name. */ + FALSE, /* partial_inplace. */ + (0xf << 22), /* src_mask. */ // dya-pass - 0 + (0xf << 22), /* dst_mask. */ + FALSE), /* pcrel_offset. */ + + HOWTO(R_ESP32S2ULP_WR_MEM_LABEL,/* type. */ + 0, /* rightshift. */ + 2, /* size (0 = byte, 1 = short, 2 = long). */ + 2, /* bitsize. */ + FALSE, /* pc_relative. */ + 4, /* bitpos. */ + complain_overflow_unsigned, /* complain_on_overflow. */ + NULL, /* special_function. */ + "R_ESP32S2ULP_WR_MEM_LABEL", /* name. */ + FALSE, /* partial_inplace. */ + (0x3 << 4), /* src_mask. */ // dya-pass - 0 + (0x3 << 4), /* dst_mask. */ + FALSE), /* pcrel_offset. */ + + + HOWTO(R_ESP32S2ULP_RESERVE, /* type. */ + 0, /* rightshift. */ + 2, /* size (0 = byte, 1 = short, 2 = long). */ + 8, /* bitsize. */ + TRUE, /* pc_relative. */ + 17, /* bitpos. */ + complain_overflow_signed, /* complain_on_overflow. */ + esp32s2ulp_bfd_reloc, /* special_function. */ + "R_ESP32S2ULP_RESERVE", /* name. */ + FALSE, /* partial_inplace. */ + 0x01fe0000, /* src_mask. */ + 0x01fe0000, /* dst_mask. */ + TRUE), /* pcrel_offset. */ +}; + +static reloc_howto_type esp32s2ulp_gnuext_howto_table[] = +{ + HOWTO(R_ESP32S2ULP_PLTPC, /* type. */ + 0, /* rightshift. */ + 1, /* size (0 = byte, 1 = short, 2 = long). */ + 16, /* bitsize. */ + FALSE, /* pc_relative. */ + 0, /* bitpos. */ + complain_overflow_bitfield, /* complain_on_overflow. */ + esp32s2ulp_pltpc_reloc, /* special_function. */ + "R_ESP32S2ULP_PLTPC", /* name. */ + FALSE, /* partial_inplace. */ + 0xffff, /* src_mask. */ + 0xffff, /* dst_mask. */ + FALSE), /* pcrel_offset. */ + + HOWTO(R_ESP32S2ULP_GOT, /* type. */ + 0, /* rightshift. */ + 1, /* size (0 = byte, 1 = short, 2 = long). */ + 16, /* bitsize. */ + FALSE, /* pc_relative. */ + 0, /* bitpos. */ + complain_overflow_bitfield, /* complain_on_overflow. */ + bfd_elf_generic_reloc, /* special_function. */ + "R_ESP32S2ULP_GOT", /* name. */ + FALSE, /* partial_inplace. */ + 0x7fff, /* src_mask. */ + 0x7fff, /* dst_mask. */ + FALSE), /* pcrel_offset. */ + + /* GNU extension to record C++ vtable hierarchy. */ + HOWTO(R_ESP32S2ULP_GNU_VTINHERIT, /* type. */ + 0, /* rightshift. */ + 2, /* size (0 = byte, 1 = short, 2 = long). */ + 0, /* bitsize. */ + FALSE, /* pc_relative. */ + 0, /* bitpos. */ + complain_overflow_dont, /* complain_on_overflow. */ + NULL, /* special_function. */ + "R_ESP32S2ULP_GNU_VTINHERIT", /* name. */ + FALSE, /* partial_inplace. */ + 0, /* src_mask. */ + 0, /* dst_mask. */ + FALSE), /* pcrel_offset. */ + + /* GNU extension to record C++ vtable member usage. */ + HOWTO(R_ESP32S2ULP_GNU_VTENTRY, /* type. */ + 0, /* rightshift. */ + 2, /* size (0 = byte, 1 = short, 2 = long). */ + 0, /* bitsize. */ + FALSE, /* pc_relative. */ + 0, /* bitpos. */ + complain_overflow_dont, /* complain_on_overflow. */ + _bfd_elf_rel_vtable_reloc_fn, /* special_function. */ + "R_ESP32S2ULP_GNU_VTENTRY", /* name. */ + FALSE, /* partial_inplace. */ + 0, /* src_mask. */ + 0, /* dst_mask. */ + FALSE) /* pcrel_offset. */ +}; + +struct esp32s2ulp_reloc_map +{ + bfd_reloc_code_real_type bfd_reloc_val; + unsigned int esp32s2ulp_reloc_val; +}; + +static const struct esp32s2ulp_reloc_map esp32s2ulp_reloc_map[] = +{ + { BFD_RELOC_NONE, R_ESP32S2ULP_UNUSED0 }, + { BFD_RELOC_ESP32S2ULP_16_IMM, R_ESP32S2ULP_RIMM16 }, + { BFD_RELOC_ESP32S2ULP_JUMPR, R_ESP32S2ULP_JUMPR }, + { BFD_RELOC_ESP32S2ULP_16_LOAD, R_ESP32S2ULP_LOAD16 }, + { BFD_RELOC_ESP32S2ULP_WR_MEM, R_ESP32S2ULP_WR_MEM }, + { BFD_RELOC_ESP32S2ULP_ALUI, R_ESP32S2ULP_ALUI }, + { BFD_RELOC_ESP32S2ULP_WAIT, R_ESP32S2ULP_WAIT }, + { BFD_RELOC_ESP32S2ULP_TSENS_CYCLE, R_ESP32S2ULP_TSENS_CYCLE }, + { BFD_RELOC_ESP32S2ULP_TSENS_DELAY, R_ESP32S2ULP_TSENS_DELAY }, + + { BFD_RELOC_ESP32S2ULP_ADC_CYCLE, R_ESP32S2ULP_ADC_CYCLE }, + { BFD_RELOC_ESP32S2ULP_ADC_SEL, R_ESP32S2ULP_ADC_SEL }, + { BFD_RELOC_ESP32S2ULP_ADC_MUX, R_ESP32S2ULP_ADC_MUX }, + { BFD_RELOC_ESP32S2ULP_WAKE, R_ESP32S2ULP_WAKE }, + { BFD_RELOC_ESP32S2ULP_SLEEP, R_ESP32S2ULP_SLEEP }, + + { BFD_RELOC_ESP32S2ULP_STAGE, R_ESP32S2ULP_STAGE }, + + { BFD_RELOC_ESP32S2ULP_JUMPR_STEP, R_ESP32S2ULP_JUMPR_STEP }, + { BFD_RELOC_ESP32S2ULP_JUMPR_THRESH, R_ESP32S2ULP_JUMPR_THRESH }, + { BFD_RELOC_ESP32S2ULP_JUMPS_THRESH, R_ESP32S2ULP_JUMPS_THRESH }, + + { BFD_RELOC_ESP32S2ULP_REG_RW_HIGH, R_ESP32S2ULP_REG_RW_HIGH }, + { BFD_RELOC_ESP32S2ULP_REG_RW_LOW, R_ESP32S2ULP_REG_RW_LOW }, + { BFD_RELOC_ESP32S2ULP_REG_RW_ADDR, R_ESP32S2ULP_REG_RW_ADDR }, + { BFD_RELOC_ESP32S2ULP_REG_RW_DATA, R_ESP32S2ULP_REG_RW_DATA }, + + { BFD_RELOC_ESP32S2ULP_I2C_RW_HIGH, R_ESP32S2ULP_I2C_RW_HIGH }, + { BFD_RELOC_ESP32S2ULP_I2C_RW_LOW, R_ESP32S2ULP_I2C_RW_LOW }, + { BFD_RELOC_ESP32S2ULP_I2C_RW_ADDR, R_ESP32S2ULP_I2C_RW_ADDR }, + { BFD_RELOC_ESP32S2ULP_I2C_RW_DATA, R_ESP32S2ULP_I2C_RW_DATA }, + { BFD_RELOC_ESP32S2ULP_I2C_RW_SEL, R_ESP32S2ULP_I2C_RW_SEL }, + + { BFD_RELOC_ESP32S2ULP_WR_MEM_LABEL, R_ESP32S2ULP_WR_MEM_LABEL }, + + { BFD_RELOC_ESP32S2ULP_RESERVE, R_ESP32S2ULP_RESERVE }, + + { BFD_RELOC_ESP32S2ULP_GOT, R_ESP32S2ULP_GOT }, + { BFD_RELOC_ESP32S2ULP_PLTPC, R_ESP32S2ULP_PLTPC }, + + { BFD_RELOC_VTABLE_INHERIT, R_ESP32S2ULP_GNU_VTINHERIT }, + { BFD_RELOC_VTABLE_ENTRY, R_ESP32S2ULP_GNU_VTENTRY }, +}; + + +static void +esp32s2ulp_info_to_howto(bfd *abfd ATTRIBUTE_UNUSED, +arelent *cache_ptr, +Elf_Internal_Rela *dst) +{ + unsigned int r_type; + + r_type = ELF32_R_TYPE(dst->r_info); + + if (r_type <= ESP32S2ULP_RELOC_MAX) + cache_ptr->howto = &esp32s2ulp_howto_table[r_type]; + + else if (r_type >= ESP32S2ULP_GNUEXT_RELOC_MIN && r_type <= ESP32S2ULP_GNUEXT_RELOC_MAX) + cache_ptr->howto = &esp32s2ulp_gnuext_howto_table[r_type - ESP32S2ULP_GNUEXT_RELOC_MIN]; + + else + cache_ptr->howto = (reloc_howto_type *)NULL; +} + +/* Given a BFD reloc type, return the howto. */ +static reloc_howto_type * +esp32s2ulp_bfd_reloc_type_lookup(bfd * abfd ATTRIBUTE_UNUSED, +bfd_reloc_code_real_type code) +{ + unsigned int i; + unsigned int r_type = (unsigned int)-1; + + for (i = sizeof(esp32s2ulp_reloc_map) / sizeof(esp32s2ulp_reloc_map[0]); i--;) + if (esp32s2ulp_reloc_map[i].bfd_reloc_val == code) + r_type = esp32s2ulp_reloc_map[i].esp32s2ulp_reloc_val; + + if (r_type <= ESP32S2ULP_RELOC_MAX) + return &esp32s2ulp_howto_table[r_type]; + + else if (r_type >= ESP32S2ULP_GNUEXT_RELOC_MIN && r_type <= ESP32S2ULP_GNUEXT_RELOC_MAX) + return &esp32s2ulp_gnuext_howto_table[r_type - ESP32S2ULP_GNUEXT_RELOC_MIN]; + + return (reloc_howto_type *)NULL; +} + +static reloc_howto_type * +esp32s2ulp_bfd_reloc_name_lookup(bfd *abfd ATTRIBUTE_UNUSED, +const char *r_name) +{ + unsigned int i; + + for (i = 0; + i < (sizeof(esp32s2ulp_howto_table) + / sizeof(esp32s2ulp_howto_table[0])); + i++) + if (esp32s2ulp_howto_table[i].name != NULL + && strcasecmp(esp32s2ulp_howto_table[i].name, r_name) == 0) + return &esp32s2ulp_howto_table[i]; + + for (i = 0; + i < (sizeof(esp32s2ulp_gnuext_howto_table) + / sizeof(esp32s2ulp_gnuext_howto_table[0])); + i++) + if (esp32s2ulp_gnuext_howto_table[i].name != NULL + && strcasecmp(esp32s2ulp_gnuext_howto_table[i].name, r_name) == 0) + return &esp32s2ulp_gnuext_howto_table[i]; + + return NULL; +} + +/* Given a esp32s2ulp relocation type, return the howto. */ +static reloc_howto_type * +esp32s2ulp_reloc_type_lookup(bfd * abfd ATTRIBUTE_UNUSED, +unsigned int r_type) +{ + if (r_type <= ESP32S2ULP_RELOC_MAX) + return &esp32s2ulp_howto_table[r_type]; + + else if (r_type >= ESP32S2ULP_GNUEXT_RELOC_MIN && r_type <= ESP32S2ULP_GNUEXT_RELOC_MAX) + return &esp32s2ulp_gnuext_howto_table[r_type - ESP32S2ULP_GNUEXT_RELOC_MIN]; + + return (reloc_howto_type *)NULL; +} +// +///* Set by ld emulation if --code-in-l1. */ +//bfd_boolean elf32_esp32s2ulp_code_in_l1 = 0; +// +///* Set by ld emulation if --data-in-l1. */ +//bfd_boolean elf32_esp32s2ulp_data_in_l1 = 0; + +static void +elf32_esp32s2ulp_final_write_processing(bfd *abfd, +bfd_boolean linker ATTRIBUTE_UNUSED) +{ + (void)abfd; + (void)linker; +} + +/* Return TRUE if the name is a local label. +esp32s2ulp local labels begin with L$. */ +static bfd_boolean +esp32s2ulp_is_local_label_name(bfd *abfd, const char *label) +{ + if (label[0] == 'L' && label[1] == '$') + return TRUE; + + return _bfd_elf_is_local_label_name(abfd, label); +} + +/* Look through the relocs for a section during the first phase, and +allocate space in the global offset table or procedure linkage +table. */ + +static bfd_boolean +esp32s2ulp_check_relocs(bfd * abfd, +struct bfd_link_info *info, + asection *sec, + const Elf_Internal_Rela *relocs) +{ + bfd *dynobj; + Elf_Internal_Shdr *symtab_hdr; + struct elf_link_hash_entry **sym_hashes; + bfd_signed_vma *local_got_refcounts; + const Elf_Internal_Rela *rel; + const Elf_Internal_Rela *rel_end; + asection *sgot; + asection *srelgot; + + if (bfd_link_relocatable(info)) + return TRUE; + + dynobj = elf_hash_table(info)->dynobj; + symtab_hdr = &elf_tdata(abfd)->symtab_hdr; + sym_hashes = elf_sym_hashes(abfd); + local_got_refcounts = elf_local_got_refcounts(abfd); + + sgot = NULL; + srelgot = NULL; + + rel_end = relocs + sec->reloc_count; + for (rel = relocs; rel < rel_end; rel++) + { + unsigned long r_symndx; + struct elf_link_hash_entry *h; + + r_symndx = ELF32_R_SYM(rel->r_info); + if (r_symndx < symtab_hdr->sh_info) + h = NULL; + else + { + h = sym_hashes[r_symndx - symtab_hdr->sh_info]; + + /* PR15323, ref flags aren't set for references in the same + object. */ + h->root.non_ir_ref = 1; + } + + switch (ELF32_R_TYPE(rel->r_info)) + { + /* This relocation describes the C++ object vtable hierarchy. + Reconstruct it for later use during GC. */ + case R_ESP32S2ULP_GNU_VTINHERIT: + if (!bfd_elf_gc_record_vtinherit(abfd, sec, h, rel->r_offset)) + return FALSE; + break; + + /* This relocation describes which C++ vtable entries + are actually used. Record for later use during GC. */ + case R_ESP32S2ULP_GNU_VTENTRY: + BFD_ASSERT(h != NULL); + if (h != NULL + && !bfd_elf_gc_record_vtentry(abfd, sec, h, rel->r_addend)) + return FALSE; + break; + + case R_ESP32S2ULP_GOT: + if (h != NULL + && strcmp(h->root.root.string, "__GLOBAL_OFFSET_TABLE_") == 0) + break; + /* Fall through. */ + + if (dynobj == NULL) + { + /* Create the .got section. */ + elf_hash_table(info)->dynobj = dynobj = abfd; + if (!_bfd_elf_create_got_section(dynobj, info)) + return FALSE; + } + + sgot = elf_hash_table(info)->sgot; + srelgot = elf_hash_table(info)->srelgot; + BFD_ASSERT(sgot != NULL); + + if (h != NULL) + { + if (h->got.refcount == 0) + { + /* Make sure this symbol is output as a dynamic symbol. */ + if (h->dynindx == -1 && !h->forced_local) + { + if (!bfd_elf_link_record_dynamic_symbol(info, h)) + return FALSE; + } + + /* Allocate space in the .got section. */ + sgot->size += 4; + /* Allocate relocation space. */ + srelgot->size += sizeof(Elf32_External_Rela); + } + h->got.refcount++; + } + else + { + /* This is a global offset table entry for a local symbol. */ + if (local_got_refcounts == NULL) + { + bfd_size_type size; + + size = symtab_hdr->sh_info; + size *= sizeof(bfd_signed_vma); + local_got_refcounts = ((bfd_signed_vma *) + bfd_zalloc(abfd, size)); + if (local_got_refcounts == NULL) + return FALSE; + elf_local_got_refcounts(abfd) = local_got_refcounts; + } + if (local_got_refcounts[r_symndx] == 0) + { + sgot->size += 4; + if (bfd_link_pic(info)) + { + /* If we are generating a shared object, we need to + output a R_68K_RELATIVE reloc so that the dynamic + linker can adjust this GOT entry. */ + srelgot->size += sizeof(Elf32_External_Rela); + } + } + local_got_refcounts[r_symndx]++; + } + break; + + default: + break; + } + } + + return TRUE; +} + +static enum elf_reloc_type_class +elf32_esp32s2ulp_reloc_type_class(const struct bfd_link_info *info ATTRIBUTE_UNUSED, +const asection *rel_sec ATTRIBUTE_UNUSED, +const Elf_Internal_Rela * rela) +{ + switch ((int)ELF32_R_TYPE(rela->r_info)) + { + default: + return reloc_class_normal; + } +} + +static bfd_reloc_status_type +esp32s2ulp_final_link_relocate(Elf_Internal_Rela *rel, reloc_howto_type *howto, +bfd *input_bfd, asection *input_section, +bfd_byte *contents, bfd_vma address, +bfd_vma value, bfd_vma addend) +{ + int r_type = ELF32_R_TYPE(rel->r_info); + //DEBUG_TRACE("dya_pass - esp32s2ulp_final_link_relocate r_type=%i, addend=%i\n", r_type, (unsigned int)addend); + if ((r_type == R_ESP32S2ULP_JUMPR) || (r_type == R_ESP32S2ULP_JUMPR_STEP)) + { + bfd_reloc_status_type r = bfd_reloc_ok; + + if (address > bfd_get_section_limit(input_bfd, input_section)) + return bfd_reloc_outofrange; + + value = value << 2; + //printf("intput value = %i, ", (int)value); + value += addend; + + /* Perform usual pc-relative correction. */ + value -= input_section->output_section->vma + input_section->output_offset; + value -= address; + + Elf_Internal_Shdr * symtab_hdr = &elf_tdata(input_bfd)->symtab_hdr; + + unsigned long r_symndx = ELF32_R_SYM(rel->r_info); + + unsigned int ddd = 0; + memcpy(&ddd, contents + address, 4); + ddd &= ~(0xff << 18); + int compare = (int)value; + compare = compare >> 2; + //printf("final reloc, compare=%i, value=%i, addend=%i, address=%i, vma=%i, flags=%08x, r_symndx=%08x, symtab_hdr->sh_info=%08x\n", compare, (unsigned int)value, (unsigned int)addend, (unsigned int)address, (unsigned int)input_section->output_section->vma, (unsigned int)input_section->flags, (unsigned int)r_symndx, (unsigned int)symtab_hdr->sh_info); + if (r_symndx >= symtab_hdr->sh_info) // Apply only for global symbols + { + if ((compare > 127) || (compare < -128)) + { + return bfd_reloc_outofrange; + } +// ddd |= ((compare & 0x000000ff) << 18); + if ((compare) >= 0) + { + ddd |= ((compare & 0x0000007f) << 18); + } + else + { + compare = -compare; + ddd |= ((compare & 0x0000007f) << 18) | (1 << 25); + } + memcpy(contents + address, &ddd, 4); + } + //DEBUG_TRACE("dya_pass - esp32s2ulp_final_link_relocate: ddd=%08x, value=%08x, addr=%08x\n", ddd, (int)value, (int)address); + return r; + } + + return _bfd_final_link_relocate(howto, input_bfd, input_section, contents, + rel->r_offset, value, addend); + +} + + +#define ESP32S2ULP_RELOC_FOR_GLOBAL_SYMBOL(info, input_bfd, input_section, rel, \ + r_symndx, symtab_hdr, sym_hashes, \ + h, sec, relocation, \ + unresolved_reloc, warned, ignored, sectioin_flags) \ + do \ + { \ + /* It seems this can happen with erroneous or unsupported \ + input (mixing a.out and elf in an archive, for example.) */ \ + if (sym_hashes == NULL) \ + return FALSE; \ + \ + h = sym_hashes[r_symndx - symtab_hdr->sh_info]; \ + \ + if (info->wrap_hash != NULL \ + && (input_section->flags & SEC_DEBUGGING) != 0) \ + h = ((struct elf_link_hash_entry *) \ + unwrap_hash_lookup (info, input_bfd, &h->root)); \ + \ + while (h->root.type == bfd_link_hash_indirect \ + || h->root.type == bfd_link_hash_warning) \ + h = (struct elf_link_hash_entry *) h->root.u.i.link; \ + \ + warned = FALSE; \ + ignored = FALSE; \ + unresolved_reloc = FALSE; \ + relocation = 0; \ + if (h->root.type == bfd_link_hash_defined \ + || h->root.type == bfd_link_hash_defweak) \ + { \ + sec = h->root.u.def.section; \ + if (sec == NULL \ + || sec->output_section == NULL) \ + /* Set a flag that will be cleared later if we find a \ + relocation value for this symbol. output_section \ + is typically NULL for symbols satisfied by a shared \ + library. */ \ + unresolved_reloc = TRUE; \ + else \ + /*DEBUG_TRACE("ESP32S2ULP_RELOC_FOR_GLOBAL_SYMBOL - value = %08x, output_section->vma = %08x, sec->output_offset = %08x, sec->size = %08x, flags=%08x\n", (unsigned int)h->root.u.def.value, (unsigned int)sec->output_section->vma, (unsigned int)sec->output_offset, (unsigned int)sec->output_section->rawsize, (unsigned int)sec->flags);*/ \ + relocation = (h->root.u.def.value \ + + sec->output_section->vma \ + + sec->output_offset); \ + sectioin_flags = sec->flags; \ + } \ + else if (h->root.type == bfd_link_hash_undefweak) \ + ; \ + else if (info->unresolved_syms_in_objects == RM_IGNORE \ + && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT) \ + ignored = TRUE; \ + else if (!bfd_link_relocatable (info)) \ + { \ + bfd_boolean err; \ + err = (info->unresolved_syms_in_objects == RM_GENERATE_ERROR \ + || ELF_ST_VISIBILITY (h->other) != STV_DEFAULT); \ + (*info->callbacks->undefined_symbol) (info, \ + h->root.root.string, \ + input_bfd, \ + input_section, \ + rel->r_offset, err); \ + warned = TRUE; \ + } \ + (void) unresolved_reloc; \ + (void) warned; \ + (void) ignored; \ + } \ + while (0) + + + + + + + + +static bfd_boolean +esp32s2ulp_relocate_section(bfd * output_bfd, +struct bfd_link_info *info, + bfd * input_bfd, + asection * input_section, + bfd_byte * contents, + Elf_Internal_Rela * relocs, + Elf_Internal_Sym * local_syms, + asection ** local_sections) +{ + bfd *dynobj; + Elf_Internal_Shdr *symtab_hdr; + struct elf_link_hash_entry **sym_hashes; + bfd_vma *local_got_offsets; + asection *sgot; + Elf_Internal_Rela *rel; + Elf_Internal_Rela *relend; + int i = 0; + + dynobj = elf_hash_table(info)->dynobj; + symtab_hdr = &elf_tdata(input_bfd)->symtab_hdr; + sym_hashes = elf_sym_hashes(input_bfd); + local_got_offsets = elf_local_got_offsets(input_bfd); + + sgot = NULL; + + rel = relocs; + relend = relocs + input_section->reloc_count; + //DEBUG_TRACE("dya_pass - esp32s2ulp_relocate_section\n"); + for (; rel < relend; rel++, i++) + { + int r_type; + reloc_howto_type *howto; + unsigned long r_symndx; + struct elf_link_hash_entry *h; + Elf_Internal_Sym *sym; + asection *sec; + bfd_vma relocation = 0; + //bfd_vma old_reloc = relocation; + bfd_boolean unresolved_reloc; + bfd_reloc_status_type r; + bfd_vma address; + + r_type = ELF32_R_TYPE(rel->r_info); + if (r_type < 0 || r_type >= 243) + { + bfd_set_error(bfd_error_bad_value); + return FALSE; + } + + if (r_type == R_ESP32S2ULP_GNU_VTENTRY + || r_type == R_ESP32S2ULP_GNU_VTINHERIT) + continue; + + howto = esp32s2ulp_reloc_type_lookup(input_bfd, r_type); + if (howto == NULL) + { + bfd_set_error(bfd_error_bad_value); + return FALSE; + } + r_symndx = ELF32_R_SYM(rel->r_info); + + h = NULL; + sym = NULL; + sec = NULL; + unresolved_reloc = FALSE; + + unsigned int section_flags = 0; + + if (r_symndx < symtab_hdr->sh_info) + { + sym = local_syms + r_symndx; + sec = local_sections[r_symndx]; + relocation = _bfd_elf_rela_local_sym(output_bfd, sym, &sec, rel); + section_flags = sec->flags; + } + else + { + bfd_boolean warned, ignored; + ESP32S2ULP_RELOC_FOR_GLOBAL_SYMBOL(info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, + unresolved_reloc, warned, ignored, section_flags); + } + + if (sec != NULL && discarded_section(sec)) + RELOC_AGAINST_DISCARDED_SECTION(info, input_bfd, input_section, + rel, 1, relend, howto, 0, contents); + + if (bfd_link_relocatable(info)) + continue; + + address = rel->r_offset; + + /* Then, process normally. */ + //DEBUG_TRACE("dya_pass - esp32s2ulp_relocate_section r_type=%i\n", (int)r_type); + switch (r_type) + { + case R_ESP32S2ULP_GNU_VTINHERIT: + case R_ESP32S2ULP_GNU_VTENTRY: + return bfd_reloc_ok; + + case R_ESP32S2ULP_GOT: + /* Relocation is to the address of the entry for this symbol + in the global offset table. */ + if (h != NULL + && strcmp(h->root.root.string, "__GLOBAL_OFFSET_TABLE_") == 0) + goto do_default; + /* Fall through. */ + /* Relocation is the offset of the entry for this symbol in + the global offset table. */ + + { + bfd_vma off; + + if (dynobj == NULL) + { + /* Create the .got section. */ + elf_hash_table(info)->dynobj = dynobj = output_bfd; + if (!_bfd_elf_create_got_section(dynobj, info)) + return FALSE; + } + + sgot = elf_hash_table(info)->sgot; + BFD_ASSERT(sgot != NULL); + + if (h != NULL) + { + bfd_boolean dyn; + + off = h->got.offset; + BFD_ASSERT(off != (bfd_vma)-1); + dyn = elf_hash_table(info)->dynamic_sections_created; + + if (!WILL_CALL_FINISH_DYNAMIC_SYMBOL(dyn, + bfd_link_pic(info), + h) + || (bfd_link_pic(info) + && (info->symbolic + || h->dynindx == -1 + || h->forced_local) + && h->def_regular)) + { + /* This is actually a static link, or it is a + -Bsymbolic link and the symbol is defined + locally, or the symbol was forced to be local + because of a version file.. We must initialize + this entry in the global offset table. Since + the offset must always be a multiple of 4, we + use the least significant bit to record whether + we have initialized it already. + + When doing a dynamic link, we create a .rela.got + relocation entry to initialize the value. This + is done in the finish_dynamic_symbol routine. */ + if ((off & 1) != 0) + off &= ~1; + else + { + bfd_put_32(output_bfd, relocation, + sgot->contents + off); + h->got.offset |= 1; + } + } + else + unresolved_reloc = FALSE; + } + else + { + BFD_ASSERT(local_got_offsets != NULL); + off = local_got_offsets[r_symndx]; + BFD_ASSERT(off != (bfd_vma)-1); + + /* The offset must always be a multiple of 4. We use + the least significant bit to record whether we have + already generated the necessary reloc. */ + if ((off & 1) != 0) + off &= ~1; + else + { + bfd_put_32(output_bfd, relocation, sgot->contents + off); + + if (bfd_link_pic(info)) + { + asection *s; + Elf_Internal_Rela outrel; + bfd_byte *loc; + + s = elf_hash_table(info)->srelgot; + BFD_ASSERT(s != NULL); + + outrel.r_offset = (sgot->output_section->vma + + sgot->output_offset + off); + outrel.r_info = + ELF32_R_INFO(0, R_ESP32S2ULP_RIMM16); + outrel.r_addend = relocation; + loc = s->contents; + loc += + s->reloc_count++ * sizeof(Elf32_External_Rela); + bfd_elf32_swap_reloca_out(output_bfd, &outrel, loc); + } + + local_got_offsets[r_symndx] |= 1; + } + } + + relocation = sgot->output_offset + off; + rel->r_addend = 0; + /* esp32s2ulp : preg = [preg + 17bitdiv4offset] relocation is div by 4. */ + relocation /= 4; + } + goto do_default; + + default: + do_default : + //DEBUG_TRACE("dya_pass esp32s2ulp_final_link_relocate rel->r_addend=%i\n", (int)rel->r_addend); +// old_reloc = (unsigned int)relocation; + if (section_flags != 0) relocation = relocation >> 2; +// printf("relocation - 999 = %08x, old_reloc = %08x, input_section->flags = %08x, section name = %s\n", (unsigned int)relocation, (unsigned int)old_reloc, section_flags, input_section->name); + rel->r_addend = 0; // dya_pass + r = esp32s2ulp_final_link_relocate(rel, howto, input_bfd, input_section, + contents, address, + relocation, rel->r_addend); + + break; + } + + /* Dynamic relocs are not propagated for SEC_DEBUGGING sections + because such sections are not SEC_ALLOC and thus ld.so will + not process them. */ + if (unresolved_reloc + && !((input_section->flags & SEC_DEBUGGING) != 0 && h->def_dynamic) + && _bfd_elf_section_offset(output_bfd, info, input_section, + rel->r_offset) != (bfd_vma)-1) + { + _bfd_error_handler + /* xgettext:c-format */ + (_("%B(%A+0x%lx): unresolvable relocation against symbol `%s'"), + input_bfd, + input_section, (long)rel->r_offset, h->root.root.string); + return FALSE; + } + + if (r != bfd_reloc_ok) + { + const char *name; + + if (h != NULL) + name = h->root.root.string; + else + { + name = bfd_elf_string_from_elf_section(input_bfd, + symtab_hdr->sh_link, + sym->st_name); + if (name == NULL) + return FALSE; + if (*name == '\0') + name = bfd_section_name(input_bfd, sec); + } + + if (r == bfd_reloc_overflow) + (*info->callbacks->reloc_overflow) + (info, (h ? &h->root : NULL), name, howto->name, + (bfd_vma)0, input_bfd, input_section, rel->r_offset); + else + { + _bfd_error_handler + /* xgettext:c-format */ + (_("%B(%A+0x%lx): reloc against `%s': error %d"), + input_bfd, input_section, + (long)rel->r_offset, name, (int)r); + return FALSE; + } + } + } + + return TRUE; +} + +static asection * +esp32s2ulp_gc_mark_hook(asection * sec, +struct bfd_link_info *info, + Elf_Internal_Rela * rel, +struct elf_link_hash_entry *h, + Elf_Internal_Sym * sym) +{ + if (h != NULL) + switch (ELF32_R_TYPE(rel->r_info)) + { + case R_ESP32S2ULP_GNU_VTINHERIT: + case R_ESP32S2ULP_GNU_VTENTRY: + return NULL; + } + + return _bfd_elf_gc_mark_hook(sec, info, rel, h, sym); +} + +/* Update the got entry reference counts for the section being removed. */ + +static bfd_boolean +esp32s2ulp_gc_sweep_hook(bfd * abfd, +struct bfd_link_info *info, + asection * sec, + const Elf_Internal_Rela * relocs) +{ + Elf_Internal_Shdr *symtab_hdr; + struct elf_link_hash_entry **sym_hashes; + bfd_signed_vma *local_got_refcounts; + const Elf_Internal_Rela *rel, *relend; + bfd *dynobj; + asection *sgot; + asection *srelgot; + + dynobj = elf_hash_table(info)->dynobj; + if (dynobj == NULL) + return TRUE; + + symtab_hdr = &elf_tdata(abfd)->symtab_hdr; + sym_hashes = elf_sym_hashes(abfd); + local_got_refcounts = elf_local_got_refcounts(abfd); + + sgot = elf_hash_table(info)->sgot; + srelgot = elf_hash_table(info)->srelgot; + + relend = relocs + sec->reloc_count; + for (rel = relocs; rel < relend; rel++) + { + unsigned long r_symndx; + struct elf_link_hash_entry *h; + + switch (ELF32_R_TYPE(rel->r_info)) + { + case R_ESP32S2ULP_GOT: + r_symndx = ELF32_R_SYM(rel->r_info); + if (r_symndx >= symtab_hdr->sh_info) + { + h = sym_hashes[r_symndx - symtab_hdr->sh_info]; + if (h->got.refcount > 0) + { + --h->got.refcount; + if (h->got.refcount == 0) + { + /* We don't need the .got entry any more. */ + sgot->size -= 4; + srelgot->size -= sizeof(Elf32_External_Rela); + } + } + } + else if (local_got_refcounts != NULL) + { + if (local_got_refcounts[r_symndx] > 0) + { + --local_got_refcounts[r_symndx]; + if (local_got_refcounts[r_symndx] == 0) + { + /* We don't need the .got entry any more. */ + sgot->size -= 4; + if (bfd_link_pic(info)) + srelgot->size -= sizeof(Elf32_External_Rela); + } + } + } + break; + default: + break; + } + } + return TRUE; +} + +extern const bfd_target esp32s2ulp_elf32_fdpic_vec; +#define IS_FDPIC(bfd) ((bfd)->xvec == &esp32s2ulp_elf32_fdpic_vec) + +/* An extension of the elf hash table data structure, +containing some additional Blackfin-specific data. */ +struct esp32s2ulpfdpic_elf_link_hash_table +{ + struct elf_link_hash_table elf; + + /* A pointer to the .rofixup section. */ + asection *sgotfixup; + /* GOT base offset. */ + bfd_vma got0; + /* Location of the first non-lazy PLT entry, i.e., the number of + bytes taken by lazy PLT entries. */ + bfd_vma plt0; + /* A hash table holding information about which symbols were + referenced with which PIC-related relocations. */ + struct htab *relocs_info; + /* Summary reloc information collected by + _esp32s2ulpfdpic_count_got_plt_entries. */ + struct _esp32s2ulpfdpic_dynamic_got_info *g; +}; + +/* Get the Blackfin ELF linker hash table from a link_info structure. */ + +#define esp32s2ulpfdpic_hash_table(info) \ + (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \ + == ESP32S2ULP_ELF_DATA ? ((struct esp32s2ulpfdpic_elf_link_hash_table *) ((info)->hash)) : NULL) + +#define esp32s2ulpfdpic_got_section(info) \ + (esp32s2ulpfdpic_hash_table (info)->elf.sgot) +#define esp32s2ulpfdpic_gotrel_section(info) \ + (esp32s2ulpfdpic_hash_table (info)->elf.srelgot) +#define esp32s2ulpfdpic_gotfixup_section(info) \ + (esp32s2ulpfdpic_hash_table (info)->sgotfixup) +#define esp32s2ulpfdpic_plt_section(info) \ + (esp32s2ulpfdpic_hash_table (info)->elf.splt) +#define esp32s2ulpfdpic_pltrel_section(info) \ + (esp32s2ulpfdpic_hash_table (info)->elf.srelplt) +#define esp32s2ulpfdpic_relocs_info(info) \ + (esp32s2ulpfdpic_hash_table (info)->relocs_info) +#define esp32s2ulpfdpic_got_initial_offset(info) \ + (esp32s2ulpfdpic_hash_table (info)->got0) +#define esp32s2ulpfdpic_plt_initial_offset(info) \ + (esp32s2ulpfdpic_hash_table (info)->plt0) +#define esp32s2ulpfdpic_dynamic_got_plt_info(info) \ + (esp32s2ulpfdpic_hash_table (info)->g) + +/* The name of the dynamic interpreter. This is put in the .interp +section. */ + +#define ELF_DYNAMIC_INTERPRETER "/lib/ld.so.1" + +#define DEFAULT_STACK_SIZE 0x20000 + +/* This structure is used to collect the number of entries present in +each addressable range of the got. */ +struct _esp32s2ulpfdpic_dynamic_got_info +{ + /* Several bits of information about the current link. */ + struct bfd_link_info *info; + /* Total size needed for GOT entries within the 18- or 32-bit + ranges. */ + bfd_vma got17m4, gothilo; + /* Total size needed for function descriptor entries within the 18- + or 32-bit ranges. */ + bfd_vma fd17m4, fdhilo; + /* Total size needed function descriptor entries referenced in PLT + entries, that would be profitable to place in offsets close to + the PIC register. */ + bfd_vma fdplt; + /* Total size needed by lazy PLT entries. */ + bfd_vma lzplt; + /* Number of relocations carried over from input object files. */ + unsigned long relocs; + /* Number of fixups introduced by relocations in input object files. */ + unsigned long fixups; +}; + +/* Create a Blackfin ELF linker hash table. */ + +static struct bfd_link_hash_table * +esp32s2ulpfdpic_elf_link_hash_table_create(bfd *abfd) +{ + struct esp32s2ulpfdpic_elf_link_hash_table *ret; + bfd_size_type amt = sizeof(struct esp32s2ulpfdpic_elf_link_hash_table); + + ret = bfd_zmalloc(amt); + if (ret == NULL) + return NULL; + + if (!_bfd_elf_link_hash_table_init(&ret->elf, abfd, + _bfd_elf_link_hash_newfunc, + sizeof(struct elf_link_hash_entry), + ESP32S2ULP_ELF_DATA)) + { + free(ret); + return NULL; + } + + return &ret->elf.root; +} + +/* Decide whether a reference to a symbol can be resolved locally or +not. If the symbol is protected, we want the local address, but +its function descriptor must be assigned by the dynamic linker. */ +#define ESP32S2ULPFDPIC_SYM_LOCAL(INFO, H) \ + (_bfd_elf_symbol_refs_local_p ((H), (INFO), 1) \ + || ! elf_hash_table (INFO)->dynamic_sections_created) +#define ESP32S2ULPFDPIC_FUNCDESC_LOCAL(INFO, H) \ + ((H)->dynindx == -1 || ! elf_hash_table (INFO)->dynamic_sections_created) + +/* This structure collects information on what kind of GOT, PLT or +function descriptors are required by relocations that reference a +certain symbol. */ +struct esp32s2ulpfdpic_relocs_info +{ + /* The index of the symbol, as stored in the relocation r_info, if + we have a local symbol; -1 otherwise. */ + long symndx; + union + { + /* The input bfd in which the symbol is defined, if it's a local + symbol. */ + bfd *abfd; + /* If symndx == -1, the hash table entry corresponding to a global + symbol (even if it turns out to bind locally, in which case it + should ideally be replaced with section's symndx + addend). */ + struct elf_link_hash_entry *h; + } d; + /* The addend of the relocation that references the symbol. */ + bfd_vma addend; + + /* The fields above are used to identify an entry. The fields below + contain information on how an entry is used and, later on, which + locations it was assigned. */ + /* The following 2 fields record whether the symbol+addend above was + ever referenced with a GOT relocation. The 17M4 suffix indicates a + GOT17M4 relocation; hilo is used for GOTLO/GOTHI pairs. */ + unsigned got17m4; + unsigned gothilo; + /* Whether a FUNCDESC relocation references symbol+addend. */ + unsigned fd; + /* Whether a FUNCDESC_GOT relocation references symbol+addend. */ + unsigned fdgot17m4; + unsigned fdgothilo; + /* Whether a FUNCDESC_GOTOFF relocation references symbol+addend. */ + unsigned fdgoff17m4; + unsigned fdgoffhilo; + /* Whether symbol+addend is referenced with GOTOFF17M4, GOTOFFLO or + GOTOFFHI relocations. The addend doesn't really matter, since we + envision that this will only be used to check whether the symbol + is mapped to the same segment as the got. */ + unsigned gotoff; + /* Whether symbol+addend is referenced by a LABEL24 relocation. */ + unsigned call; + /* Whether symbol+addend is referenced by a 32 or FUNCDESC_VALUE + relocation. */ + unsigned sym; + /* Whether we need a PLT entry for a symbol. Should be implied by + something like: + (call && symndx == -1 && ! ESP32S2ULPFDPIC_SYM_LOCAL (info, d.h)) */ + unsigned plt : 1; + /* Whether a function descriptor should be created in this link unit + for symbol+addend. Should be implied by something like: + (plt || fdgotoff17m4 || fdgotofflohi + || ((fd || fdgot17m4 || fdgothilo) + && (symndx != -1 || ESP32S2ULPFDPIC_FUNCDESC_LOCAL (info, d.h)))) */ + unsigned privfd : 1; + /* Whether a lazy PLT entry is needed for this symbol+addend. + Should be implied by something like: + (privfd && symndx == -1 && ! ESP32S2ULPFDPIC_SYM_LOCAL (info, d.h) + && ! (info->flags & DF_BIND_NOW)) */ + unsigned lazyplt : 1; + /* Whether we've already emitted GOT relocations and PLT entries as + needed for this symbol. */ + unsigned done : 1; + + /* The number of R_ESP32S2ULP_BYTE4_DATA, R_ESP32S2ULP_FUNCDESC and R_ESP32S2ULP_FUNCDESC_VALUE + relocations referencing the symbol. */ + unsigned relocs32, relocsfd, relocsfdv; + + /* The number of .rofixups entries and dynamic relocations allocated + for this symbol, minus any that might have already been used. */ + unsigned fixups, dynrelocs; + + /* The offsets of the GOT entries assigned to symbol+addend, to the + function descriptor's address, and to a function descriptor, + respectively. Should be zero if unassigned. The offsets are + counted from the value that will be assigned to the PIC register, + not from the beginning of the .got section. */ + bfd_signed_vma got_entry, fdgot_entry, fd_entry; + /* The offsets of the PLT entries assigned to symbol+addend, + non-lazy and lazy, respectively. If unassigned, should be + (bfd_vma)-1. */ + bfd_vma plt_entry, lzplt_entry; +}; + +/* Compute a hash with the key fields of an esp32s2ulpfdpic_relocs_info entry. */ +static hashval_t +esp32s2ulpfdpic_relocs_info_hash(const void *entry_) +{ + const struct esp32s2ulpfdpic_relocs_info *entry = entry_; + + return (entry->symndx == -1 + ? (long)entry->d.h->root.root.hash + : entry->symndx + (long)entry->d.abfd->id * 257) + entry->addend; +} + +/* Test whether the key fields of two esp32s2ulpfdpic_relocs_info entries are +identical. */ +static int +esp32s2ulpfdpic_relocs_info_eq(const void *entry1, const void *entry2) +{ + const struct esp32s2ulpfdpic_relocs_info *e1 = entry1; + const struct esp32s2ulpfdpic_relocs_info *e2 = entry2; + + return e1->symndx == e2->symndx && e1->addend == e2->addend + && (e1->symndx == -1 ? e1->d.h == e2->d.h : e1->d.abfd == e2->d.abfd); +} + +/* Find or create an entry in a hash table HT that matches the key +fields of the given ENTRY. If it's not found, memory for a new +entry is allocated in ABFD's obstack. */ +static struct esp32s2ulpfdpic_relocs_info * +esp32s2ulpfdpic_relocs_info_find(struct htab *ht, +bfd *abfd, +const struct esp32s2ulpfdpic_relocs_info *entry, +enum insert_option insert) +{ + struct esp32s2ulpfdpic_relocs_info **loc; + + if (!ht) + return NULL; + + loc = (struct esp32s2ulpfdpic_relocs_info **) htab_find_slot(ht, entry, insert); + + if (!loc) + return NULL; + + if (*loc) + return *loc; + + *loc = bfd_zalloc(abfd, sizeof(**loc)); + + if (!*loc) + return *loc; + + (*loc)->symndx = entry->symndx; + (*loc)->d = entry->d; + (*loc)->addend = entry->addend; + (*loc)->plt_entry = (bfd_vma)-1; + (*loc)->lzplt_entry = (bfd_vma)-1; + + return *loc; +} + +/* Obtain the address of the entry in HT associated with H's symbol + +addend, creating a new entry if none existed. ABFD is only used +for memory allocation purposes. */ +inline static struct esp32s2ulpfdpic_relocs_info * +esp32s2ulpfdpic_relocs_info_for_global(struct htab *ht, +bfd *abfd, +struct elf_link_hash_entry *h, + bfd_vma addend, +enum insert_option insert) +{ + struct esp32s2ulpfdpic_relocs_info entry; + + entry.symndx = -1; + entry.d.h = h; + entry.addend = addend; + + return esp32s2ulpfdpic_relocs_info_find(ht, abfd, &entry, insert); +} + +/* Obtain the address of the entry in HT associated with the SYMNDXth +local symbol of the input bfd ABFD, plus the addend, creating a new +entry if none existed. */ +inline static struct esp32s2ulpfdpic_relocs_info * +esp32s2ulpfdpic_relocs_info_for_local(struct htab *ht, +bfd *abfd, +long symndx, +bfd_vma addend, +enum insert_option insert) +{ + struct esp32s2ulpfdpic_relocs_info entry; + + entry.symndx = symndx; + entry.d.abfd = abfd; + entry.addend = addend; + + return esp32s2ulpfdpic_relocs_info_find(ht, abfd, &entry, insert); +} + +/* Merge fields set by check_relocs() of two entries that end up being +mapped to the same (presumably global) symbol. */ + +inline static void +esp32s2ulpfdpic_pic_merge_early_relocs_info(struct esp32s2ulpfdpic_relocs_info *e2, +struct esp32s2ulpfdpic_relocs_info const *e1) +{ + e2->got17m4 |= e1->got17m4; + e2->gothilo |= e1->gothilo; + e2->fd |= e1->fd; + e2->fdgot17m4 |= e1->fdgot17m4; + e2->fdgothilo |= e1->fdgothilo; + e2->fdgoff17m4 |= e1->fdgoff17m4; + e2->fdgoffhilo |= e1->fdgoffhilo; + e2->gotoff |= e1->gotoff; + e2->call |= e1->call; + e2->sym |= e1->sym; +} + +/* Every block of 65535 lazy PLT entries shares a single call to the +resolver, inserted in the 32768th lazy PLT entry (i.e., entry # +32767, counting from 0). All other lazy PLT entries branch to it +in a single instruction. */ + +#define LZPLT_RESOLVER_EXTRA 10 +#define LZPLT_NORMAL_SIZE 6 +#define LZPLT_ENTRIES 1362 + +#define ESP32S2ULPFDPIC_LZPLT_BLOCK_SIZE ((bfd_vma) LZPLT_NORMAL_SIZE * LZPLT_ENTRIES + LZPLT_RESOLVER_EXTRA) +#define ESP32S2ULPFDPIC_LZPLT_RESOLV_LOC (LZPLT_NORMAL_SIZE * LZPLT_ENTRIES / 2) + + +/* Add a fixup to the ROFIXUP section. */ + +static bfd_vma +_esp32s2ulpfdpic_add_rofixup(bfd *output_bfd, asection *rofixup, bfd_vma offset, +struct esp32s2ulpfdpic_relocs_info *entry) +{ + bfd_vma fixup_offset; + + if (rofixup->flags & SEC_EXCLUDE) + return -1; + + fixup_offset = rofixup->reloc_count * 4; + if (rofixup->contents) + { + BFD_ASSERT(fixup_offset < rofixup->size); + bfd_put_32(output_bfd, offset, rofixup->contents + fixup_offset); + } + rofixup->reloc_count++; + + if (entry && entry->symndx) + { + /* If the entry's index is zero, this relocation was probably to a + linkonce section that got discarded. We reserved a dynamic + relocation, but it was for another entry than the one we got at + the time of emitting the relocation. Unfortunately there's no + simple way for us to catch this situation, since the relocation + is cleared right before calling relocate_section, at which point + we no longer know what the relocation used to point to. */ + BFD_ASSERT(entry->fixups > 0); + entry->fixups--; + } + + return fixup_offset; +} + +/* Find the segment number in which OSEC, and output section, is +located. */ + +static unsigned +_esp32s2ulpfdpic_osec_to_segment(bfd *output_bfd, asection *osec) +{ + Elf_Internal_Phdr *p = _bfd_elf_find_segment_containing_section(output_bfd, osec); + + return (p != NULL) ? p - elf_tdata(output_bfd)->phdr : -1; +} + +/* Relocate an Blackfin ELF section. + +The RELOCATE_SECTION function is called by the new ELF backend linker +to handle the relocations for a section. + +The relocs are always passed as Rela structures; if the section +actually uses Rel structures, the r_addend field will always be +zero. + +This function is responsible for adjusting the section contents as +necessary, and (if using Rela relocs and generating a relocatable +output file) adjusting the reloc addend as necessary. + +This function does not have to worry about setting the reloc +address or the reloc symbol index. + +LOCAL_SYMS is a pointer to the swapped in local symbols. + +LOCAL_SECTIONS is an array giving the section in the input file +corresponding to the st_shndx field of each local symbol. + +The global hash table entry for the global symbols can be found +via elf_sym_hashes (input_bfd). + +When generating relocatable output, this function must handle +STB_LOCAL/STT_SECTION symbols specially. The output symbol is +going to be the section symbol corresponding to the output +section, which means that the addend must be adjusted +accordingly. */ + +static bfd_boolean +esp32s2ulpfdpic_relocate_section(bfd * output_bfd, +struct bfd_link_info *info, + bfd * input_bfd, + asection * input_section, + bfd_byte * contents, + Elf_Internal_Rela * relocs, + Elf_Internal_Sym * local_syms, + asection ** local_sections) +{ + (void)local_sections; // dya - remove warning + Elf_Internal_Shdr *symtab_hdr; + struct elf_link_hash_entry **sym_hashes; + Elf_Internal_Rela *rel; + Elf_Internal_Rela *relend; + unsigned isec_segment, + check_segment[2]; + int silence_segment_error = !bfd_link_pic(info); + + symtab_hdr = &elf_tdata(input_bfd)->symtab_hdr; + sym_hashes = elf_sym_hashes(input_bfd); + relend = relocs + input_section->reloc_count; + + isec_segment = _esp32s2ulpfdpic_osec_to_segment(output_bfd, + input_section->output_section); + + for (rel = relocs; rel < relend; rel++) + { + reloc_howto_type *howto; + unsigned long r_symndx; + Elf_Internal_Sym *sym; + asection *sec; + struct elf_link_hash_entry *h; + bfd_vma relocation; + bfd_reloc_status_type r; + const char * name = NULL; + int r_type; + struct esp32s2ulpfdpic_relocs_info *picrel; + + r_type = ELF32_R_TYPE(rel->r_info); + + if (r_type == R_ESP32S2ULP_GNU_VTINHERIT + || r_type == R_ESP32S2ULP_GNU_VTENTRY) + continue; + + r_symndx = ELF32_R_SYM(rel->r_info); + howto = esp32s2ulp_reloc_type_lookup(input_bfd, r_type); + if (howto == NULL) + { + bfd_set_error(bfd_error_bad_value); + return FALSE; + } + + h = NULL; + sym = NULL; + sec = NULL; + unsigned int section_flags = 0; + if (r_symndx < symtab_hdr->sh_info) + { + sym = local_syms + r_symndx; + relocation = _bfd_elf_rela_local_sym(output_bfd, sym, &sec, rel); + section_flags = 0; + name = bfd_elf_string_from_elf_section + (input_bfd, symtab_hdr->sh_link, sym->st_name); + name = (name == NULL) ? bfd_section_name(input_bfd, sec) : name; + } + else + { + bfd_boolean warned, ignored; + bfd_boolean unresolved_reloc; + + ESP32S2ULP_RELOC_FOR_GLOBAL_SYMBOL(info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, + unresolved_reloc, warned, ignored, section_flags); + } + + if (sec != NULL && discarded_section(sec)) + RELOC_AGAINST_DISCARDED_SECTION(info, input_bfd, input_section, + rel, 1, relend, howto, 0, contents); + + if (bfd_link_relocatable(info)) + continue; + + if (h != NULL + && (h->root.type == bfd_link_hash_defined + || h->root.type == bfd_link_hash_defweak) + && !ESP32S2ULPFDPIC_SYM_LOCAL(info, h)) + { + relocation = 0; + } + (void)section_flags; + switch (r_type) + { + + default: + picrel = NULL; + if (h && !ESP32S2ULPFDPIC_SYM_LOCAL(info, h) + && _bfd_elf_section_offset(output_bfd, info, input_section, + rel->r_offset) != (bfd_vma)-1) + { + info->callbacks->warning + (info, _("relocation references symbol not defined in the module"), + name, input_bfd, input_section, rel->r_offset); + return FALSE; + } + break; + } + + switch (r_type) + { + default: + check_segment[0] = isec_segment; + check_segment[1] = sec + ? _esp32s2ulpfdpic_osec_to_segment(output_bfd, sec->output_section) + : (unsigned)-1; + break; + } + + if (check_segment[0] != check_segment[1] && IS_FDPIC(output_bfd)) + { +#if 1 /* If you take this out, remove the #error from fdpic-static-6.d + in the ld testsuite. */ + /* This helps catch problems in GCC while we can't do more + than static linking. The idea is to test whether the + input file basename is crt0.o only once. */ + if (silence_segment_error == 1) + silence_segment_error = + (strlen(input_bfd->filename) == 6 + && filename_cmp(input_bfd->filename, "crt0.o") == 0) + || (strlen(input_bfd->filename) > 6 + && filename_cmp(input_bfd->filename + + strlen(input_bfd->filename) - 7, + "/crt0.o") == 0) + ? -1 : 0; +#endif + if (!silence_segment_error + /* We don't want duplicate errors for undefined + symbols. */ + && !(picrel && picrel->symndx == -1 + && picrel->d.h->root.type == bfd_link_hash_undefined)) + info->callbacks->warning + (info, + bfd_link_pic(info) + ? _("relocations between different segments are not supported") + : _("warning: relocation references a different segment"), + name, input_bfd, input_section, rel->r_offset); + if (!silence_segment_error && bfd_link_pic(info)) + return FALSE; + elf_elfheader(output_bfd)->e_flags |= EF_ESP32S2ULP_PIC; + } + + r = esp32s2ulp_final_link_relocate(rel, howto, input_bfd, input_section, + contents, rel->r_offset, + relocation, rel->r_addend); + + if (r != bfd_reloc_ok) + { + const char * msg = (const char *)NULL; + + switch (r) + { + case bfd_reloc_overflow: + (*info->callbacks->reloc_overflow) + (info, (h ? &h->root : NULL), name, howto->name, + (bfd_vma)0, input_bfd, input_section, rel->r_offset); + break; + + case bfd_reloc_undefined: + (*info->callbacks->undefined_symbol) + (info, name, input_bfd, input_section, rel->r_offset, TRUE); + break; + + case bfd_reloc_outofrange: + msg = _("internal error: out of range error"); + break; + + case bfd_reloc_notsupported: + msg = _("internal error: unsupported relocation error"); + break; + + case bfd_reloc_dangerous: + msg = _("internal error: dangerous relocation"); + break; + + default: + msg = _("internal error: unknown error"); + break; + } + + if (msg) + (*info->callbacks->warning) (info, msg, name, input_bfd, + input_section, rel->r_offset); + } + } + + return TRUE; +} + +/* Update the relocation information for the relocations of the section +being removed. */ + +static bfd_boolean +esp32s2ulpfdpic_gc_sweep_hook(bfd *abfd, +struct bfd_link_info *info, + asection *sec, + const Elf_Internal_Rela *relocs) +{ + Elf_Internal_Shdr *symtab_hdr; + struct elf_link_hash_entry **sym_hashes, **sym_hashes_end; + const Elf_Internal_Rela *rel; + const Elf_Internal_Rela *rel_end; + struct esp32s2ulpfdpic_relocs_info *picrel; + + BFD_ASSERT(IS_FDPIC(abfd)); + + symtab_hdr = &elf_tdata(abfd)->symtab_hdr; + sym_hashes = elf_sym_hashes(abfd); + sym_hashes_end = sym_hashes + symtab_hdr->sh_size / sizeof(Elf32_External_Sym); + if (!elf_bad_symtab(abfd)) + sym_hashes_end -= symtab_hdr->sh_info; + + rel_end = relocs + sec->reloc_count; + for (rel = relocs; rel < rel_end; rel++) + { + struct elf_link_hash_entry *h; + unsigned long r_symndx; + + r_symndx = ELF32_R_SYM(rel->r_info); + if (r_symndx < symtab_hdr->sh_info) + h = NULL; + else + h = sym_hashes[r_symndx - symtab_hdr->sh_info]; + + if (h != NULL) + picrel = esp32s2ulpfdpic_relocs_info_for_global(esp32s2ulpfdpic_relocs_info(info), + abfd, h, + rel->r_addend, NO_INSERT); + else + picrel = esp32s2ulpfdpic_relocs_info_for_local(esp32s2ulpfdpic_relocs_info + (info), abfd, r_symndx, + rel->r_addend, NO_INSERT); + + if (!picrel) + return TRUE; + } + + return TRUE; +} + +/* We need dynamic symbols for every section, since segments can +relocate independently. */ +static bfd_boolean +_esp32s2ulpfdpic_link_omit_section_dynsym(bfd *output_bfd ATTRIBUTE_UNUSED, +struct bfd_link_info *info ATTRIBUTE_UNUSED, + asection *p) +{ + switch (elf_section_data(p)->this_hdr.sh_type) + { + case SHT_PROGBITS: + case SHT_NOBITS: + /* If sh_type is yet undecided, assume it could be + SHT_PROGBITS/SHT_NOBITS. */ + case SHT_NULL: + return FALSE; + + /* There shouldn't be section relative relocations + against any other section. */ + default: + return TRUE; + } +} + +/* Create a .got section, as well as its additional info field. This +is almost entirely copied from +elflink.c:_bfd_elf_create_got_section(). */ + +static bfd_boolean +_esp32s2ulp_create_got_section(bfd *abfd, struct bfd_link_info *info) +{ + flagword flags, pltflags; + asection *s; + struct elf_link_hash_entry *h; + const struct elf_backend_data *bed = get_elf_backend_data(abfd); + int ptralign; + + /* This function may be called more than once. */ + s = elf_hash_table(info)->sgot; + if (s != NULL) + return TRUE; + + /* Machine specific: although pointers are 32-bits wide, we want the + GOT to be aligned to a 64-bit boundary, such that function + descriptors in it can be accessed with 64-bit loads and + stores. */ + ptralign = 3; + + flags = (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY + | SEC_LINKER_CREATED); + pltflags = flags; + + s = bfd_make_section_anyway_with_flags(abfd, ".got", flags); + elf_hash_table(info)->sgot = s; + if (s == NULL + || !bfd_set_section_alignment(abfd, s, ptralign)) + return FALSE; + + if (bed->want_got_sym) + { + /* Define the symbol _GLOBAL_OFFSET_TABLE_ at the start of the .got + (or .got.plt) section. We don't do this in the linker script + because we don't want to define the symbol if we are not creating + a global offset table. */ + h = _bfd_elf_define_linkage_sym(abfd, info, s, "__GLOBAL_OFFSET_TABLE_"); + elf_hash_table(info)->hgot = h; + if (h == NULL) + return FALSE; + + /* Machine-specific: we want the symbol for executables as + well. */ + if (!bfd_elf_link_record_dynamic_symbol(info, h)) + return FALSE; + } + + /* The first bit of the global offset table is the header. */ + s->size += bed->got_header_size; + + /* This is the machine-specific part. Create and initialize section + data for the got. */ + if (IS_FDPIC(abfd)) + { + esp32s2ulpfdpic_relocs_info(info) = htab_try_create(1, + esp32s2ulpfdpic_relocs_info_hash, + esp32s2ulpfdpic_relocs_info_eq, + (htab_del)NULL); + if (!esp32s2ulpfdpic_relocs_info(info)) + return FALSE; + + s = bfd_make_section_anyway_with_flags(abfd, ".rel.got", + (flags | SEC_READONLY)); + if (s == NULL + || !bfd_set_section_alignment(abfd, s, 2)) + return FALSE; + + esp32s2ulpfdpic_gotrel_section(info) = s; + + /* Machine-specific. */ + s = bfd_make_section_anyway_with_flags(abfd, ".rofixup", + (flags | SEC_READONLY)); + if (s == NULL + || !bfd_set_section_alignment(abfd, s, 2)) + return FALSE; + + esp32s2ulpfdpic_gotfixup_section(info) = s; + } + + pltflags |= SEC_CODE; + if (bed->plt_not_loaded) + pltflags &= ~(SEC_CODE | SEC_LOAD | SEC_HAS_CONTENTS); + if (bed->plt_readonly) + pltflags |= SEC_READONLY; + + s = bfd_make_section_anyway_with_flags(abfd, ".plt", pltflags); + if (s == NULL + || !bfd_set_section_alignment(abfd, s, bed->plt_alignment)) + return FALSE; + /* Blackfin-specific: remember it. */ + esp32s2ulpfdpic_plt_section(info) = s; + + if (bed->want_plt_sym) + { + /* Define the symbol _PROCEDURE_LINKAGE_TABLE_ at the start of the + .plt section. */ + struct bfd_link_hash_entry *bh = NULL; + + if (!(_bfd_generic_link_add_one_symbol + (info, abfd, "__PROCEDURE_LINKAGE_TABLE_", BSF_GLOBAL, s, 0, NULL, + FALSE, get_elf_backend_data(abfd)->collect, &bh))) + return FALSE; + h = (struct elf_link_hash_entry *) bh; + h->def_regular = 1; + h->type = STT_OBJECT; + + if (!bfd_link_executable(info) + && !bfd_elf_link_record_dynamic_symbol(info, h)) + return FALSE; + } + + /* Blackfin-specific: we want rel relocations for the plt. */ + s = bfd_make_section_anyway_with_flags(abfd, ".rel.plt", + flags | SEC_READONLY); + if (s == NULL + || !bfd_set_section_alignment(abfd, s, bed->s->log_file_align)) + return FALSE; + /* Blackfin-specific: remember it. */ + esp32s2ulpfdpic_pltrel_section(info) = s; + + return TRUE; +} + +/* Make sure the got and plt sections exist, and that our pointers in +the link hash table point to them. */ + +static bfd_boolean +elf32_esp32s2ulpfdpic_create_dynamic_sections(bfd *abfd, struct bfd_link_info *info) +{ + /* This is mostly copied from + elflink.c:_bfd_elf_create_dynamic_sections(). */ + flagword flags; + asection *s; + const struct elf_backend_data *bed = get_elf_backend_data(abfd); + + flags = (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY + | SEC_LINKER_CREATED); + + /* We need to create .plt, .rel[a].plt, .got, .got.plt, .dynbss, and + .rel[a].bss sections. */ + + /* Blackfin-specific: we want to create the GOT in the Blackfin way. */ + if (!_esp32s2ulp_create_got_section(abfd, info)) + return FALSE; + + /* Blackfin-specific: make sure we created everything we wanted. */ + BFD_ASSERT(esp32s2ulpfdpic_got_section(info) && esp32s2ulpfdpic_gotrel_section(info) + /* && esp32s2ulpfdpic_gotfixup_section (info) */ + && esp32s2ulpfdpic_plt_section(info) + && esp32s2ulpfdpic_pltrel_section(info)); + + if (bed->want_dynbss) + { + /* The .dynbss section is a place to put symbols which are defined + by dynamic objects, are referenced by regular objects, and are + not functions. We must allocate space for them in the process + image and use a R_*_COPY reloc to tell the dynamic linker to + initialize them at run time. The linker script puts the .dynbss + section into the .bss section of the final image. */ + s = bfd_make_section_anyway_with_flags(abfd, ".dynbss", + SEC_ALLOC | SEC_LINKER_CREATED); + if (s == NULL) + return FALSE; + + /* The .rel[a].bss section holds copy relocs. This section is not + normally needed. We need to create it here, though, so that the + linker will map it to an output section. We can't just create it + only if we need it, because we will not know whether we need it + until we have seen all the input files, and the first time the + main linker code calls BFD after examining all the input files + (size_dynamic_sections) the input sections have already been + mapped to the output sections. If the section turns out not to + be needed, we can discard it later. We will never need this + section when generating a shared object, since they do not use + copy relocs. */ + if (!bfd_link_pic(info)) + { + s = bfd_make_section_anyway_with_flags(abfd, + ".rela.bss", + flags | SEC_READONLY); + if (s == NULL + || !bfd_set_section_alignment(abfd, s, bed->s->log_file_align)) + return FALSE; + } + } + + return TRUE; +} + +/* Compute the total GOT size required by each symbol in each range. +Symbols may require up to 4 words in the GOT: an entry pointing to +the symbol, an entry pointing to its function descriptor, and a +private function descriptors taking two words. */ + +static void +_esp32s2ulpfdpic_count_nontls_entries(struct esp32s2ulpfdpic_relocs_info *entry, +struct _esp32s2ulpfdpic_dynamic_got_info *dinfo) +{ + /* Allocate space for a GOT entry pointing to the symbol. */ + if (entry->got17m4) + dinfo->got17m4 += 4; + else if (entry->gothilo) + dinfo->gothilo += 4; + else + entry->relocs32--; + entry->relocs32++; + + /* Allocate space for a GOT entry pointing to the function + descriptor. */ + if (entry->fdgot17m4) + dinfo->got17m4 += 4; + else if (entry->fdgothilo) + dinfo->gothilo += 4; + else + entry->relocsfd--; + entry->relocsfd++; + + /* Decide whether we need a PLT entry, a function descriptor in the + GOT, and a lazy PLT entry for this symbol. */ + entry->plt = entry->call + && entry->symndx == -1 && !ESP32S2ULPFDPIC_SYM_LOCAL(dinfo->info, entry->d.h) + && elf_hash_table(dinfo->info)->dynamic_sections_created; + entry->privfd = entry->plt + || entry->fdgoff17m4 || entry->fdgoffhilo + || ((entry->fd || entry->fdgot17m4 || entry->fdgothilo) + && (entry->symndx != -1 + || ESP32S2ULPFDPIC_FUNCDESC_LOCAL(dinfo->info, entry->d.h))); + entry->lazyplt = entry->privfd + && entry->symndx == -1 && !ESP32S2ULPFDPIC_SYM_LOCAL(dinfo->info, entry->d.h) + && !(dinfo->info->flags & DF_BIND_NOW) + && elf_hash_table(dinfo->info)->dynamic_sections_created; + + /* Allocate space for a function descriptor. */ + if (entry->fdgoff17m4) + dinfo->fd17m4 += 8; + else if (entry->privfd && entry->plt) + dinfo->fdplt += 8; + else if (entry->privfd) + dinfo->fdhilo += 8; + else + entry->relocsfdv--; + entry->relocsfdv++; + + if (entry->lazyplt) + dinfo->lzplt += LZPLT_NORMAL_SIZE; +} + +/* Compute the number of dynamic relocations and fixups that a symbol +requires, and add (or subtract) from the grand and per-symbol +totals. */ + +static void +_esp32s2ulpfdpic_count_relocs_fixups(struct esp32s2ulpfdpic_relocs_info *entry, +struct _esp32s2ulpfdpic_dynamic_got_info *dinfo, + bfd_boolean subtract) +{ + bfd_vma relocs = 0, fixups = 0; + + if (!bfd_link_pde(dinfo->info)) + relocs = entry->relocs32 + entry->relocsfd + entry->relocsfdv; + else + { + if (entry->symndx != -1 || ESP32S2ULPFDPIC_SYM_LOCAL(dinfo->info, entry->d.h)) + { + if (entry->symndx != -1 + || entry->d.h->root.type != bfd_link_hash_undefweak) + fixups += entry->relocs32 + 2 * entry->relocsfdv; + } + else + relocs += entry->relocs32 + entry->relocsfdv; + + if (entry->symndx != -1 + || ESP32S2ULPFDPIC_FUNCDESC_LOCAL(dinfo->info, entry->d.h)) + { + if (entry->symndx != -1 + || entry->d.h->root.type != bfd_link_hash_undefweak) + fixups += entry->relocsfd; + } + else + relocs += entry->relocsfd; + } + + if (subtract) + { + relocs = -relocs; + fixups = -fixups; + } + + entry->dynrelocs += relocs; + entry->fixups += fixups; + dinfo->relocs += relocs; + dinfo->fixups += fixups; +} + +/* Compute the total GOT and PLT size required by each symbol in each range. * +Symbols may require up to 4 words in the GOT: an entry pointing to +the symbol, an entry pointing to its function descriptor, and a +private function descriptors taking two words. */ + +static int +_esp32s2ulpfdpic_count_got_plt_entries(void **entryp, void *dinfo_) +{ + struct esp32s2ulpfdpic_relocs_info *entry = *entryp; + struct _esp32s2ulpfdpic_dynamic_got_info *dinfo = dinfo_; + + _esp32s2ulpfdpic_count_nontls_entries(entry, dinfo); + + _esp32s2ulpfdpic_count_relocs_fixups(entry, dinfo, FALSE); + + return 1; +} + +/* This structure is used to assign offsets to got entries, function +descriptors, plt entries and lazy plt entries. */ + +struct _esp32s2ulpfdpic_dynamic_got_plt_info +{ + /* Summary information collected with _esp32s2ulpfdpic_count_got_plt_entries. */ + struct _esp32s2ulpfdpic_dynamic_got_info g; + + /* For each addressable range, we record a MAX (positive) and MIN + (negative) value. CUR is used to assign got entries, and it's + incremented from an initial positive value to MAX, then from MIN + to FDCUR (unless FDCUR wraps around first). FDCUR is used to + assign function descriptors, and it's decreased from an initial + non-positive value to MIN, then from MAX down to CUR (unless CUR + wraps around first). All of MIN, MAX, CUR and FDCUR always point + to even words. ODD, if non-zero, indicates an odd word to be + used for the next got entry, otherwise CUR is used and + incremented by a pair of words, wrapping around when it reaches + MAX. FDCUR is decremented (and wrapped) before the next function + descriptor is chosen. FDPLT indicates the number of remaining + slots that can be used for function descriptors used only by PLT + entries. */ + struct _esp32s2ulpfdpic_dynamic_got_alloc_data + { + bfd_signed_vma max, cur, odd, fdcur, min; + bfd_vma fdplt; + } got17m4, gothilo; +}; + +/* Determine the positive and negative ranges to be used by each +offset range in the GOT. FDCUR and CUR, that must be aligned to a +double-word boundary, are the minimum (negative) and maximum +(positive) GOT offsets already used by previous ranges, except for +an ODD entry that may have been left behind. GOT and FD indicate +the size of GOT entries and function descriptors that must be +placed within the range from -WRAP to WRAP. If there's room left, +up to FDPLT bytes should be reserved for additional function +descriptors. */ + +inline static bfd_signed_vma +_esp32s2ulpfdpic_compute_got_alloc_data(struct _esp32s2ulpfdpic_dynamic_got_alloc_data *gad, +bfd_signed_vma fdcur, +bfd_signed_vma odd, +bfd_signed_vma cur, +bfd_vma got, +bfd_vma fd, +bfd_vma fdplt, +bfd_vma wrap) +{ + bfd_signed_vma wrapmin = -wrap; + + /* Start at the given initial points. */ + gad->fdcur = fdcur; + gad->cur = cur; + + /* If we had an incoming odd word and we have any got entries that + are going to use it, consume it, otherwise leave gad->odd at + zero. We might force gad->odd to zero and return the incoming + odd such that it is used by the next range, but then GOT entries + might appear to be out of order and we wouldn't be able to + shorten the GOT by one word if it turns out to end with an + unpaired GOT entry. */ + if (odd && got) + { + gad->odd = odd; + got -= 4; + odd = 0; + } + else + gad->odd = 0; + + /* If we're left with an unpaired GOT entry, compute its location + such that we can return it. Otherwise, if got doesn't require an + odd number of words here, either odd was already zero in the + block above, or it was set to zero because got was non-zero, or + got was already zero. In the latter case, we want the value of + odd to carry over to the return statement, so we don't want to + reset odd unless the condition below is true. */ + if (got & 4) + { + odd = cur + got; + got += 4; + } + + /* Compute the tentative boundaries of this range. */ + gad->max = cur + got; + gad->min = fdcur - fd; + gad->fdplt = 0; + + /* If function descriptors took too much space, wrap some of them + around. */ + if (gad->min < wrapmin) + { + gad->max += wrapmin - gad->min; + gad->min = wrapmin; + } + /* If there is space left and we have function descriptors + referenced in PLT entries that could take advantage of shorter + offsets, place them here. */ + else if (fdplt && gad->min > wrapmin) + { + bfd_vma fds; + if ((bfd_vma)(gad->min - wrapmin) < fdplt) + fds = gad->min - wrapmin; + else + fds = fdplt; + + fdplt -= fds; + gad->min -= fds; + gad->fdplt += fds; + } + + /* If GOT entries took too much space, wrap some of them around. + This may well cause gad->min to become lower than wrapmin. This + will cause a relocation overflow later on, so we don't have to + report it here . */ + if ((bfd_vma)gad->max > wrap) + { + gad->min -= gad->max - wrap; + gad->max = wrap; + } + /* If there is more space left, try to place some more function + descriptors for PLT entries. */ + else if (fdplt && (bfd_vma)gad->max < wrap) + { + bfd_vma fds; + if ((bfd_vma)(wrap - gad->max) < fdplt) + fds = wrap - gad->max; + else + fds = fdplt; + + fdplt -= fds; + gad->max += fds; + gad->fdplt += fds; + } + + /* If odd was initially computed as an offset past the wrap point, + wrap it around. */ + if (odd > gad->max) + odd = gad->min + odd - gad->max; + + /* _esp32s2ulpfdpic_get_got_entry() below will always wrap gad->cur if needed + before returning, so do it here too. This guarantees that, + should cur and fdcur meet at the wrap point, they'll both be + equal to min. */ + if (gad->cur == gad->max) + gad->cur = gad->min; + + return odd; +} + +/* Compute the location of the next GOT entry, given the allocation +data for a range. */ + +inline static bfd_signed_vma +_esp32s2ulpfdpic_get_got_entry(struct _esp32s2ulpfdpic_dynamic_got_alloc_data *gad) +{ + bfd_signed_vma ret; + + if (gad->odd) + { + /* If there was an odd word left behind, use it. */ + ret = gad->odd; + gad->odd = 0; + } + else + { + /* Otherwise, use the word pointed to by cur, reserve the next + as an odd word, and skip to the next pair of words, possibly + wrapping around. */ + ret = gad->cur; + gad->odd = gad->cur + 4; + gad->cur += 8; + if (gad->cur == gad->max) + gad->cur = gad->min; + } + + return ret; +} + +/* Compute the location of the next function descriptor entry in the +GOT, given the allocation data for a range. */ + +inline static bfd_signed_vma +_esp32s2ulpfdpic_get_fd_entry(struct _esp32s2ulpfdpic_dynamic_got_alloc_data *gad) +{ + /* If we're at the bottom, wrap around, and only then allocate the + next pair of words. */ + if (gad->fdcur == gad->min) + gad->fdcur = gad->max; + return gad->fdcur -= 8; +} + +/* Assign GOT offsets for every GOT entry and function descriptor. +Doing everything in a single pass is tricky. */ + +static int +_esp32s2ulpfdpic_assign_got_entries(void **entryp, void *info_) +{ + struct esp32s2ulpfdpic_relocs_info *entry = *entryp; + struct _esp32s2ulpfdpic_dynamic_got_plt_info *dinfo = info_; + + if (entry->got17m4) + entry->got_entry = _esp32s2ulpfdpic_get_got_entry(&dinfo->got17m4); + else if (entry->gothilo) + entry->got_entry = _esp32s2ulpfdpic_get_got_entry(&dinfo->gothilo); + + if (entry->fdgot17m4) + entry->fdgot_entry = _esp32s2ulpfdpic_get_got_entry(&dinfo->got17m4); + else if (entry->fdgothilo) + entry->fdgot_entry = _esp32s2ulpfdpic_get_got_entry(&dinfo->gothilo); + + if (entry->fdgoff17m4) + entry->fd_entry = _esp32s2ulpfdpic_get_fd_entry(&dinfo->got17m4); + else if (entry->plt && dinfo->got17m4.fdplt) + { + dinfo->got17m4.fdplt -= 8; + entry->fd_entry = _esp32s2ulpfdpic_get_fd_entry(&dinfo->got17m4); + } + else if (entry->plt) + { + dinfo->gothilo.fdplt -= 8; + entry->fd_entry = _esp32s2ulpfdpic_get_fd_entry(&dinfo->gothilo); + } + else if (entry->privfd) + entry->fd_entry = _esp32s2ulpfdpic_get_fd_entry(&dinfo->gothilo); + + return 1; +} + +/* Assign GOT offsets to private function descriptors used by PLT +entries (or referenced by 32-bit offsets), as well as PLT entries +and lazy PLT entries. */ + +static int +_esp32s2ulpfdpic_assign_plt_entries(void **entryp, void *info_) +{ + struct esp32s2ulpfdpic_relocs_info *entry = *entryp; + struct _esp32s2ulpfdpic_dynamic_got_plt_info *dinfo = info_; + + /* If this symbol requires a local function descriptor, allocate + one. */ + if (entry->privfd && entry->fd_entry == 0) + { + if (dinfo->got17m4.fdplt) + { + entry->fd_entry = _esp32s2ulpfdpic_get_fd_entry(&dinfo->got17m4); + dinfo->got17m4.fdplt -= 8; + } + else + { + BFD_ASSERT(dinfo->gothilo.fdplt); + entry->fd_entry = _esp32s2ulpfdpic_get_fd_entry(&dinfo->gothilo); + dinfo->gothilo.fdplt -= 8; + } + } + + if (entry->plt) + { + int size; + + /* We use the section's raw size to mark the location of the + next PLT entry. */ + entry->plt_entry = esp32s2ulpfdpic_plt_section(dinfo->g.info)->size; + + /* Figure out the length of this PLT entry based on the + addressing mode we need to reach the function descriptor. */ + BFD_ASSERT(entry->fd_entry); + if (entry->fd_entry >= -(1 << (18 - 1)) + && entry->fd_entry + 4 < (1 << (18 - 1))) + size = 10; + else + size = 16; + + esp32s2ulpfdpic_plt_section(dinfo->g.info)->size += size; + } + + if (entry->lazyplt) + { + entry->lzplt_entry = dinfo->g.lzplt; + dinfo->g.lzplt += LZPLT_NORMAL_SIZE; + /* If this entry is the one that gets the resolver stub, account + for the additional instruction. */ + if (entry->lzplt_entry % ESP32S2ULPFDPIC_LZPLT_BLOCK_SIZE + == ESP32S2ULPFDPIC_LZPLT_RESOLV_LOC) + dinfo->g.lzplt += LZPLT_RESOLVER_EXTRA; + } + + return 1; +} + +/* Cancel out any effects of calling _esp32s2ulpfdpic_assign_got_entries and +_esp32s2ulpfdpic_assign_plt_entries. */ + +static int +_esp32s2ulpfdpic_reset_got_plt_entries(void **entryp, void *ignore ATTRIBUTE_UNUSED) +{ + struct esp32s2ulpfdpic_relocs_info *entry = *entryp; + + entry->got_entry = 0; + entry->fdgot_entry = 0; + entry->fd_entry = 0; + entry->plt_entry = (bfd_vma)-1; + entry->lzplt_entry = (bfd_vma)-1; + + return 1; +} + +/* Follow indirect and warning hash entries so that each got entry +points to the final symbol definition. P must point to a pointer +to the hash table we're traversing. Since this traversal may +modify the hash table, we set this pointer to NULL to indicate +we've made a potentially-destructive change to the hash table, so +the traversal must be restarted. */ +static int +_esp32s2ulpfdpic_resolve_final_relocs_info(void **entryp, void *p) +{ + struct esp32s2ulpfdpic_relocs_info *entry = *entryp; + htab_t *htab = p; + + if (entry->symndx == -1) + { + struct elf_link_hash_entry *h = entry->d.h; + struct esp32s2ulpfdpic_relocs_info *oentry; + + while (h->root.type == bfd_link_hash_indirect + || h->root.type == bfd_link_hash_warning) + h = (struct elf_link_hash_entry *)h->root.u.i.link; + + if (entry->d.h == h) + return 1; + + oentry = esp32s2ulpfdpic_relocs_info_for_global(*htab, 0, h, entry->addend, + NO_INSERT); + + if (oentry) + { + /* Merge the two entries. */ + esp32s2ulpfdpic_pic_merge_early_relocs_info(oentry, entry); + htab_clear_slot(*htab, entryp); + return 1; + } + + entry->d.h = h; + + /* If we can't find this entry with the new bfd hash, re-insert + it, and get the traversal restarted. */ + if (!htab_find(*htab, entry)) + { + htab_clear_slot(*htab, entryp); + entryp = htab_find_slot(*htab, entry, INSERT); + if (!*entryp) + *entryp = entry; + /* Abort the traversal, since the whole table may have + moved, and leave it up to the parent to restart the + process. */ + *(htab_t *)p = NULL; + return 0; + } + } + + return 1; +} + +/* Compute the total size of the GOT, the PLT, the dynamic relocations +section and the rofixup section. Assign locations for GOT and PLT +entries. */ + +static bfd_boolean +_esp32s2ulpfdpic_size_got_plt(bfd *output_bfd, +struct _esp32s2ulpfdpic_dynamic_got_plt_info *gpinfop) +{ + bfd_signed_vma odd; + bfd_vma limit; + struct bfd_link_info *info = gpinfop->g.info; + bfd *dynobj = elf_hash_table(info)->dynobj; + + memcpy(esp32s2ulpfdpic_dynamic_got_plt_info(info), &gpinfop->g, + sizeof(gpinfop->g)); + + odd = 12; + /* Compute the total size taken by entries in the 18-bit range, + to tell how many PLT function descriptors we can bring into it + without causing it to overflow. */ + limit = odd + gpinfop->g.got17m4 + gpinfop->g.fd17m4; + if (limit < (bfd_vma)1 << 18) + limit = ((bfd_vma)1 << 18) - limit; + else + limit = 0; + if (gpinfop->g.fdplt < limit) + limit = gpinfop->g.fdplt; + + /* Determine the ranges of GOT offsets that we can use for each + range of addressing modes. */ + odd = _esp32s2ulpfdpic_compute_got_alloc_data(&gpinfop->got17m4, + 0, + odd, + 16, + gpinfop->g.got17m4, + gpinfop->g.fd17m4, + limit, + (bfd_vma)1 << (18 - 1)); + odd = _esp32s2ulpfdpic_compute_got_alloc_data(&gpinfop->gothilo, + gpinfop->got17m4.min, + odd, + gpinfop->got17m4.max, + gpinfop->g.gothilo, + gpinfop->g.fdhilo, + gpinfop->g.fdplt - gpinfop->got17m4.fdplt, + (bfd_vma)1 << (32 - 1)); + + /* Now assign (most) GOT offsets. */ + htab_traverse(esp32s2ulpfdpic_relocs_info(info), _esp32s2ulpfdpic_assign_got_entries, + gpinfop); + + esp32s2ulpfdpic_got_section(info)->size = gpinfop->gothilo.max + - gpinfop->gothilo.min + /* If an odd word is the last word of the GOT, we don't need this + word to be part of the GOT. */ + - (odd + 4 == gpinfop->gothilo.max ? 4 : 0); + if (esp32s2ulpfdpic_got_section(info)->size == 0) + esp32s2ulpfdpic_got_section(info)->flags |= SEC_EXCLUDE; + else if (esp32s2ulpfdpic_got_section(info)->size == 12 + && !elf_hash_table(info)->dynamic_sections_created) + { + esp32s2ulpfdpic_got_section(info)->flags |= SEC_EXCLUDE; + esp32s2ulpfdpic_got_section(info)->size = 0; + } + else + { + esp32s2ulpfdpic_got_section(info)->contents = + (bfd_byte *)bfd_zalloc(dynobj, + esp32s2ulpfdpic_got_section(info)->size); + if (esp32s2ulpfdpic_got_section(info)->contents == NULL) + return FALSE; + } + + if (elf_hash_table(info)->dynamic_sections_created) + /* Subtract the number of lzplt entries, since those will generate + relocations in the pltrel section. */ + esp32s2ulpfdpic_gotrel_section(info)->size = + (gpinfop->g.relocs - gpinfop->g.lzplt / LZPLT_NORMAL_SIZE) + * get_elf_backend_data(output_bfd)->s->sizeof_rel; + else + BFD_ASSERT(gpinfop->g.relocs == 0); + if (esp32s2ulpfdpic_gotrel_section(info)->size == 0) + esp32s2ulpfdpic_gotrel_section(info)->flags |= SEC_EXCLUDE; + else + { + esp32s2ulpfdpic_gotrel_section(info)->contents = + (bfd_byte *)bfd_zalloc(dynobj, + esp32s2ulpfdpic_gotrel_section(info)->size); + if (esp32s2ulpfdpic_gotrel_section(info)->contents == NULL) + return FALSE; + } + + esp32s2ulpfdpic_gotfixup_section(info)->size = (gpinfop->g.fixups + 1) * 4; + if (esp32s2ulpfdpic_gotfixup_section(info)->size == 0) + esp32s2ulpfdpic_gotfixup_section(info)->flags |= SEC_EXCLUDE; + else + { + esp32s2ulpfdpic_gotfixup_section(info)->contents = + (bfd_byte *)bfd_zalloc(dynobj, + esp32s2ulpfdpic_gotfixup_section(info)->size); + if (esp32s2ulpfdpic_gotfixup_section(info)->contents == NULL) + return FALSE; + } + + if (elf_hash_table(info)->dynamic_sections_created) + esp32s2ulpfdpic_pltrel_section(info)->size = + gpinfop->g.lzplt / LZPLT_NORMAL_SIZE * get_elf_backend_data(output_bfd)->s->sizeof_rel; + if (esp32s2ulpfdpic_pltrel_section(info)->size == 0) + esp32s2ulpfdpic_pltrel_section(info)->flags |= SEC_EXCLUDE; + else + { + esp32s2ulpfdpic_pltrel_section(info)->contents = + (bfd_byte *)bfd_zalloc(dynobj, + esp32s2ulpfdpic_pltrel_section(info)->size); + if (esp32s2ulpfdpic_pltrel_section(info)->contents == NULL) + return FALSE; + } + + /* Add 4 bytes for every block of at most 65535 lazy PLT entries, + such that there's room for the additional instruction needed to + call the resolver. Since _esp32s2ulpfdpic_assign_got_entries didn't + account for them, our block size is 4 bytes smaller than the real + block size. */ + if (elf_hash_table(info)->dynamic_sections_created) + { + esp32s2ulpfdpic_plt_section(info)->size = gpinfop->g.lzplt + + ((gpinfop->g.lzplt + (ESP32S2ULPFDPIC_LZPLT_BLOCK_SIZE - 4) - LZPLT_NORMAL_SIZE) + / (ESP32S2ULPFDPIC_LZPLT_BLOCK_SIZE - 4) * LZPLT_RESOLVER_EXTRA); + } + + /* Reset it, such that _esp32s2ulpfdpic_assign_plt_entries() can use it to + actually assign lazy PLT entries addresses. */ + gpinfop->g.lzplt = 0; + + /* Save information that we're going to need to generate GOT and PLT + entries. */ + esp32s2ulpfdpic_got_initial_offset(info) = -gpinfop->gothilo.min; + + if (get_elf_backend_data(output_bfd)->want_got_sym) + elf_hash_table(info)->hgot->root.u.def.value + = esp32s2ulpfdpic_got_initial_offset(info); + + if (elf_hash_table(info)->dynamic_sections_created) + esp32s2ulpfdpic_plt_initial_offset(info) = + esp32s2ulpfdpic_plt_section(info)->size; + + htab_traverse(esp32s2ulpfdpic_relocs_info(info), _esp32s2ulpfdpic_assign_plt_entries, + gpinfop); + + /* Allocate the PLT section contents only after + _esp32s2ulpfdpic_assign_plt_entries has a chance to add the size of the + non-lazy PLT entries. */ + if (esp32s2ulpfdpic_plt_section(info)->size == 0) + esp32s2ulpfdpic_plt_section(info)->flags |= SEC_EXCLUDE; + else + { + esp32s2ulpfdpic_plt_section(info)->contents = + (bfd_byte *)bfd_zalloc(dynobj, + esp32s2ulpfdpic_plt_section(info)->size); + if (esp32s2ulpfdpic_plt_section(info)->contents == NULL) + return FALSE; + } + + return TRUE; +} + +/* Set the sizes of the dynamic sections. */ + +static bfd_boolean +elf32_esp32s2ulpfdpic_size_dynamic_sections(bfd *output_bfd, +struct bfd_link_info *info) +{ + struct elf_link_hash_table *htab; + bfd *dynobj; + asection *s; + struct _esp32s2ulpfdpic_dynamic_got_plt_info gpinfo; + + htab = elf_hash_table(info); + dynobj = htab->dynobj; + BFD_ASSERT(dynobj != NULL); + + if (htab->dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ + if (bfd_link_executable(info) && !info->nointerp) + { + s = bfd_get_linker_section(dynobj, ".interp"); + BFD_ASSERT(s != NULL); + s->size = sizeof ELF_DYNAMIC_INTERPRETER; + s->contents = (bfd_byte *)ELF_DYNAMIC_INTERPRETER; + } + } + + memset(&gpinfo, 0, sizeof(gpinfo)); + gpinfo.g.info = info; + + for (;;) + { + htab_t relocs = esp32s2ulpfdpic_relocs_info(info); + + htab_traverse(relocs, _esp32s2ulpfdpic_resolve_final_relocs_info, &relocs); + + if (relocs == esp32s2ulpfdpic_relocs_info(info)) + break; + } + + htab_traverse(esp32s2ulpfdpic_relocs_info(info), _esp32s2ulpfdpic_count_got_plt_entries, + &gpinfo.g); + + /* Allocate space to save the summary information, we're going to + use it if we're doing relaxations. */ + esp32s2ulpfdpic_dynamic_got_plt_info(info) = bfd_alloc(dynobj, sizeof(gpinfo.g)); + + if (!_esp32s2ulpfdpic_size_got_plt(output_bfd, &gpinfo)) + return FALSE; + + if (elf_hash_table(info)->dynamic_sections_created) + { + if (esp32s2ulpfdpic_got_section(info)->size) + if (!_bfd_elf_add_dynamic_entry(info, DT_PLTGOT, 0)) + return FALSE; + + if (esp32s2ulpfdpic_pltrel_section(info)->size) + if (!_bfd_elf_add_dynamic_entry(info, DT_PLTRELSZ, 0) + || !_bfd_elf_add_dynamic_entry(info, DT_PLTREL, DT_REL) + || !_bfd_elf_add_dynamic_entry(info, DT_JMPREL, 0)) + return FALSE; + + if (esp32s2ulpfdpic_gotrel_section(info)->size) + if (!_bfd_elf_add_dynamic_entry(info, DT_REL, 0) + || !_bfd_elf_add_dynamic_entry(info, DT_RELSZ, 0) + || !_bfd_elf_add_dynamic_entry(info, DT_RELENT, + sizeof(Elf32_External_Rel))) + return FALSE; + } + + s = bfd_get_linker_section(dynobj, ".dynbss"); + if (s && s->size == 0) + s->flags |= SEC_EXCLUDE; + + s = bfd_get_linker_section(dynobj, ".rela.bss"); + if (s && s->size == 0) + s->flags |= SEC_EXCLUDE; + + return TRUE; +} + +static bfd_boolean +elf32_esp32s2ulpfdpic_always_size_sections(bfd *output_bfd, +struct bfd_link_info *info) +{ + if (!bfd_link_relocatable(info) + && !bfd_elf_stack_segment_size(output_bfd, info, + "__stacksize", DEFAULT_STACK_SIZE)) + return FALSE; + + return TRUE; +} + +/* Check whether any of the relocations was optimized away, and +subtract it from the relocation or fixup count. */ +static bfd_boolean +_esp32s2ulpfdpic_check_discarded_relocs(bfd *abfd, asection *sec, +struct bfd_link_info *info, + bfd_boolean *changed) +{ + (void)info;// dya - remove warning + (void)changed;// dya - remove warning + Elf_Internal_Shdr *symtab_hdr; + struct elf_link_hash_entry **sym_hashes, **sym_hashes_end; + + if ((sec->flags & SEC_RELOC) == 0 + || sec->reloc_count == 0) + return TRUE; + + symtab_hdr = &elf_tdata(abfd)->symtab_hdr; + sym_hashes = elf_sym_hashes(abfd); + sym_hashes_end = sym_hashes + symtab_hdr->sh_size / sizeof(Elf32_External_Sym); + if (!elf_bad_symtab(abfd)) + sym_hashes_end -= symtab_hdr->sh_info; + + return TRUE; +} + +static bfd_boolean +esp32s2ulpfdpic_elf_discard_info(bfd *ibfd, +struct elf_reloc_cookie *cookie ATTRIBUTE_UNUSED, +struct bfd_link_info *info) +{ + bfd_boolean changed = FALSE; + asection *s; + bfd *obfd = NULL; + + /* Account for relaxation of .eh_frame section. */ + for (s = ibfd->sections; s; s = s->next) + if (s->sec_info_type == SEC_INFO_TYPE_EH_FRAME) + { + if (!_esp32s2ulpfdpic_check_discarded_relocs(ibfd, s, info, &changed)) + return FALSE; + obfd = s->output_section->owner; + } + + if (changed) + { + struct _esp32s2ulpfdpic_dynamic_got_plt_info gpinfo; + + memset(&gpinfo, 0, sizeof(gpinfo)); + memcpy(&gpinfo.g, esp32s2ulpfdpic_dynamic_got_plt_info(info), + sizeof(gpinfo.g)); + + /* Clear GOT and PLT assignments. */ + htab_traverse(esp32s2ulpfdpic_relocs_info(info), + _esp32s2ulpfdpic_reset_got_plt_entries, + NULL); + + if (!_esp32s2ulpfdpic_size_got_plt(obfd, &gpinfo)) + return FALSE; + } + + return TRUE; +} + +static bfd_boolean +elf32_esp32s2ulpfdpic_finish_dynamic_sections(bfd *output_bfd, +struct bfd_link_info *info) +{ + bfd *dynobj; + asection *sdyn; + + dynobj = elf_hash_table(info)->dynobj; + + if (esp32s2ulpfdpic_got_section(info)) + { + BFD_ASSERT(esp32s2ulpfdpic_gotrel_section(info)->size + /* PR 17334: It appears that the GOT section can end up + being bigger than the number of relocs. Presumably + because some relocs have been deleted. A test case has + yet to be generated for verify this, but in the meantime + the test below has been changed from == to >= so that + applications can continue to be built. */ + >= (esp32s2ulpfdpic_gotrel_section(info)->reloc_count + * sizeof(Elf32_External_Rel))); + + if (esp32s2ulpfdpic_gotfixup_section(info)) + { + struct elf_link_hash_entry *hgot = elf_hash_table(info)->hgot; + bfd_vma got_value = hgot->root.u.def.value + + hgot->root.u.def.section->output_section->vma + + hgot->root.u.def.section->output_offset; + + _esp32s2ulpfdpic_add_rofixup(output_bfd, esp32s2ulpfdpic_gotfixup_section(info), + got_value, 0); + + if (esp32s2ulpfdpic_gotfixup_section(info)->size + != (esp32s2ulpfdpic_gotfixup_section(info)->reloc_count * 4)) + { + _bfd_error_handler + ("LINKER BUG: .rofixup section size mismatch"); + return FALSE; + } + } + } + if (elf_hash_table(info)->dynamic_sections_created) + { + BFD_ASSERT(esp32s2ulpfdpic_pltrel_section(info)->size + == (esp32s2ulpfdpic_pltrel_section(info)->reloc_count + * sizeof(Elf32_External_Rel))); + } + + sdyn = bfd_get_linker_section(dynobj, ".dynamic"); + + if (elf_hash_table(info)->dynamic_sections_created) + { + Elf32_External_Dyn * dyncon; + Elf32_External_Dyn * dynconend; + + BFD_ASSERT(sdyn != NULL); + + dyncon = (Elf32_External_Dyn *)sdyn->contents; + dynconend = (Elf32_External_Dyn *)(sdyn->contents + sdyn->size); + + for (; dyncon < dynconend; dyncon++) + { + Elf_Internal_Dyn dyn; + + bfd_elf32_swap_dyn_in(dynobj, dyncon, &dyn); + + switch (dyn.d_tag) + { + default: + break; + + case DT_PLTGOT: + dyn.d_un.d_ptr = esp32s2ulpfdpic_got_section(info)->output_section->vma + + esp32s2ulpfdpic_got_section(info)->output_offset + + esp32s2ulpfdpic_got_initial_offset(info); + bfd_elf32_swap_dyn_out(output_bfd, &dyn, dyncon); + break; + + case DT_JMPREL: + dyn.d_un.d_ptr = esp32s2ulpfdpic_pltrel_section(info) + ->output_section->vma + + esp32s2ulpfdpic_pltrel_section(info)->output_offset; + bfd_elf32_swap_dyn_out(output_bfd, &dyn, dyncon); + break; + + case DT_PLTRELSZ: + dyn.d_un.d_val = esp32s2ulpfdpic_pltrel_section(info)->size; + bfd_elf32_swap_dyn_out(output_bfd, &dyn, dyncon); + break; + } + } + } + + return TRUE; +} + +/* Adjust a symbol defined by a dynamic object and referenced by a +regular object. */ + +static bfd_boolean +elf32_esp32s2ulpfdpic_adjust_dynamic_symbol(struct bfd_link_info *info, +struct elf_link_hash_entry *h) +{ + bfd * dynobj; + + dynobj = elf_hash_table(info)->dynobj; + + /* Make sure we know what is going on here. */ + BFD_ASSERT(dynobj != NULL + && (h->u.weakdef != NULL + || (h->def_dynamic + && h->ref_regular + && !h->def_regular))); + + /* If this is a weak symbol, and there is a real definition, the + processor independent code will have arranged for us to see the + real definition first, and we can just use the same value. */ + if (h->u.weakdef != NULL) + { + BFD_ASSERT(h->u.weakdef->root.type == bfd_link_hash_defined + || h->u.weakdef->root.type == bfd_link_hash_defweak); + h->root.u.def.section = h->u.weakdef->root.u.def.section; + h->root.u.def.value = h->u.weakdef->root.u.def.value; + } + + return TRUE; +} + +/* Perform any actions needed for dynamic symbols. */ + +static bfd_boolean +elf32_esp32s2ulpfdpic_finish_dynamic_symbol +(bfd *output_bfd ATTRIBUTE_UNUSED, +struct bfd_link_info *info ATTRIBUTE_UNUSED, +struct elf_link_hash_entry *h ATTRIBUTE_UNUSED, + Elf_Internal_Sym *sym ATTRIBUTE_UNUSED) +{ + return TRUE; +} + +/* Decide whether to attempt to turn absptr or lsda encodings in +shared libraries into pcrel within the given input section. */ + +static bfd_boolean +esp32s2ulpfdpic_elf_use_relative_eh_frame +(bfd *input_bfd ATTRIBUTE_UNUSED, +struct bfd_link_info *info ATTRIBUTE_UNUSED, + asection *eh_frame_section ATTRIBUTE_UNUSED) +{ + /* We can't use PC-relative encodings in FDPIC binaries, in general. */ + return FALSE; +} + +/* Adjust the contents of an eh_frame_hdr section before they're output. */ + +static bfd_byte +esp32s2ulpfdpic_elf_encode_eh_address(bfd *abfd, +struct bfd_link_info *info, + asection *osec, bfd_vma offset, + asection *loc_sec, bfd_vma loc_offset, + bfd_vma *encoded) +{ + struct elf_link_hash_entry *h; + + h = elf_hash_table(info)->hgot; + BFD_ASSERT(h && h->root.type == bfd_link_hash_defined); + + if (!h || (_esp32s2ulpfdpic_osec_to_segment(abfd, osec) + == _esp32s2ulpfdpic_osec_to_segment(abfd, loc_sec->output_section))) + return _bfd_elf_encode_eh_address(abfd, info, osec, offset, + loc_sec, loc_offset, encoded); + + BFD_ASSERT(_esp32s2ulpfdpic_osec_to_segment(abfd, osec) + == (_esp32s2ulpfdpic_osec_to_segment + (abfd, h->root.u.def.section->output_section))); + + *encoded = osec->vma + offset + - (h->root.u.def.value + + h->root.u.def.section->output_section->vma + + h->root.u.def.section->output_offset); + + return DW_EH_PE_datarel | DW_EH_PE_sdata4; +} + + + +/* Look through the relocs for a section during the first phase. + +Besides handling virtual table relocs for gc, we have to deal with +all sorts of PIC-related relocations. We describe below the +general plan on how to handle such relocations, even though we only +collect information at this point, storing them in hash tables for +perusal of later passes. + +32 relocations are propagated to the linker output when creating +position-independent output. LO16 and HI16 relocations are not +supposed to be encountered in this case. + +LABEL16 should always be resolvable by the linker, since it's only +used by branches. + +LABEL24, on the other hand, is used by calls. If it turns out that +the target of a call is a dynamic symbol, a PLT entry must be +created for it, which triggers the creation of a private function +descriptor and, unless lazy binding is disabled, a lazy PLT entry. + +GPREL relocations require the referenced symbol to be in the same +segment as _gp, but this can only be checked later. + +All GOT, GOTOFF and FUNCDESC relocations require a .got section to +exist. LABEL24 might as well, since it may require a PLT entry, +that will require a got. + +Non-FUNCDESC GOT relocations require a GOT entry to be created +regardless of whether the symbol is dynamic. However, since a +global symbol that turns out to not be exported may have the same +address of a non-dynamic symbol, we don't assign GOT entries at +this point, such that we can share them in this case. A relocation +for the GOT entry always has to be created, be it to offset a +private symbol by the section load address, be it to get the symbol +resolved dynamically. + +FUNCDESC GOT relocations require a GOT entry to be created, and +handled as if a FUNCDESC relocation was applied to the GOT entry in +an object file. + +FUNCDESC relocations referencing a symbol that turns out to NOT be +dynamic cause a private function descriptor to be created. The +FUNCDESC relocation then decays to a 32 relocation that points at +the private descriptor. If the symbol is dynamic, the FUNCDESC +relocation is propagated to the linker output, such that the +dynamic linker creates the canonical descriptor, pointing to the +dynamically-resolved definition of the function. + +Non-FUNCDESC GOTOFF relocations must always refer to non-dynamic +symbols that are assigned to the same segment as the GOT, but we +can only check this later, after we know the complete set of +symbols defined and/or exported. + +FUNCDESC GOTOFF relocations require a function descriptor to be +created and, unless lazy binding is disabled or the symbol is not +dynamic, a lazy PLT entry. Since we can't tell at this point +whether a symbol is going to be dynamic, we have to decide later +whether to create a lazy PLT entry or bind the descriptor directly +to the private function. + +FUNCDESC_VALUE relocations are not supposed to be present in object +files, but they may very well be simply propagated to the linker +output, since they have no side effect. + + +A function descriptor always requires a FUNCDESC_VALUE relocation. +Whether it's in .plt.rel or not depends on whether lazy binding is +enabled and on whether the referenced symbol is dynamic. + +The existence of a lazy PLT requires the resolverStub lazy PLT +entry to be present. + + +As for assignment of GOT, PLT and lazy PLT entries, and private +descriptors, we might do them all sequentially, but we can do +better than that. For example, we can place GOT entries and +private function descriptors referenced using 12-bit operands +closer to the PIC register value, such that these relocations don't +overflow. Those that are only referenced with LO16 relocations +could come next, but we may as well place PLT-required function +descriptors in the 12-bit range to make them shorter. Symbols +referenced with LO16/HI16 may come next, but we may place +additional function descriptors in the 16-bit range if we can +reliably tell that we've already placed entries that are ever +referenced with only LO16. PLT entries are therefore generated as +small as possible, while not introducing relocation overflows in +GOT or FUNCDESC_GOTOFF relocations. Lazy PLT entries could be +generated before or after PLT entries, but not intermingled with +them, such that we can have more lazy PLT entries in range for a +branch to the resolverStub. The resolverStub should be emitted at +the most distant location from the first lazy PLT entry such that +it's still in range for a branch, or closer, if there isn't a need +for so many lazy PLT entries. Additional lazy PLT entries may be +emitted after the resolverStub, as long as branches are still in +range. If the branch goes out of range, longer lazy PLT entries +are emitted. + +We could further optimize PLT and lazy PLT entries by giving them +priority in assignment to closer-to-gr17 locations depending on the +number of occurrences of references to them (assuming a function +that's called more often is more important for performance, so its +PLT entry should be faster), or taking hints from the compiler. +Given infinite time and money... :-) */ + +static bfd_boolean +esp32s2ulpfdpic_check_relocs(bfd *abfd, struct bfd_link_info *info, +asection *sec, const Elf_Internal_Rela *relocs) +{ + Elf_Internal_Shdr *symtab_hdr; + struct elf_link_hash_entry **sym_hashes; + const Elf_Internal_Rela *rel; + const Elf_Internal_Rela *rel_end; + + if (bfd_link_relocatable(info)) + return TRUE; + + symtab_hdr = &elf_tdata(abfd)->symtab_hdr; + sym_hashes = elf_sym_hashes(abfd); + + rel_end = relocs + sec->reloc_count; + for (rel = relocs; rel < rel_end; rel++) + { + struct elf_link_hash_entry *h; + unsigned long r_symndx; + + r_symndx = ELF32_R_SYM(rel->r_info); + if (r_symndx < symtab_hdr->sh_info) + h = NULL; + else + h = sym_hashes[r_symndx - symtab_hdr->sh_info]; + + switch (ELF32_R_TYPE(rel->r_info)) + { + /* This relocation describes the C++ object vtable hierarchy. + Reconstruct it for later use during GC. */ + case R_ESP32S2ULP_GNU_VTINHERIT: + if (!bfd_elf_gc_record_vtinherit(abfd, sec, h, rel->r_offset)) + return FALSE; + break; + + /* This relocation describes which C++ vtable entries are actually + used. Record for later use during GC. */ + case R_ESP32S2ULP_GNU_VTENTRY: + BFD_ASSERT(h != NULL); + if (h != NULL + && !bfd_elf_gc_record_vtentry(abfd, sec, h, rel->r_addend)) + return FALSE; + break; + + case R_ESP32S2ULP_JUMPR: + break; + + default: + _bfd_error_handler + /* xgettext:c-format */ + (_("%B: unsupported relocation type %i"), + abfd, ELF32_R_TYPE(rel->r_info)); + return FALSE; + } + } + + return TRUE; +} + +/* Set the right machine number for a Blackfin ELF file. */ + +static bfd_boolean +elf32_esp32s2ulp_object_p(bfd *abfd) +{ + bfd_default_set_arch_mach(abfd, bfd_arch_esp32s2ulp, 0); + return (((elf_elfheader(abfd)->e_flags & EF_ESP32S2ULP_FDPIC) != 0) + == (IS_FDPIC(abfd))); +} + +static bfd_boolean +elf32_esp32s2ulp_set_private_flags(bfd * abfd, flagword flags) +{ + elf_elfheader(abfd)->e_flags = flags; + elf_flags_init(abfd) = TRUE; + return TRUE; +} + +/* Display the flags field. */ +static bfd_boolean +elf32_esp32s2ulp_print_private_bfd_data(bfd * abfd, void * ptr) +{ + FILE *file = (FILE *)ptr; + flagword flags; + + BFD_ASSERT(abfd != NULL && ptr != NULL); + + /* Print normal ELF private data. */ + _bfd_elf_print_private_bfd_data(abfd, ptr); + + flags = elf_elfheader(abfd)->e_flags; + + /* xgettext:c-format */ + fprintf(file, _("private flags = %lx:"), elf_elfheader(abfd)->e_flags); + + if (flags & EF_ESP32S2ULP_PIC) + fprintf(file, " -fpic"); + + if (flags & EF_ESP32S2ULP_FDPIC) + fprintf(file, " -mfdpic"); + + fputc('\n', file); + + return TRUE; +} + +/* Merge backend specific data from an object file to the output +object file when linking. */ + +static bfd_boolean +elf32_esp32s2ulp_merge_private_bfd_data(bfd *ibfd, struct bfd_link_info *info) +{ + bfd *obfd = info->output_bfd; + flagword old_flags, new_flags; + bfd_boolean error = FALSE; + + new_flags = elf_elfheader(ibfd)->e_flags; + old_flags = elf_elfheader(obfd)->e_flags; + + if (new_flags & EF_ESP32S2ULP_FDPIC) + new_flags &= ~EF_ESP32S2ULP_PIC; + +#ifndef DEBUG + if (0) +#endif + _bfd_error_handler + ("old_flags = 0x%.8lx, new_flags = 0x%.8lx, init = %s, filename = %s", + old_flags, new_flags, elf_flags_init(obfd) ? "yes" : "no", + bfd_get_filename(ibfd)); + + if (!elf_flags_init(obfd)) /* First call, no flags set. */ + { + elf_flags_init(obfd) = TRUE; + elf_elfheader(obfd)->e_flags = new_flags; + } + + if (((new_flags & EF_ESP32S2ULP_FDPIC) == 0) != (!IS_FDPIC(obfd))) + { + error = TRUE; + if (IS_FDPIC(obfd)) + _bfd_error_handler + (_("%s: cannot link non-fdpic object file into fdpic executable"), + bfd_get_filename(ibfd)); + else + _bfd_error_handler + (_("%s: cannot link fdpic object file into non-fdpic executable"), + bfd_get_filename(ibfd)); + } + + if (error) + bfd_set_error(bfd_error_bad_value); + + return !error; +} + +/* esp32s2ulp ELF linker hash entry. */ + +struct esp32s2ulp_link_hash_entry +{ + struct elf_link_hash_entry root; + + /* Number of PC relative relocs copied for this symbol. */ + struct esp32s2ulp_pcrel_relocs_copied *pcrel_relocs_copied; +}; + +/* esp32s2ulp ELF linker hash table. */ + +struct esp32s2ulp_link_hash_table +{ + struct elf_link_hash_table root; + + /* Small local sym cache. */ + struct sym_cache sym_cache; +}; + +#define esp32s2ulp_hash_entry(ent) ((struct esp32s2ulp_link_hash_entry *) (ent)) + +static struct bfd_hash_entry * +esp32s2ulp_link_hash_newfunc(struct bfd_hash_entry *entry, +struct bfd_hash_table *table, const char *string) +{ + struct bfd_hash_entry *ret = entry; + + /* Allocate the structure if it has not already been allocated by a + subclass. */ + if (ret == NULL) + ret = bfd_hash_allocate(table, sizeof(struct esp32s2ulp_link_hash_entry)); + if (ret == NULL) + return ret; + + /* Call the allocation method of the superclass. */ + ret = _bfd_elf_link_hash_newfunc(ret, table, string); + if (ret != NULL) + esp32s2ulp_hash_entry(ret)->pcrel_relocs_copied = NULL; + + return ret; +} + +/* Create an esp32s2ulp ELF linker hash table. */ + +static struct bfd_link_hash_table * +esp32s2ulp_link_hash_table_create(bfd * abfd) +{ + struct esp32s2ulp_link_hash_table *ret; + bfd_size_type amt = sizeof(struct esp32s2ulp_link_hash_table); + + ret = bfd_zmalloc(amt); + if (ret == NULL) + return NULL; + + if (!_bfd_elf_link_hash_table_init(&ret->root, abfd, + esp32s2ulp_link_hash_newfunc, + sizeof(struct elf_link_hash_entry), + ESP32S2ULP_ELF_DATA)) + { + free(ret); + return NULL; + } + + ret->sym_cache.abfd = NULL; + + return &ret->root.root; +} + +/* The size in bytes of an entry in the procedure linkage table. */ + +/* Finish up the dynamic sections. */ + +static bfd_boolean +esp32s2ulp_finish_dynamic_sections(bfd * output_bfd ATTRIBUTE_UNUSED, +struct bfd_link_info *info) +{ + bfd *dynobj; + asection *sdyn; + + dynobj = elf_hash_table(info)->dynobj; + + sdyn = bfd_get_linker_section(dynobj, ".dynamic"); + + if (elf_hash_table(info)->dynamic_sections_created) + { + Elf32_External_Dyn *dyncon, *dynconend; + + BFD_ASSERT(sdyn != NULL); + + dyncon = (Elf32_External_Dyn *)sdyn->contents; + dynconend = (Elf32_External_Dyn *)(sdyn->contents + sdyn->size); + for (; dyncon < dynconend; dyncon++) + { + Elf_Internal_Dyn dyn; + + bfd_elf32_swap_dyn_in(dynobj, dyncon, &dyn); + + } + + } + return TRUE; +} + +/* Finish up dynamic symbol handling. We set the contents of various +dynamic sections here. */ + +static bfd_boolean +esp32s2ulp_finish_dynamic_symbol(bfd * output_bfd, +struct bfd_link_info *info, +struct elf_link_hash_entry *h, + Elf_Internal_Sym * sym) +{ + if (h->got.offset != (bfd_vma)-1) + { + asection *sgot; + asection *srela; + Elf_Internal_Rela rela; + bfd_byte *loc; + + /* This symbol has an entry in the global offset table. + Set it up. */ + + sgot = elf_hash_table(info)->sgot; + srela = elf_hash_table(info)->srelgot; + BFD_ASSERT(sgot != NULL && srela != NULL); + + rela.r_offset = (sgot->output_section->vma + + sgot->output_offset + + (h->got.offset & ~(bfd_vma)1)); + + /* If this is a -Bsymbolic link, and the symbol is defined + locally, we just want to emit a RELATIVE reloc. Likewise if + the symbol was forced to be local because of a version file. + The entry in the global offset table will already have been + initialized in the relocate_section function. */ + if (bfd_link_pic(info) + && (info->symbolic + || h->dynindx == -1 || h->forced_local) && h->def_regular) + { + _bfd_error_handler(_("*** check this relocation %s"), + __FUNCTION__); + rela.r_info = ELF32_R_INFO(0, R_ESP32S2ULP_RIMM16); + rela.r_addend = bfd_get_signed_32(output_bfd, + (sgot->contents + + + (h->got. + offset & ~(bfd_vma)1))); + } + else + { + bfd_put_32(output_bfd, (bfd_vma)0, + sgot->contents + (h->got.offset & ~(bfd_vma)1)); + rela.r_info = ELF32_R_INFO(h->dynindx, R_ESP32S2ULP_GOT); + rela.r_addend = 0; + } + + loc = srela->contents; + loc += srela->reloc_count++ * sizeof(Elf32_External_Rela); + bfd_elf32_swap_reloca_out(output_bfd, &rela, loc); + } + + if (h->needs_copy) + { + BFD_ASSERT(0); + } + /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. */ + if (strcmp(h->root.root.string, "__DYNAMIC") == 0 + || h == elf_hash_table(info)->hgot) + sym->st_shndx = SHN_ABS; + + return TRUE; +} + +/* Adjust a symbol defined by a dynamic object and referenced by a +regular object. The current definition is in some section of the +dynamic object, but we're not including those sections. We have to +change the definition to something the rest of the link can +understand. */ + +static bfd_boolean +esp32s2ulp_adjust_dynamic_symbol(struct bfd_link_info *info, +struct elf_link_hash_entry *h) +{ + bfd *dynobj; + asection *s; + unsigned int power_of_two; + + dynobj = elf_hash_table(info)->dynobj; + + /* Make sure we know what is going on here. */ + BFD_ASSERT(dynobj != NULL + && (h->needs_plt + || h->u.weakdef != NULL + || (h->def_dynamic && h->ref_regular && !h->def_regular))); + + /* If this is a function, put it in the procedure linkage table. We + will fill in the contents of the procedure linkage table later, + when we know the address of the .got section. */ + if (h->type == STT_FUNC || h->needs_plt) + { + BFD_ASSERT(0); + } + + /* If this is a weak symbol, and there is a real definition, the + processor independent code will have arranged for us to see the + real definition first, and we can just use the same value. */ + if (h->u.weakdef != NULL) + { + BFD_ASSERT(h->u.weakdef->root.type == bfd_link_hash_defined + || h->u.weakdef->root.type == bfd_link_hash_defweak); + h->root.u.def.section = h->u.weakdef->root.u.def.section; + h->root.u.def.value = h->u.weakdef->root.u.def.value; + return TRUE; + } + + /* This is a reference to a symbol defined by a dynamic object which + is not a function. */ + + /* If we are creating a shared library, we must presume that the + only references to the symbol are via the global offset table. + For such cases we need not do anything here; the relocations will + be handled correctly by relocate_section. */ + if (bfd_link_pic(info)) + return TRUE; + + /* We must allocate the symbol in our .dynbss section, which will + become part of the .bss section of the executable. There will be + an entry for this symbol in the .dynsym section. The dynamic + object will contain position independent code, so all references + from the dynamic object to this symbol will go through the global + offset table. The dynamic linker will use the .dynsym entry to + determine the address it must put in the global offset table, so + both the dynamic object and the regular object will refer to the + same memory location for the variable. */ + + s = bfd_get_linker_section(dynobj, ".dynbss"); + BFD_ASSERT(s != NULL); + +#if 0 /* Bfin does not currently have a COPY reloc. */ + /* We must generate a R_ESP32S2ULP_COPY reloc to tell the dynamic linker to + copy the initial value out of the dynamic object and into the + runtime process image. We need to remember the offset into the + .rela.bss section we are going to use. */ + if ((h->root.u.def.section->flags & SEC_ALLOC) != 0) + { + asection *srel; + + srel = bfd_get_linker_section(dynobj, ".rela.bss"); + BFD_ASSERT(srel != NULL); + srel->size += sizeof(Elf32_External_Rela); + h->needs_copy = 1; + } +#else + if ((h->root.u.def.section->flags & SEC_ALLOC) != 0) + { + _bfd_error_handler(_("the esp32s2ulp target does not currently support the generation of copy relocations")); + return FALSE; + } +#endif + /* We need to figure out the alignment required for this symbol. I + have no idea how ELF linkers handle this. */ + power_of_two = bfd_log2(h->size); + if (power_of_two > 3) + power_of_two = 3; + + /* Apply the required alignment. */ + s->size = BFD_ALIGN(s->size, (bfd_size_type)(1 << power_of_two)); + if (power_of_two > bfd_get_section_alignment(dynobj, s)) + { + if (!bfd_set_section_alignment(dynobj, s, power_of_two)) + return FALSE; + } + + /* Define the symbol as being at this point in the section. */ + h->root.u.def.section = s; + h->root.u.def.value = s->size; + + /* Increment the section size to make room for the symbol. */ + s->size += h->size; + + return TRUE; +} + +/* The esp32s2ulp linker needs to keep track of the number of relocs that it +decides to copy in check_relocs for each symbol. This is so that it +can discard PC relative relocs if it doesn't need them when linking +with -Bsymbolic. We store the information in a field extending the +regular ELF linker hash table. */ + +/* This structure keeps track of the number of PC relative relocs we have +copied for a given symbol. */ + +struct esp32s2ulp_pcrel_relocs_copied +{ + /* Next section. */ + struct esp32s2ulp_pcrel_relocs_copied *next; + /* A section in dynobj. */ + asection *section; + /* Number of relocs copied in this section. */ + bfd_size_type count; +}; + +/* This function is called via elf_link_hash_traverse if we are +creating a shared object. In the -Bsymbolic case it discards the +space allocated to copy PC relative relocs against symbols which +are defined in regular objects. For the normal shared case, it +discards space for pc-relative relocs that have become local due to +symbol visibility changes. We allocated space for them in the +check_relocs routine, but we won't fill them in in the +relocate_section routine. + +We also check whether any of the remaining relocations apply +against a readonly section, and set the DF_TEXTREL flag in this +case. */ + +static bfd_boolean +esp32s2ulp_discard_copies(struct elf_link_hash_entry *h, void * inf) +{ + struct bfd_link_info *info = (struct bfd_link_info *) inf; + struct esp32s2ulp_pcrel_relocs_copied *s; + + if (!h->def_regular || (!info->symbolic && !h->forced_local)) + { + if ((info->flags & DF_TEXTREL) == 0) + { + /* Look for relocations against read-only sections. */ + for (s = esp32s2ulp_hash_entry(h)->pcrel_relocs_copied; + s != NULL; s = s->next) + if ((s->section->flags & SEC_READONLY) != 0) + { + info->flags |= DF_TEXTREL; + break; + } + } + + return TRUE; + } + + for (s = esp32s2ulp_hash_entry(h)->pcrel_relocs_copied; + s != NULL; s = s->next) + s->section->size -= s->count * sizeof(Elf32_External_Rela); + + return TRUE; +} + +static bfd_boolean +esp32s2ulp_size_dynamic_sections(bfd * output_bfd ATTRIBUTE_UNUSED, +struct bfd_link_info *info) +{ + bfd *dynobj; + asection *s; + bfd_boolean relocs; + + dynobj = elf_hash_table(info)->dynobj; + BFD_ASSERT(dynobj != NULL); + + if (elf_hash_table(info)->dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ + if (bfd_link_executable(info)) + { + s = bfd_get_linker_section(dynobj, ".interp"); + BFD_ASSERT(s != NULL); + s->size = sizeof ELF_DYNAMIC_INTERPRETER; + s->contents = (unsigned char *)ELF_DYNAMIC_INTERPRETER; + } + } + else + { + /* We may have created entries in the .rela.got section. + However, if we are not creating the dynamic sections, we will + not actually use these entries. Reset the size of .rela.got, + which will cause it to get stripped from the output file + below. */ + s = elf_hash_table(info)->srelgot; + if (s != NULL) + s->size = 0; + } + + /* If this is a -Bsymbolic shared link, then we need to discard all + PC relative relocs against symbols defined in a regular object. + For the normal shared case we discard the PC relative relocs + against symbols that have become local due to visibility changes. + We allocated space for them in the check_relocs routine, but we + will not fill them in in the relocate_section routine. */ + if (bfd_link_pic(info)) + elf_link_hash_traverse(elf_hash_table(info), + esp32s2ulp_discard_copies, info); + + /* The check_relocs and adjust_dynamic_symbol entry points have + determined the sizes of the various dynamic sections. Allocate + memory for them. */ + relocs = FALSE; + for (s = dynobj->sections; s != NULL; s = s->next) + { + const char *name; + bfd_boolean strip; + + if ((s->flags & SEC_LINKER_CREATED) == 0) + continue; + + /* It's OK to base decisions on the section name, because none + of the dynobj section names depend upon the input files. */ + name = bfd_get_section_name(dynobj, s); + + strip = FALSE; + + if (CONST_STRNEQ(name, ".rela")) + { + if (s->size == 0) + { + /* If we don't need this section, strip it from the + output file. This is mostly to handle .rela.bss and + .rela.plt. We must create both sections in + create_dynamic_sections, because they must be created + before the linker maps input sections to output + sections. The linker does that before + adjust_dynamic_symbol is called, and it is that + function which decides whether anything needs to go + into these sections. */ + strip = TRUE; + } + else + { + relocs = TRUE; + + /* We use the reloc_count field as a counter if we need + to copy relocs into the output file. */ + s->reloc_count = 0; + } + } + else if (!CONST_STRNEQ(name, ".got")) + { + /* It's not one of our sections, so don't allocate space. */ + continue; + } + + if (strip) + { + s->flags |= SEC_EXCLUDE; + continue; + } + + /* Allocate memory for the section contents. */ + /* FIXME: This should be a call to bfd_alloc not bfd_zalloc. + Unused entries should be reclaimed before the section's contents + are written out, but at the moment this does not happen. Thus in + order to prevent writing out garbage, we initialise the section's + contents to zero. */ + s->contents = (bfd_byte *)bfd_zalloc(dynobj, s->size); + if (s->contents == NULL && s->size != 0) + return FALSE; + } + + if (elf_hash_table(info)->dynamic_sections_created) + { + /* Add some entries to the .dynamic section. We fill in the + values later, in esp32s2ulp_finish_dynamic_sections, but we + must add the entries now so that we get the correct size for + the .dynamic section. The DT_DEBUG entry is filled in by the + dynamic linker and used by the debugger. */ +#define add_dynamic_entry(TAG, VAL) \ + _bfd_elf_add_dynamic_entry (info, TAG, VAL) + + if (!bfd_link_pic(info)) + { + if (!add_dynamic_entry(DT_DEBUG, 0)) + return FALSE; + } + + + if (relocs) + { + if (!add_dynamic_entry(DT_RELA, 0) + || !add_dynamic_entry(DT_RELASZ, 0) + || !add_dynamic_entry(DT_RELAENT, + sizeof(Elf32_External_Rela))) + return FALSE; + } + + if ((info->flags & DF_TEXTREL) != 0) + { + if (!add_dynamic_entry(DT_TEXTREL, 0)) + return FALSE; + } + } +#undef add_dynamic_entry + + return TRUE; +} + +/* Given a .data section and a .emreloc in-memory section, store +relocation information into the .emreloc section which can be +used at runtime to relocate the section. This is called by the +linker when the --embedded-relocs switch is used. This is called +after the add_symbols entry point has been called for all the +objects, and before the final_link entry point is called. */ + +bfd_boolean +bfd_esp32s2ulp_elf32_create_embedded_relocs(bfd *abfd, +struct bfd_link_info *info, + asection *datasec, + asection *relsec, + char **errmsg) +{ + Elf_Internal_Shdr *symtab_hdr; + Elf_Internal_Sym *isymbuf = NULL; + Elf_Internal_Rela *internal_relocs = NULL; + Elf_Internal_Rela *irel, *irelend; + bfd_byte *p; + bfd_size_type amt; + + BFD_ASSERT(!bfd_link_relocatable(info)); + + *errmsg = NULL; + + if (datasec->reloc_count == 0) + return TRUE; + + symtab_hdr = &elf_tdata(abfd)->symtab_hdr; + + /* Get a copy of the native relocations. */ + internal_relocs = (_bfd_elf_link_read_relocs + (abfd, datasec, NULL, (Elf_Internal_Rela *)NULL, + info->keep_memory)); + if (internal_relocs == NULL) + goto error_return; + + amt = (bfd_size_type)datasec->reloc_count * 12; + relsec->contents = (bfd_byte *)bfd_alloc(abfd, amt); + if (relsec->contents == NULL) + goto error_return; + + p = relsec->contents; + + irelend = internal_relocs + datasec->reloc_count; + for (irel = internal_relocs; irel < irelend; irel++, p += 12) + { + /* We are going to write a four byte longword into the runtime + reloc section. The longword will be the address in the data + section which must be relocated. It is followed by the name + of the target section NUL-padded or truncated to 8 + characters. */ + + /* We can only relocate absolute longword relocs at run time. */ + *errmsg = _("unsupported reloc type"); + bfd_set_error(bfd_error_bad_value); + goto error_return; + } + + if (isymbuf != NULL && symtab_hdr->contents != (unsigned char *)isymbuf) + free(isymbuf); + if (internal_relocs != NULL + && elf_section_data(datasec)->relocs != internal_relocs) + free(internal_relocs); + return TRUE; + +error_return: + if (isymbuf != NULL && symtab_hdr->contents != (unsigned char *)isymbuf) + free(isymbuf); + if (internal_relocs != NULL + && elf_section_data(datasec)->relocs != internal_relocs) + free(internal_relocs); + return FALSE; +} + +struct bfd_elf_special_section const elf32_esp32s2ulp_special_sections[] = +{ + { NULL, 0, 0, 0, 0 } +}; + + +#define TARGET_LITTLE_SYM esp32s2ulp_elf32_vec +#define TARGET_LITTLE_NAME "elf32-esp32s2ulp" +#define ELF_ARCH bfd_arch_esp32s2ulp +#define ELF_TARGET_ID ESP32S2ULP_ELF_DATA +#define ELF_MACHINE_CODE EM_ESP32S2ULP +#define ELF_MAXPAGESIZE 0x1000 +#define elf_symbol_leading_char '_' + +#define bfd_elf32_bfd_reloc_type_lookup esp32s2ulp_bfd_reloc_type_lookup +#define bfd_elf32_bfd_reloc_name_lookup \ + esp32s2ulp_bfd_reloc_name_lookup +#define elf_info_to_howto esp32s2ulp_info_to_howto +#define elf_info_to_howto_rel 0 +#define elf_backend_object_p elf32_esp32s2ulp_object_p + +#define bfd_elf32_bfd_is_local_label_name \ + esp32s2ulp_is_local_label_name +#define esp32s2ulp_hash_table(p) \ + ((struct esp32s2ulp_link_hash_table *) (p)->hash) + + + +#define elf_backend_create_dynamic_sections \ + _bfd_elf_create_dynamic_sections +#define bfd_elf32_bfd_link_hash_table_create \ + esp32s2ulp_link_hash_table_create +#define bfd_elf32_bfd_final_link bfd_elf_gc_common_final_link + +#define elf_backend_check_relocs esp32s2ulp_check_relocs +#define elf_backend_adjust_dynamic_symbol \ + esp32s2ulp_adjust_dynamic_symbol +#define elf_backend_size_dynamic_sections \ + esp32s2ulp_size_dynamic_sections +#define elf_backend_relocate_section esp32s2ulp_relocate_section +#define elf_backend_finish_dynamic_symbol \ + esp32s2ulp_finish_dynamic_symbol +#define elf_backend_finish_dynamic_sections \ + esp32s2ulp_finish_dynamic_sections +#define elf_backend_gc_mark_hook esp32s2ulp_gc_mark_hook +#define elf_backend_gc_sweep_hook esp32s2ulp_gc_sweep_hook +#define bfd_elf32_bfd_merge_private_bfd_data \ + elf32_esp32s2ulp_merge_private_bfd_data +#define bfd_elf32_bfd_set_private_flags \ + elf32_esp32s2ulp_set_private_flags +#define bfd_elf32_bfd_print_private_bfd_data \ + elf32_esp32s2ulp_print_private_bfd_data +#define elf_backend_final_write_processing \ + elf32_esp32s2ulp_final_write_processing +#define elf_backend_reloc_type_class elf32_esp32s2ulp_reloc_type_class +#define elf_backend_stack_align 8 +#define elf_backend_can_gc_sections 1 +#define elf_backend_special_sections elf32_esp32s2ulp_special_sections +#define elf_backend_can_refcount 1 +#define elf_backend_want_got_plt 0 +#define elf_backend_plt_readonly 1 +#define elf_backend_want_plt_sym 0 +#define elf_backend_got_header_size 12 +#define elf_backend_rela_normal 1 + +#include "elf32-target.h" + +#undef TARGET_LITTLE_SYM +#define TARGET_LITTLE_SYM esp32s2ulp_elf32_fdpic_vec +#undef TARGET_LITTLE_NAME +#define TARGET_LITTLE_NAME "elf32-esp32s2ulpfdpic" +#undef elf32_bed +#define elf32_bed elf32_esp32s2ulpfdpic_bed + +#undef elf_backend_gc_sweep_hook +#define elf_backend_gc_sweep_hook esp32s2ulpfdpic_gc_sweep_hook + +#undef elf_backend_got_header_size +#define elf_backend_got_header_size 0 + +#undef elf_backend_relocate_section +#define elf_backend_relocate_section esp32s2ulpfdpic_relocate_section +#undef elf_backend_check_relocs +#define elf_backend_check_relocs esp32s2ulpfdpic_check_relocs + +#undef bfd_elf32_bfd_link_hash_table_create +#define bfd_elf32_bfd_link_hash_table_create \ + esp32s2ulpfdpic_elf_link_hash_table_create +#undef elf_backend_always_size_sections +#define elf_backend_always_size_sections \ + elf32_esp32s2ulpfdpic_always_size_sections + +#undef elf_backend_create_dynamic_sections +#define elf_backend_create_dynamic_sections \ + elf32_esp32s2ulpfdpic_create_dynamic_sections +#undef elf_backend_adjust_dynamic_symbol +#define elf_backend_adjust_dynamic_symbol \ + elf32_esp32s2ulpfdpic_adjust_dynamic_symbol +#undef elf_backend_size_dynamic_sections +#define elf_backend_size_dynamic_sections \ + elf32_esp32s2ulpfdpic_size_dynamic_sections +#undef elf_backend_finish_dynamic_symbol +#define elf_backend_finish_dynamic_symbol \ + elf32_esp32s2ulpfdpic_finish_dynamic_symbol +#undef elf_backend_finish_dynamic_sections +#define elf_backend_finish_dynamic_sections \ + elf32_esp32s2ulpfdpic_finish_dynamic_sections + +#undef elf_backend_discard_info +#define elf_backend_discard_info \ + esp32s2ulpfdpic_elf_discard_info +#undef elf_backend_can_make_relative_eh_frame +#define elf_backend_can_make_relative_eh_frame \ + esp32s2ulpfdpic_elf_use_relative_eh_frame +#undef elf_backend_can_make_lsda_relative_eh_frame +#define elf_backend_can_make_lsda_relative_eh_frame \ + esp32s2ulpfdpic_elf_use_relative_eh_frame +#undef elf_backend_encode_eh_address +#define elf_backend_encode_eh_address \ + esp32s2ulpfdpic_elf_encode_eh_address + +#undef elf_backend_may_use_rel_p +#define elf_backend_may_use_rel_p 1 +#undef elf_backend_may_use_rela_p +#define elf_backend_may_use_rela_p 1 +/* We use REL for dynamic relocations only. */ +#undef elf_backend_default_use_rela_p +#define elf_backend_default_use_rela_p 1 + +#undef elf_backend_omit_section_dynsym +#define elf_backend_omit_section_dynsym _esp32s2ulpfdpic_link_omit_section_dynsym + +#include "elf32-target.h" diff --git a/bfd/elf32-esp32s2ulp.h b/bfd/elf32-esp32s2ulp.h new file mode 100644 index 00000000000..0469e2c5d09 --- /dev/null +++ b/bfd/elf32-esp32s2ulp.h @@ -0,0 +1,3 @@ +extern bfd_boolean bfd_esp32s2ulp_elf32_create_embedded_relocs + (bfd *, struct bfd_link_info *, struct bfd_section *, struct bfd_section *, + char **); diff --git a/bfd/elf32-esp32ulp.c b/bfd/elf32-esp32ulp.c old mode 100755 new mode 100644 diff --git a/bfd/mep-relocs.pl b/bfd/mep-relocs.pl old mode 100755 new mode 100644 diff --git a/bfd/targets.c b/bfd/targets.c index 1af6678dcd0..b1c828bf133 100644 --- a/bfd/targets.c +++ b/bfd/targets.c @@ -701,6 +701,8 @@ extern const bfd_target bfin_elf32_vec; extern const bfd_target bfin_elf32_fdpic_vec; extern const bfd_target esp32ulp_elf32_vec; extern const bfd_target esp32ulp_elf32_fdpic_vec; +extern const bfd_target esp32s2ulp_elf32_vec; +extern const bfd_target esp32s2ulp_elf32_fdpic_vec; extern const bfd_target cr16_elf32_vec; extern const bfd_target cris_aout_vec; extern const bfd_target cris_elf32_vec; @@ -1032,6 +1034,9 @@ static const bfd_target * const _bfd_target_vector[] = &esp32ulp_elf32_vec, &esp32ulp_elf32_fdpic_vec, + &esp32s2ulp_elf32_vec, + &esp32s2ulp_elf32_fdpic_vec, + &cr16_elf32_vec, &cris_aout_vec, diff --git a/binutils/readelf.c b/binutils/readelf.c index bec5f4d3fcc..89d8cebccde 100644 --- a/binutils/readelf.c +++ b/binutils/readelf.c @@ -97,6 +97,7 @@ #include "elf/avr.h" #include "elf/bfin.h" #include "elf/esp32ulp.h" +#include "elf/esp32s2ulp.h" #include "elf/cr16.h" #include "elf/cris.h" #include "elf/crx.h" @@ -1569,6 +1570,10 @@ dump_relocations (Filedata * filedata, rtype = elf_esp32ulp_reloc_type(type); break; + case EM_ESP32S2ULP: + rtype = elf_esp32s2ulp_reloc_type(type); + break; + case EM_CYGNUS_MEP: rtype = elf_mep_reloc_type (type); break; @@ -3200,6 +3205,15 @@ get_machine_flags (Filedata * filedata, unsigned e_flags, unsigned e_machine) break; + case EM_ESP32S2ULP: + if (e_flags & EF_ESP32S2ULP_PIC) + strcat(buf, ", PIC"); + + if (e_flags & EF_ESP32S2ULP_FDPIC) + strcat(buf, ", FDPIC"); + + break; + case EM_CYGNUS_FRV: switch (e_flags & EF_FRV_CPU_MASK) { diff --git a/config.sub b/config.sub old mode 100755 new mode 100644 index e147e33f56f..aa07ded4b36 --- a/config.sub +++ b/config.sub @@ -257,6 +257,10 @@ case $1 in basic_machine=esp32ulp-unknown os=linux ;; + esp32s2dum) + basic_machine=esp32s2ulp-unknown + os=linux + ;; cegcc) basic_machine=arm-unknown os=cegcc @@ -1022,6 +1026,10 @@ case $cpu-$vendor in cpu=esp32ulp os=linux ;; + esp32s2dum-*) + cpu=esp32s2ulp + os=linux + ;; c54x-*) cpu=tic54x ;; @@ -1177,7 +1185,7 @@ case $cpu-$vendor in | asmjs \ | ba \ | be32 | be64 \ - | bfin | esp32ulp | bpf | bs2000 \ + | bfin | esp32ulp | esp32s2ulp | bpf | bs2000 \ | c[123]* | c30 | [cjt]90 | c4x \ | c8051 | clipper | craynv | csky | cydra \ | d10v | d30v | dlx | dsp16xx \ diff --git a/configure b/configure index bd05764c339..1776cbfa7de 100755 --- a/configure +++ b/configure @@ -3490,6 +3490,9 @@ case "${target}" in esp32ulp-*-*) noconfigdirs="$noconfigdirs target-boehm-gc" ;; + esp32s2ulp-*-*) + noconfigdirs="$noconfigdirs target-boehm-gc" + ;; cris-*-* | crisv32-*-*) case "${target}" in *-*-linux*) diff --git a/configure.ac b/configure.ac index 2e5154cc81e..cea201c0312 100644 --- a/configure.ac +++ b/configure.ac @@ -734,6 +734,9 @@ case "${target}" in esp32ulp-*-*) noconfigdirs="$noconfigdirs target-boehm-gc" ;; + esp32s2ulp-*-*) + noconfigdirs="$noconfigdirs target-boehm-gc" + ;; cris-*-* | crisv32-*-*) case "${target}" in *-*-linux*) diff --git a/djunpack.bat b/djunpack.bat old mode 100755 new mode 100644 diff --git a/elfcpp/elfcpp.h b/elfcpp/elfcpp.h index dab4bbe2ac3..d9851089e88 100644 --- a/elfcpp/elfcpp.h +++ b/elfcpp/elfcpp.h @@ -263,6 +263,7 @@ enum EM EM_MSP430 = 105, EM_BLACKFIN = 106, EM_ESP32DUM = 245, + EM_ESP32S2DUM = 246, EM_SE_C33 = 107, EM_SEP = 108, EM_ARCA = 109, diff --git a/gas/Makefile.am b/gas/Makefile.am index 4dd8eb44458..ebefa8f2eb1 100644 --- a/gas/Makefile.am +++ b/gas/Makefile.am @@ -136,6 +136,7 @@ TARGET_CPU_CFILES = \ config/tc-bfin.c \ config/tc-bpf.c \ config/tc-esp32ulp.c \ + config/tc-esp32s2ulp.c \ config/tc-cr16.c \ config/tc-cris.c \ config/tc-crx.c \ @@ -213,6 +214,7 @@ TARGET_CPU_HFILES = \ config/tc-bfin.h \ config/tc-bpf.h \ config/tc-esp32ulp.h \ + config/tc-esp32s2ulp.h \ config/tc-cr16.h \ config/tc-cris.h \ config/tc-crx.h \ @@ -373,6 +375,7 @@ EXTRA_SCRIPTS = .gdbinit EXTRA_DIST = m68k-parse.c itbl-parse.c itbl-parse.h itbl-lex.c \ bfin-parse.c bfin-parse.h bfin-lex.c \ esp32ulp-parse.c esp32ulp-parse.h esp32ulp-lex.c \ + esp32s2ulp-parse.c esp32s2ulp-parse.h esp32s2ulp-lex.c \ rl78-parse.c rl78-parse.h \ rx-parse.c rx-parse.h diff --git a/gas/Makefile.in b/gas/Makefile.in index 3e9da6bc9a7..a5bba8a6f36 100644 --- a/gas/Makefile.in +++ b/gas/Makefile.in @@ -116,7 +116,7 @@ DIST_COMMON = NEWS README ChangeLog $(srcdir)/Makefile.in \ $(am__configure_deps) $(srcdir)/config.in \ $(srcdir)/../mkinstalldirs $(srcdir)/gdbinit.in \ $(srcdir)/gdbinit.in $(top_srcdir)/po/Make-in m68k-parse.c \ - bfin-parse.c esp32ulp-parse.c rl78-parse.c rx-parse.c itbl-parse.c itbl-lex.c \ + bfin-parse.c esp32ulp-parse.c esp32s2ulp-parse.c rl78-parse.c rx-parse.c itbl-parse.c itbl-lex.c \ $(srcdir)/../depcomp $(srcdir)/../ylwrap ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 am__aclocal_m4_deps = $(top_srcdir)/../bfd/acinclude.m4 \ @@ -532,6 +532,7 @@ TARGET_CPU_CFILES = \ config/tc-bfin.c \ config/tc-bpf.c \ config/tc-esp32ulp.c \ + config/tc-esp32s2ulp.c \ config/tc-cr16.c \ config/tc-cris.c \ config/tc-crx.c \ @@ -609,6 +610,7 @@ TARGET_CPU_HFILES = \ config/tc-bfin.h \ config/tc-bpf.h \ config/tc-esp32ulp.h \ + config/tc-esp32s2ulp.h \ config/tc-cr16.h \ config/tc-cris.h \ config/tc-crx.h \ @@ -762,6 +764,7 @@ EXTRA_SCRIPTS = .gdbinit EXTRA_DIST = m68k-parse.c itbl-parse.c itbl-parse.h itbl-lex.c \ bfin-parse.c bfin-parse.h bfin-lex.c \ esp32ulp-parse.c esp32ulp-parse.h esp32ulp-lex.c \ + esp32s2ulp-parse.c esp32s2ulp-parse.h esp32s2ulp-lex.c \ rl78-parse.c rl78-parse.h \ rx-parse.c rx-parse.h @@ -800,7 +803,7 @@ as_new_DEPENDENCIES = $(TARG_CPU_O) $(OBJ_FORMAT_O) $(ATOF_TARG_O) \ EXTRA_as_new_SOURCES = $(CFILES) $(HFILES) $(TARGET_CPU_CFILES) \ $(TARGET_CPU_HFILES) $(OBJ_FORMAT_CFILES) $(OBJ_FORMAT_HFILES) \ $(TARG_ENV_CFILES) $(CONFIG_ATOF_CFILES) $(MULTI_CFILES) \ - config/m68k-parse.y config/bfin-parse.y config/esp32ulp-parse.y config/rl78-parse.y \ + config/m68k-parse.y config/bfin-parse.y config/esp32ulp-parse.y config/esp32s2ulp-parse.y config/rl78-parse.y \ config/rx-parse.y EXPECT = expect RUNTEST = runtest @@ -910,6 +913,10 @@ config/tc-bfin.$(OBJEXT): config/$(am__dirstamp) \ config/$(DEPDIR)/$(am__dirstamp) config/tc-bpf.$(OBJEXT): config/$(am__dirstamp) \ config/$(DEPDIR)/$(am__dirstamp) +config/tc-esp32ulp.$(OBJEXT): config/$(am__dirstamp) \ + config/$(DEPDIR)/$(am__dirstamp) +config/tc-esp32s2ulp.$(OBJEXT): config/$(am__dirstamp) \ + config/$(DEPDIR)/$(am__dirstamp) config/tc-cr16.$(OBJEXT): config/$(am__dirstamp) \ config/$(DEPDIR)/$(am__dirstamp) config/tc-cris.$(OBJEXT): config/$(am__dirstamp) \ @@ -1108,6 +1115,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/as.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/atof-generic.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/esp32ulp-parse.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/esp32s2ulp-parse.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cgen.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/compress-debug.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cond.Po@am__quote@ @@ -1167,6 +1175,8 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-avr.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-bfin.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-bpf.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-esp32ulp.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-esp32s2ulp.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-cr16.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-cris.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-crx.Po@am__quote@ @@ -1457,6 +1467,7 @@ maintainer-clean-generic: -rm -f config/rl78-parse.c -rm -f config/rx-parse.c -rm -f esp32ulp-parse.c + -rm -f esp32s2ulp-parse.c -rm -f itbl-lex.c -rm -f itbl-parse.c clean: clean-recursive @@ -1638,14 +1649,21 @@ esp32ulp-parse.h: esp32ulp-parse.c esp32ulp-parse.h: ; @true $(srcdir)/config/esp32ulp-parse.h: ; @true -esp32ulp-lex.c: $(srcdir)/config/esp32ulp-lex.l - $(SHELL) $(YLWRAP) $(srcdir)/config/esp32ulp-lex.l lex.yy.c esp32ulp-lex.c -- $(LEXCOMPILE) -esp32ulp-lex-wrapper.@OBJEXT@: $(srcdir)/config/esp32ulp-lex-wrapper.c esp32ulp-lex.c esp32ulp-parse.h $(srcdir)/config/esp32ulp-defs.h -@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $(srcdir)/config/esp32ulp-lex-wrapper.c $(NO_WERROR) +esp32s2ulp-parse.c: $(srcdir)/config/esp32s2ulp-parse.y + $(SHELL) $(YLWRAP) $(srcdir)/config/esp32s2ulp-parse.y y.tab.c esp32s2ulp-parse.c y.tab.h esp32s2ulp-parse.h -- $(YACCCOMPILE) -d ; +esp32s2ulp-parse.h: esp32s2ulp-parse.c +esp32s2ulp-parse.h: ; @true +$(srcdir)/config/esp32s2ulp-parse.h: ; @true + +esp32s2ulp-lex.c: $(srcdir)/config/esp32s2ulp-lex.l + $(SHELL) $(YLWRAP) $(srcdir)/config/esp32s2ulp-lex.l lex.yy.c esp32s2ulp-lex.c -- $(LEXCOMPILE) +esp32s2ulp-lex-wrapper.@OBJEXT@: $(srcdir)/config/esp32s2ulp-lex-wrapper.c esp32s2ulp-lex.c esp32s2ulp-parse.h $(srcdir)/config/esp32s2ulp-defs.h +@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $(srcdir)/config/esp32s2ulp-lex-wrapper.c $(NO_WERROR) @am__fastdepCC_TRUE@ mv -f $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po -@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='esp32ulp-lex-wrapper.c' object='$@' libtool=no @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='esp32s2ulp-lex-wrapper.c' object='$@' libtool=no @AMDEPBACKSLASH@ @AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ -@am__fastdepCC_FALSE@ $(COMPILE) -c $(srcdir)/config/esp32ulp-lex-wrapper.c $(NO_WERROR) +@am__fastdepCC_FALSE@ $(COMPILE) -c $(srcdir)/config/esp32s2ulp-lex-wrapper.c $(NO_WERROR) + rl78-parse.c: $(srcdir)/config/rl78-parse.y $(srcdir)/../bfd/reloc.c $(SHELL) $(YLWRAP) $(srcdir)/config/rl78-parse.y y.tab.c rl78-parse.c y.tab.h rl78-parse.h -- $(YACCCOMPILE) -d ; rl78-parse.h: rl78-parse.c diff --git a/gas/config/esp32s2ulp-aux.h b/gas/config/esp32s2ulp-aux.h new file mode 100644 index 00000000000..d17c5d07f29 --- /dev/null +++ b/gas/config/esp32s2ulp-aux.h @@ -0,0 +1,65 @@ +/* ESP32ULP ELF-32 support for GAS + Copyright (c) 2016-2017 Espressif Systems (Shanghai) PTE LTD. + + This file is part of GAS, the GNU Assembler. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#include "esp32s2ulp-defs.h" + +#define REG_T Register * + +INSTR_T esp32s2ulp_gen_progctrl (int, int); + +INSTR_T esp32s2ulp_gen_alu_op(int, int, int); +INSTR_T esp32s2ulp_gen_alu_ADDR(int, int, int); +INSTR_T esp32s2ulp_gen_alu_ADDI(int, int, int); +INSTR_T esp32s2ulp_gen_jump_r(int, int); +INSTR_T esp32s2ulp_gen_jump_i(Expr_Node* , int); +INSTR_T esp32s2ulp_gen_jump_rels(Expr_Node*, int, int); +INSTR_T esp32s2ulp_move_const2reg(int, int); +INSTR_T esp32s2ulp_move_addr2reg(int, Expr_Node*); + +INSTR_T esp32s2ulp_wr_mem_stlh(int low_hi, int dst_reg, int src_reg, Expr_Node* offset); +INSTR_T esp32s2ulp_wr_mem_st32(int dst_reg, int src_reg, Expr_Node* offset, Expr_Node* label); +INSTR_T esp32s2ulp_wr_mem_sti32(int dst_reg, int src_reg, Expr_Node* label); +INSTR_T esp32s2ulp_wr_mem_st_l(int low_hi, int dst_reg, int src_reg, Expr_Node* offset, Expr_Node* label); +INSTR_T esp32s2ulp_wr_mem_sti_l(int dst_reg, int src_reg, Expr_Node* label); +INSTR_T esp32s2ulp_wr_mem_sti(int dst_reg, int src_reg); +INSTR_T esp32s2ulp_wr_mem_offset(Expr_Node* offset); + +INSTR_T esp32s2ulp_rd_mem_addr(int lh, int dst_reg, int src_reg, Expr_Node* addr); +INSTR_T esp32s2ulp_rd_mem_offset(int dst_reg, int src_reg, int addr); +INSTR_T esp32s2ulp_cmd_halt(void); +INSTR_T esp32s2ulp_cmd_sleep(Expr_Node* cycles); +INSTR_T esp32s2ulp_cmd_wakeup(Expr_Node* wake); +INSTR_T esp32s2ulp_cmd_wait(Expr_Node* cycles); +INSTR_T esp32s2ulp_cmd_tsens(int dreg, Expr_Node* delay); +INSTR_T esp32s2ulp_cmd_adc(int dreg, Expr_Node* sar_sel, Expr_Node* mux); +INSTR_T esp32s2ulp_gen_alu_r(int dst, int src1, int src2, int operation); +INSTR_T esp32s2ulp_gen_alu_i(int dst, int src1, Expr_Node* imm, int operation); +INSTR_T esp32s2ulp_cmd_stage(int dir, Expr_Node* imm); +INSTR_T esp32s2ulp_cmd_stage_rst(void); +INSTR_T esp32s2ulp_cmd_jump_relr(Expr_Node* step, Expr_Node* thresh, int cond); +INSTR_T esp32s2ulp_cmd_jump_rels(Expr_Node* step, Expr_Node* thresh, int cond); +INSTR_T esp32s2ulp_cmd_reg_rd(Expr_Node* addr, Expr_Node* high, Expr_Node* low); +INSTR_T esp32s2ulp_cmd_reg_wr(Expr_Node* addr, Expr_Node* high, Expr_Node* low, Expr_Node* data); +// I2C operations +INSTR_T esp32s2ulp_cmd_i2c_rd(Expr_Node* i2c_addr, Expr_Node* high, Expr_Node* low, Expr_Node* i2c_sel); +INSTR_T esp32s2ulp_cmd_i2c_wr(Expr_Node* i2c_addr, Expr_Node* high, Expr_Node* low, Expr_Node* i2c_sel, Expr_Node* data); + + + diff --git a/gas/config/esp32s2ulp-defs.h b/gas/config/esp32s2ulp-defs.h new file mode 100644 index 00000000000..e899f4981d4 --- /dev/null +++ b/gas/config/esp32s2ulp-defs.h @@ -0,0 +1,240 @@ +/* esp32s2ulp-defs.h + ESP32ULP GNU Assembler + + Copyright (c) 2016-2017 Espressif Systems (Shanghai) PTE LTD. + + based on Copyright (C) 2005-2017 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#ifndef ESP32S2ULP_PARSE_H +#define ESP32S2ULP_PARSE_H + +#include "opcode/esp32s2ulp.h" + +#define PCREL 1 +#define CODE_FRAG_SIZE 4096 /* 1 page. */ + + + +/* High-Nibble: group code, low nibble: register code. */ + + +#define T_REG_R 0x00 +#define T_REG_P 0x10 +#define T_REG_I 0x20 +#define T_REG_B 0x30 +#define T_REG_L 0x34 +#define T_REG_M 0x24 +#define T_REG_A 0x40 + +/* All registers above this value don't + belong to a usuable register group. */ +#define T_NOGROUP 0xa0 + +/* Flags. */ +#define F_REG_NONE 0 +#define F_REG_HIGH 1 +#define F_REG_LOW 2 + +enum machine_registers +{ + REG_R0 = T_REG_R, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7, REG_R8, +}; + +/* Register type checking macros. */ + +#define CLASS_MASK 0xf0 + +/* register type checking. */ +#define _TYPECHECK(r, x) (((r).regno & CLASS_MASK) == T_REG_##x) + +#define IS_DREG(r) _TYPECHECK(r, R) + +typedef enum +{ + ones_compl, + twos_compl, + mult, + divide, + mod, + add, + sub, + lsh, + rsh, + logand, + logior, + logxor +} expr_opcodes_t; + +struct expressionS; + +#define SYMBOL_T symbolS* + +struct expression_cell +{ + int value; + SYMBOL_T symbol; +}; + +/* User Type Definitions. */ +struct esp32s2ulp_insn +{ + unsigned long value; + struct esp32s2ulp_insn *next; + struct expression_cell *exp; + int pcrel; + int reloc; + int mult; // Multiple instructions command +}; + +#define INSTR_T struct esp32s2ulp_insn* +#define EXPR_T struct expression_cell* + +typedef struct expr_node_struct Expr_Node; + +extern INSTR_T gencode(unsigned long x); +extern INSTR_T conscode(INSTR_T head, INSTR_T tail); +extern INSTR_T conctcode(INSTR_T head, INSTR_T tail); +extern INSTR_T note_reloc +(INSTR_T code, Expr_Node *, int reloc, int pcrel); +extern INSTR_T note_reloc1 +(INSTR_T code, const char * sym, int reloc, int pcrel); +extern INSTR_T note_reloc2 +(INSTR_T code, const char *symbol, int reloc, int value, int pcrel); + +/* Types of expressions. */ +typedef enum +{ + Expr_Node_Binop, /* Binary operator. */ + Expr_Node_Unop, /* Unary operator. */ + Expr_Node_Reloc, /* Symbol to be relocated. */ + Expr_Node_GOT_Reloc, /* Symbol to be relocated using the GOT. */ + Expr_Node_Constant /* Constant. */ +} Expr_Node_Type; + +/* Types of operators. */ +typedef enum +{ + Expr_Op_Type_Add, + Expr_Op_Type_Sub, + Expr_Op_Type_Mult, + Expr_Op_Type_Div, + Expr_Op_Type_Mod, + Expr_Op_Type_Lshift, + Expr_Op_Type_Rshift, + Expr_Op_Type_BAND, /* Bitwise AND. */ + Expr_Op_Type_BOR, /* Bitwise OR. */ + Expr_Op_Type_BXOR, /* Bitwise exclusive OR. */ + Expr_Op_Type_LAND, /* Logical AND. */ + Expr_Op_Type_LOR, /* Logical OR. */ + Expr_Op_Type_NEG, + Expr_Op_Type_COMP /* Complement. */ +} Expr_Op_Type; + +/* The value that can be stored ... depends on type. */ +typedef union +{ + const char *s_value; /* if relocation symbol, the text. */ + long long i_value; /* if constant, the value. */ + Expr_Op_Type op_value; /* if operator, the value. */ +} Expr_Node_Value; + +/* The expression node. */ +struct expr_node_struct +{ + Expr_Node_Type type; + Expr_Node_Value value; + Expr_Node *Left_Child; + Expr_Node *Right_Child; +}; + + +/* Operations on the expression node. */ +Expr_Node *Expr_Node_Create(Expr_Node_Type type, + Expr_Node_Value value, + Expr_Node *Left_Child, + Expr_Node *Right_Child); + +/* Generate the reloc structure as a series of instructions. */ +INSTR_T Expr_Node_Gen_Reloc(Expr_Node *head, int parent_reloc); + +#define MKREF(x) mkexpr (0,x) + +#define NULL_CODE ((INSTR_T) 0) + +#ifndef EXPR_VALUE +#define EXPR_VALUE(x) (((x)->type == Expr_Node_Constant) ? ((x)->value.i_value) : 0) +#endif +#ifndef EXPR_SYMBOL +#define EXPR_SYMBOL(x) ((x)->symbol) +#endif + + +typedef long reg_t; + + +typedef struct _register +{ + reg_t regno; /* Register ID as defined in machine_registers. */ + int flags; +} Register; + + +typedef struct _macfunc +{ + char n; + char op; + char w; + char P; + Register dst; + Register s0; + Register s1; +} Macfunc; + +typedef enum +{ + SEMANTIC_ERROR, + NO_INSN_GENERATED, + INSN_GENERATED +} parse_state; + + +#ifdef __cplusplus +extern "C" { +#endif + + extern int debug_codeselection; + + void error(const char *format, ...); + void warn(char *format, ...); + int semantic_error(char *syntax); + void semantic_error_2(char *syntax); + + EXPR_T mkexpr(int, SYMBOL_T); + + /* Defined in esp32s2ulp-lex.l. */ + void set_start_state(void); + + extern int insn_regmask(int, int); +#ifdef __cplusplus +} +#endif + +#endif /* ESP32S2ULP_PARSE_H */ + diff --git a/gas/config/esp32s2ulp-lex-wrapper.c b/gas/config/esp32s2ulp-lex-wrapper.c new file mode 100644 index 00000000000..c58a70f6c9f --- /dev/null +++ b/gas/config/esp32s2ulp-lex-wrapper.c @@ -0,0 +1,25 @@ +/* + ESP32ULP GNU Assembler + + Copyright (c) 2016-2017 Espressif Systems (Shanghai) PTE LTD. + + This file is part of GAS, the GNU Assembler. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + + +#include "sysdep.h" +#include "esp32s2ulp-lex.c" diff --git a/gas/config/esp32s2ulp-lex.l b/gas/config/esp32s2ulp-lex.l new file mode 100644 index 00000000000..0824a21307a --- /dev/null +++ b/gas/config/esp32s2ulp-lex.l @@ -0,0 +1,346 @@ +/* esp32s2ulp-lex.l ESP32S2ULP GNU Assembler + + Copyright (c) 2016-2017 Espressif Systems (Shanghai) PTE LTD. + + based on Copyright (C) 2005-2017 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ +%{ + +#include "as.h" +#include "esp32s2ulp-defs.h" +#include "esp32s2ulp-parse.h" + +static long parse_int (char **end); +static int parse_reg (Register *r, int type, char *rt); +int yylex (void); + +#define _REG yylval.reg + + +%} + +/* Define Start States ... Actually we will use exclusion. + If no start state is specified it should match any state + and would match some keyword rules only with + initial. */ +%s KEYWORD +%s FLAGS + +%% + +[nN][oO][pP] return NOP; +[aA][dD][dD] return ADD; +[sS][uU][bB] return SUB; +[aA][nN][dD] return AND; +[mM][oO][vV][eE] return MOVE; +[oO][rR] return OR; +[lL][sS][hH] return LSH; +[rR][sS][hH] return RSH; + +[jJ][uU][mM][pP] { BEGIN 0; return JUMP;} +[jJ][uU][mM][pP][rR] { BEGIN 0; return JUMPR;} +[jJ][uU][mM][pP][sS] { BEGIN 0; return JUMPS;} +[sS][tT][3][2] return ST32; +[sS][tT][iI][3][2] return STI32; +[sS][tT][oO] return STO; +[sS][tT][iI] return STI; +[sS][tT] return ST; +[sS][tT][lL] return STL; +[sS][tT][hH] return STH; +[lL][dD] return LD; +[lL][dD][lL] return LDL; +[lL][dD][hH] return LDH; +[hH][aA][lL][tT] return HALT; +[wW][aA][kK][eE] return WAKE; +[sS][lL][eE][eE][pP] return SLEEP; +[tT][sS][eE][nN][sS] return TSENS; +[wW][aA][iI][tT] return WAIT; +[aA][dD][cC] return ADC; +[sS][tT][aA][gG][eE][_][iI][nN][cC] return STAGE_INC; +[sS][tT][aA][gG][eE][_][dD][eE][cC] return STAGE_DEC; +[sS][tT][aA][gG][eE][_][rR][sS][tT] return STAGE_RST; +[rR][eE][gG][_][rR][dD] return REG_RD; +[rR][eE][gG][_][wW][rR] return REG_WR; +[iI][2][cC][_][rR][dD] return I2C_RD; +[iI][2][cC][_][wW][rR] return I2C_WR; + + +[eE][qQ] return EQ; +[oO][vV] return OV; +[gG][tT] return GT; +[gG][eE] return GE; +[lL][eE] return LE; +[lL][tT] return LT; + + +[rR][0-3] return parse_reg (&yylval.reg, T_REG_R, yytext); + +[Gg][Oo][Tt] return GOT; + + +"~" return TILDA; +"|" return BAR; +"^" return CARET; +"]" return RBRACK; +"[" return LBRACK; +">>" return GREATER_GREATER; +"<<" return LESS_LESS; +"<" return LESS_THAN; +"(" BEGIN(FLAGS); return LPAREN; +")" BEGIN(INITIAL); return RPAREN; +":" return COLON; +"/" return SLASH; +"-" return MINUS; +"," return COMMA; +"+" return PLUS; +"*" return STAR; +"&" return AMPERSAND; +"%" return PERCENT; +"!" return BANG; +";" return SEMICOLON; +"@" return AT; + +([0-9]+)|(0[xX][0-9a-fA-F]+)|([bhfodBHOFD]#[0-9a-fA-F]+)|(0"."[0-9]+) { + yylval.value = parse_int (&yytext); + return NUMBER; + } +([0-9]+[bf])|([[:alpha:]\x80-\xff_$.][[:alnum:]\x80-\xff_$.]*) { + if (isdigit(yytext[0])) { + char lc= yytext[strlen(yytext)-1]; + if (lc == 'b') { + char *name = fb_label_name (atoi(yytext), 0); + yylval.symbol = symbol_find (name); + if ((yylval.symbol!= NULL) && (S_IS_DEFINED (yylval.symbol))) { + know (SEG_NORMAL (S_GET_SEGMENT (yylval.symbol))); + } else { + as_bad (_("backward ref to unknown label \"%d:\""), (int) atoi(yytext)); + } + } else if (lc == 'f') { + char *name = fb_label_name (atoi(yytext), 1); + yylval.symbol = symbol_find_or_make (name); + #ifndef many_segments + know (S_GET_SEGMENT (yylval.symbol) == undefined_section + || S_GET_SEGMENT (yylval.symbol) == text_section || S_GET_SEGMENT (yylval.symbol) == data_section); + #endif + } + } else { + yylval.symbol = symbol_find_or_make (yytext); + symbol_mark_used (yylval.symbol); + } + return SYMBOL; + } + +[ \t\n] ; +"/*".*"*/" ; +. return yytext[0]; +%% +static long parse_int (char **end) +{ + char fmt = '\0'; + int not_done = 1; + int shiftvalue = 0; + const char * char_bag; + long value = 0; + char *arg = *end; + + while (*arg && *arg == ' ') + arg++; + + switch (*arg) + { + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + fmt = 'd'; + break; + + case '0': /* Accept different formatted integers hex octal and binary. */ + { + char c = *++arg; + arg++; + if (c == 'x' || c == 'X') /* Hex input. */ + fmt = 'h'; + else if (c == 'b' || c == 'B') + fmt = 'b'; + else if (c == '.') + fmt = 'f'; + else + { /* Octal. */ + arg--; + fmt = 'o'; + } + break; + } + + case 'd': + case 'D': + case 'h': + case 'H': + case 'o': + case 'O': + case 'b': + case 'B': + case 'f': + case 'F': + { + fmt = *arg++; + if (*arg == '#') + arg++; + } + } + + switch (fmt) + { + case 'h': + case 'H': + shiftvalue = 4; + char_bag = "0123456789ABCDEFabcdef"; + break; + + case 'o': + case 'O': + shiftvalue = 3; + char_bag = "01234567"; + break; + + case 'b': + case 'B': + shiftvalue = 1; + char_bag = "01"; + break; + +/* The assembler allows for fractional constants to be created + by either the 0.xxxx or the f#xxxx format + + i.e. 0.5 would result in 0x4000 + + note .5 would result in the identifier .5. + + The assembler converts to fractional format 1.15 by the simple rule: + + value = (short) (finput * (1 << 15)). */ + + case 'f': + case 'F': + { + float fval = 0.0; + float pos = 10.0; + while (1) + { + int c; + c = *arg++; + + if (c >= '0' && c <= '9') + { + float digit = (c - '0') / pos; + fval = fval + digit; + pos = pos * 10.0; + } + else + { + *--arg = c; + value = (short) (fval * (1 << 15)); + break; + } + } + *end = arg+1; + return value; + } + + case 'd': + case 'D': + default: + { + while (1) + { + char c; + c = *arg++; + if (c >= '0' && c <= '9') + value = (value * 10) + (c - '0'); + else + { + /* Constants that are suffixed with k|K are multiplied by 1024 + This suffix is only allowed on decimal constants. */ + if (c == 'k' || c == 'K') + value *= 1024; + else + *--arg = c; + break; + } + } + *end = arg+1; + return value; + } + } + + while (not_done) + { + char c; + c = *arg++; + if (c == 0 || !strchr (char_bag, c)) + { + not_done = 0; + *--arg = c; + } + else + { + if (c >= 'a' && c <= 'z') + c = c - ('a' - '9') + 1; + else if (c >= 'A' && c <= 'Z') + c = c - ('A' - '9') + 1; + + c -= '0'; + value = (value << shiftvalue) + c; + } + } + *end = arg+1; + return value; +} + + +static int parse_reg (Register *r, int cl, char *rt) +{ + r->regno = cl | (rt[1] - '0'); + r->flags = F_REG_NONE; + return REG; +} + +/* Our start state is KEYWORD as we have + command keywords such as PREFETCH. */ + +void +set_start_state (void) +{ + BEGIN KEYWORD; +} + + +#ifndef yywrap +int +yywrap () +{ + return 1; +} +#endif diff --git a/gas/config/esp32s2ulp-parse.y b/gas/config/esp32s2ulp-parse.y new file mode 100644 index 00000000000..a113a87a06c --- /dev/null +++ b/gas/config/esp32s2ulp-parse.y @@ -0,0 +1,1193 @@ +/* esp32s2ulp-parse.y Espressif ESP32S2ULP Parser + + Copyright (c) 2016-2017 Espressif Systems (Shanghai) PTE LTD. + + based on Copyright (C) 2016-2017 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ +%{ + +#include "as.h" + +#include "esp32s2ulp-aux.h" /* Opcode generating auxiliaries. */ +#include "elf/common.h" +#include "elf/esp32s2ulp.h" + +#define IS_IMM(expr, bits) value_match (expr, bits, 0, 1, 1) +#define IS_UIMM(expr, bits) value_match (expr, bits, 0, 1, 0) +#define PROGCTRL(prgfunc, poprnd) \ + esp32s2ulp_gen_progctrl (prgfunc, poprnd) + +#define ALU_ADDR(dst, src1, src2) \ + esp32s2ulp_gen_alu_ADDR(dst.regno, src1.regno, src2.regno) + +#define ALU_ADDI(dst, src1, imm) \ + esp32s2ulp_gen_alu_ADDI(dst.regno, src1.regno, imm) + +#define JUMP_R(dst, cond) \ + esp32s2ulp_gen_jump_r(dst.regno, cond) +#define JUMP_I(dst, cond) \ + esp32s2ulp_gen_jump_i(dst, cond) + +#define CMD_JUMPR(step, tresh, cond) \ + esp32s2ulp_cmd_jump_relr(step, tresh, cond) +#define CMD_JUMPS(step, tresh, cond) \ + esp32s2ulp_cmd_jump_rels(step, tresh, cond) + +#define MOVE_C2R(dst, data) \ + esp32s2ulp_move_const2reg(dst.regno, data) +#define MOVE_E2R(dst, addr) \ + esp32s2ulp_move_addr2reg(dst.regno, addr) + +// ---- Store operations -------------------- +//INSTR_T esp32s2ulp_wr_mem_stlh(int low_hi, int dst_reg, int src_reg, Expr_Node* offset); +//INSTR_T esp32s2ulp_wr_mem_st32(int dst_reg, int src_reg, Expr_Node* offset, Expr_Node* label); +//INSTR_T esp32s2ulp_wr_mem_sti32(int dst_reg, int src_reg, Expr_Node* label); +//INSTR_T esp32s2ulp_wr_mem_st_l(int low_hi, int dst_reg, int src_reg, Expr_Node* offset, Expr_Node* label); +//INSTR_T esp32s2ulp_wr_mem_sti_l(int dst_reg, int src_reg, Expr_Node* label); +//INSTR_T esp32s2ulp_wr_mem_sti(int dst_reg, int src_reg); +//INSTR_T esp32s2ulp_wr_mem_offset(Expr_Node* offset); + +#define WR_MEM_STLR(lh, dst, src, offset) \ + esp32s2ulp_wr_mem_stlh(lh, dst.regno, src.regno, offset) + +#define WR_MEM_ST32(dst, src, offset, label) \ + esp32s2ulp_wr_mem_st32(dst.regno, src.regno, offset, label) + +#define WR_MEM_STI32(dst, src, label) \ + esp32s2ulp_wr_mem_sti32(dst.regno, src.regno, label) + +#define WR_MEM_ST_L(lh, dst, src, offset, label) \ + esp32s2ulp_wr_mem_st_l(lh, dst.regno, src.regno, offset, label) + +#define WR_MEM_STI_L(dst, src, label) \ + esp32s2ulp_wr_mem_sti_l(dst.regno, src.regno, label) + +#define WR_MEM_STI(dst, src) \ + esp32s2ulp_wr_mem_sti(dst.regno, src.regno) + + +#define WR_MEM_STO(offset) \ + esp32s2ulp_wr_mem_offset(offset) +// ---------------------------------------------- + +#define RD_MEM_ADDR(lh, dst, src, addr) \ + esp32s2ulp_rd_mem_addr(lh, dst.regno, src.regno, addr) +#define RD_MEM_OFFSET(dst, src, addr) \ + esp32s2ulp_rd_mem_offset(dst.regno, src.regno, addr) + +#define CMD_REG_RD(addr, high, low) \ + esp32s2ulp_cmd_reg_rd(addr, high, low) +#define CMD_REG_WR(addr, high, low, data) \ + esp32s2ulp_cmd_reg_wr(addr, high, low, data) + +#define CMD_I2C_RD(i2c_addr, high, low, i2c_sel) \ + esp32s2ulp_cmd_i2c_rd(i2c_addr, high, low, i2c_sel) +#define CMD_I2C_WR(i2c_addr, high, low, i2c_sel, data) \ + esp32s2ulp_cmd_i2c_wr(i2c_addr, high, low, i2c_sel, data) + + + +#define CMD_HALT() \ + esp32s2ulp_cmd_halt() +#define CMD_WAKEUP(wake) \ + esp32s2ulp_cmd_wakeup(wake) +#define CMD_SLEEP(cycles) \ + esp32s2ulp_cmd_sleep(cycles) +#define CMD_WAIT(cycles) \ + esp32s2ulp_cmd_wait(cycles) + +#define CMD_TSENS(dreg, delay) \ + esp32s2ulp_cmd_tsens(dreg.regno, delay) + +#define CMD_ADC(dreg, sar_sel, mux) \ + esp32s2ulp_cmd_adc(dreg.regno, sar_sel, mux) + +#define CMD_ALUR(dst, src1, src2, operation) \ + esp32s2ulp_gen_alu_r(dst.regno,src1.regno,src2.regno, operation) +#define CMD_ALUI(dst, src1, imm, operation) \ + esp32s2ulp_gen_alu_i(dst.regno, src1.regno, imm, operation) +#define CMD_ALUI_DIR(dst, imm, operation) \ + esp32s2ulp_gen_alu_i(dst.regno, 0, imm, operation) + +#define CMD_STAGE(dir, imm) \ + esp32s2ulp_cmd_stage(dir, imm) +#define CMD_STAGE_RST() \ + esp32s2ulp_cmd_stage_rst() + +static int value_match (Expr_Node *, int, int, int, int); + +extern FILE *errorf; +extern INSTR_T insn; + +static Expr_Node *binary (Expr_Op_Type, Expr_Node *, Expr_Node *); +static Expr_Node *unary (Expr_Op_Type, Expr_Node *); + +static void notethat (const char *, ...); + +extern char *yytext; +int yyerror (const char *); + +/* Used to set SRCx fields to all 1s as described in the PRM. */ + +void error (const char *format, ...) +{ + va_list ap; + static char buffer[2000]; + + va_start (ap, format); + vsprintf (buffer, format, ap); + va_end (ap); + + as_bad ("%s", buffer); +} + +int +yyerror (const char *msg) +{ + if (msg[0] == '\0') + error ("%s", msg); + + else if (yytext[0] != ';') + error ("%s. Input text was %s.", msg, yytext); + else + error ("%s.", msg); + + return -1; +} + +extern int yylex (void); +/* Return true if a value is inside a range. */ +#define IN_RANGE(x, low, high) \ + (((EXPR_VALUE(x)) >= (low)) && (EXPR_VALUE(x)) <= ((high))) + + +%} + +%union { + INSTR_T instr; + Expr_Node *expr; + SYMBOL_T symbol; + long value; + Register reg; + Macfunc macfunc; + struct { int r0; int s0; int x0; int aop; } modcodes; + struct { int r0; } r0; +} + + +/* Registers. */ +%token REG + +/* Progctrl. */ +%token NOP +%token JUMP JUMPR JUMPS + +/* DYA tokens*/ +%token ADD +%token SUB +%token LSH +%token RSH +%token AND +%token OR +%token MOVE + +%token ST32 +%token STO +%token STI +%token STI32 +%token ST +%token STL +%token STH +%token LD +%token LDL +%token LDH +%token HALT +%token WAKE +%token SLEEP +%token TSENS +%token WAIT +%token ADC +%token STAGE_INC +%token STAGE_DEC +%token STAGE_RST +%token REG_RD +%token REG_WR +%token I2C_RD +%token I2C_WR + +/* Emulator only. */ +%token ABORT + +/* Operators. */ +%token NOT TILDA BANG +%token AMPERSAND BAR +%token PERCENT +%token CARET +%token BXOR + +%token MINUS PLUS STAR SLASH +%token NEG + +/* Shift/rotate ops. */ +%token SHIFT LSHIFT ASHIFT BXORSHIFT +%token ROT +%token LESS_LESS GREATER_GREATER +%token _GREATER_GREATER_GREATER +%token DIVS DIVQ + +/* In place operators. */ +%token GE LT LE GT OV EQ +%token LESS_THAN + +/* Cache. */ +%token FLUSHINV FLUSH +%token IFLUSH PREFETCH + +/* Misc. */ +%token PRNT +%token OUTC +%token WHATREG +%token TESTSET + +/* Modifiers. */ +%token ASL ASR +%token B W +%token NS S CO SCO +%token TH TL +%token BP +%token BREV +%token X Z +%token R RND RNDL RNDH RND12 RND20 +%token V +%token LO HI + +/* Bit ops. */ +%token BITTGL BITCLR BITSET BITTST BITMUX + + +/* Semantic auxiliaries. */ + +%token COMMA +%token COLON SEMICOLON +%token RPAREN LPAREN LBRACK RBRACK +%token SYMBOL NUMBER +%token GOT GOT17M4 FUNCDESC_GOT17M4 +%token AT + +/* Types. */ +%type asm + +%type NUMBER +%type expr_1 +%type asm_1 + +%type searchmod +%type branchmod +%type branchrel +%type branchrels + +%type symbol +%type SYMBOL +%type eterm +%type REG +%type expr +%type got +%type got_or_expr +%type any_gotrel GOT GOT17M4 FUNCDESC_GOT17M4 + +/* Precedence rules. */ +%left BAR +%left CARET +%left AMPERSAND +%left LESS_LESS GREATER_GREATER +%left PLUS MINUS +%left STAR SLASH PERCENT + + +%right TILDA BANG +%start statement +%% +statement: + | asm + { + insn = $1; + if (insn == (INSTR_T) 0) + return NO_INSN_GENERATED; + else if (insn == (INSTR_T) - 1) + return SEMANTIC_ERROR; + else + return INSN_GENERATED; + } + ; + +asm: asm_1 SEMICOLON + /* Parallel instructions. */ + | error + { + $$ = 0; + yyerror (""); + yyerrok; + } + ; + +/* DSPMAC. */ + +asm_1: + +/* DYA operation */ +/*ALU operations*/ + + | ADD REG COMMA REG COMMA REG + { + if (IS_DREG ($2) && IS_DREG ($4) && IS_DREG ($6)) + { + notethat ("ADD : dest_reg = src_reg1 + src_reg2\n"); + $$ = CMD_ALUR ($2, $4, $6, ALU_SEL_ADD); + } + else + return yyerror ("Register mismatch"); + } + | ADD REG COMMA REG COMMA expr + { + notethat ("ADD : dest_reg = src_reg1 + imm\n"); + if (IS_DREG ($2) && IS_DREG ($4)) + { + notethat ("ADD : dest_reg = src_reg1 + imm\n"); + $$ = CMD_ALUI ($2, $4, $6, ALU_SEL_ADD); + } + else + return yyerror ("Register mismatch"); + } + | SUB REG COMMA REG COMMA REG + { + if (IS_DREG ($2) && IS_DREG ($4) && IS_DREG ($6)) + { + notethat ("SUB : dest_reg = src_reg1 + src_reg2\n"); + $$ = CMD_ALUR ($2, $4, $6, ALU_SEL_SUB); + } + else + return yyerror ("Register mismatch"); + } + | SUB REG COMMA REG COMMA expr + { + if (IS_DREG ($2) && IS_DREG ($4)) + { + notethat ("SUM : dest_reg = src_reg1 + imm\n"); + $$ = CMD_ALUI ($2, $4, $6, ALU_SEL_SUB); + } + else + return yyerror ("Register mismatch"); + } + | AND REG COMMA REG COMMA REG + { + if (IS_DREG ($2) && IS_DREG ($4) && IS_DREG ($6)) + { + notethat ("AND : dest_reg = src_reg1 + src_reg2\n"); + $$ = CMD_ALUR ($2, $4, $6, ALU_SEL_AND); + } + else + return yyerror ("Register mismatch"); + } + | AND REG COMMA REG COMMA expr + { + if (IS_DREG ($2) && IS_DREG ($4)) + { + notethat ("AND : dest_reg = src_reg1 + imm\n"); + $$ = CMD_ALUI ($2, $4, $6, ALU_SEL_AND); + } + else + return yyerror ("Register mismatch"); + } + | OR REG COMMA REG COMMA REG + { + if (IS_DREG ($2) && IS_DREG ($4) && IS_DREG ($6)) + { + notethat ("OR : dest_reg = src_reg1 | src_reg2\n"); + $$ = CMD_ALUR ($2, $4, $6, ALU_SEL_OR); + } + else + return yyerror ("Register mismatch"); + } + | OR REG COMMA REG COMMA expr + { + if (IS_DREG ($2) && IS_DREG ($4)) + { + notethat ("OR : dest_reg = src_reg1 | imm\n"); + $$ = CMD_ALUI ($2, $4, $6, ALU_SEL_OR); + } + else + return yyerror ("Register mismatch"); + } + | RSH REG COMMA REG COMMA REG + { + if (IS_DREG ($2) && IS_DREG ($4) && IS_DREG ($6)) + { + notethat ("RSH : dest_reg = src_reg1 >> src_reg2\n"); + $$ = CMD_ALUR ($2, $4, $6, ALU_SEL_RSH); + } + else + return yyerror ("Register mismatch"); + } + | RSH REG COMMA REG COMMA expr + { + if (IS_DREG ($2) && IS_DREG ($4)) + { + notethat ("RSH : dest_reg = src_reg1 >> imm\n"); + $$ = CMD_ALUI ($2, $4, $6, ALU_SEL_RSH); + } + else + return yyerror ("Register mismatch"); + } + | LSH REG COMMA REG COMMA REG + { + if (IS_DREG ($2) && IS_DREG ($4) && IS_DREG ($6)) + { + notethat ("LSH : dest_reg = src_reg1 << src_reg2\n"); + $$ = CMD_ALUR ($2, $4, $6, ALU_SEL_LSH); + } + else + return yyerror ("Register mismatch"); + } + | LSH REG COMMA REG COMMA expr + { + if (IS_DREG ($2) && IS_DREG ($4)) + { + notethat ("LSH : dest_reg = src_reg1 << imm\n"); + $$ = CMD_ALUI ($2, $4, $6, ALU_SEL_LSH); + } + else + return yyerror ("Register mismatch"); + } + | MOVE REG COMMA REG + { + if (IS_DREG ($2) && IS_DREG ($4)) + { + notethat ("LSH : dest_reg = src_reg1\n"); + $$ = CMD_ALUR ($2, $4, $4, ALU_SEL_MOV); + } + else + return yyerror ("Register mismatch"); + } + | MOVE REG COMMA expr + { + if (IS_DREG ($2)) + { + notethat ("MOVE : dest_reg = imm\n"); + $$ = CMD_ALUI_DIR ($2, $4, ALU_SEL_MOV); + } + else + return yyerror ("Register mismatch"); + } + | STAGE_RST + { + notethat ("STAGE_RST \n"); + $$ = CMD_STAGE_RST(); + } + | STAGE_INC expr + { + notethat ("STAGE_INC \n"); + $$ = CMD_STAGE(ALU_SEL_SINC, $2); + } + | STAGE_DEC expr + { + notethat ("STAGE_DEC \n"); + $$ = CMD_STAGE(ALU_SEL_SDEC, $2); + } + + +/*=================================================================================================*/ + | JUMP REG + { + if (IS_DREG ($2)) + { + notethat ("JUMP_R : dest_addr, condition\n"); + $$ = JUMP_R ($2, 0); + } + else + { + return yyerror ("Register mismatch"); + } + } + | JUMP REG COMMA branchmod + { + if (IS_DREG ($2)) + { + notethat ("JUMP_R : dest_addr, condition\n"); + $$ = JUMP_R ($2, $4.r0); + } + else + { + return yyerror ("Register mismatch"); + } + } + | JUMP expr + { + if (IS_IMM ($2, 11)) + { + notethat ("JUMP_I : dest_addr, condition\n"); + $$ = JUMP_I ($2, 0); + } + else + { + return yyerror ("Register mismatch"); + } + } + | JUMP expr COMMA branchmod + { + if (IS_IMM ($2, 11)) + { + notethat ("JUMP : dest_addr, condition\n"); + $$ = JUMP_I ($2, $4.r0); + } + else + { + return yyerror ("Register mismatch"); + } + } + | JUMPR expr COMMA expr COMMA branchrel + { + if (IS_UIMM ($2, 8) && IS_IMM ($4, 16)) + { + notethat ("JUMPR : rel_addr, threshold, condition\n"); + $$ = CMD_JUMPR($2, $4, $6.r0); + } + else + { + return yyerror ("Jump adress is to far"); + } + } + | JUMPS expr COMMA expr COMMA branchrels + { + if (IS_UIMM ($2, 8) && IS_IMM ($4, 16)) + { + notethat ("JUMPS : rel_addr, threshold, condition\n"); + $$ = CMD_JUMPS($2, $4, $6.r0); + } + else + { + return yyerror ("Jump adress is to far"); + } + } + | ST32 REG COMMA REG COMMA expr COMMA expr + { + if (IS_UIMM ($6, 11) && IS_DREG ($2) && IS_DREG ($4)) + { + notethat ("ST32 : Rdst, Rsrs, offset, label; Mem [ Rsrc + offset ] = { PC[ 10 : 0 ], 3’b0, label[ 1 : 0 ], Rdst[ 15 : 0 ] }\n"); + $$ = WR_MEM_ST32($2, $4, $6, $8); + } + else + { + return yyerror ("Register mismatch"); + } + } + | STI32 REG COMMA REG COMMA expr + { + if (IS_UIMM ($6, 2) && IS_DREG ($2) && IS_DREG ($4)) + { + notethat ("STI32 : Rdst, Rsrs, label (autoincrement offset); Mem [ Rsrc + offset ] = { PC[ 10 : 0 ], 3’b0, label[ 1 : 0 ], Rdst[ 15 : 0 ] }\n"); + $$ = WR_MEM_STI32($2, $4, $6); + } + else + { + return yyerror ("Register mismatch"); + } + } + | ST REG COMMA REG COMMA expr + { + if (IS_UIMM ($6, 11) && IS_DREG ($2) && IS_DREG ($4)) + { + notethat ("STL : Rdst, Rsrs, offset, MEM[Rsrc + offset] = Rdst\n"); + $$ = WR_MEM_STLR(0, $2, $4, $6); + } + else + { + return yyerror ("Register mismatch"); + } + } + | STL REG COMMA REG COMMA expr + { + if (IS_UIMM ($6, 11) && IS_DREG ($2) && IS_DREG ($4)) + { + notethat ("STL : Rdst, Rsrs, offset, MEM[Rsrc + offset] = Rdst\n"); + $$ = WR_MEM_STLR(0, $2, $4, $6); + } + else + { + return yyerror ("Register mismatch"); + } + } + | STH REG COMMA REG COMMA expr + { + if (IS_UIMM ($6, 11) && IS_DREG ($2) && IS_DREG ($4)) + { + notethat ("STH : Rdst, Rsrs, offset, MEM[Rsrc + offset] = Rdst\n"); + $$ = WR_MEM_STLR(1, $2, $4, $6); + } + else + { + return yyerror ("Register mismatch"); + } + } + | STL REG COMMA REG COMMA expr COMMA expr + { + if (IS_UIMM ($6, 11) && IS_DREG ($2) && IS_DREG ($4)) + { + notethat ("STL : Rdst, Rsrs, offset,label; Mem [ Rsrs + offset ] = { label[ 1 : 0 ], Rdst[ 13 : 0 ] } (depends on H/L bit)\n"); + $$ = WR_MEM_ST_L(0, $2, $4, $6, $8); + } + else + { + return yyerror ("Register mismatch"); + } + } + | STH REG COMMA REG COMMA expr COMMA expr + { + if (IS_UIMM ($6, 11) && IS_DREG ($2) && IS_DREG ($4)) + { + notethat ("STH : Rdst, Rsrs, offset,label; Mem [ Rsrs + offset ] = { label[ 1 : 0 ], Rdst[ 13 : 0 ] } (depends on H/L bit)\n"); + $$ = WR_MEM_ST_L(1, $2, $4, $6, $8); + } + else + { + return yyerror ("Register mismatch"); + } + } + | STI REG COMMA REG COMMA expr + { + if (IS_DREG ($2) && IS_DREG ($4)) + { + notethat ("STI : Rdst, Rsrs,label; Mem [ Rsrs + offset ] = { label[ 1 : 0 ], Rdst[ 13 : 0 ] } (depends on H/L bit)\n"); + $$ = WR_MEM_STI_L($2, $4, $6); + } + else + { + return yyerror ("Register mismatch"); + } + } + | STI REG COMMA REG + { + if (IS_DREG ($2) && IS_DREG ($4)) + { + notethat ("STI : Rdst, Rsrs; Mem [ Rsrs + offset ] = Rdst } (depends on H/L bit)\n"); + $$ = WR_MEM_STI($2, $4); + } + else + { + return yyerror ("Register mismatch"); + } + } + | STO expr + { + if (IS_UIMM ($2, 11)) + { + notethat ("STO Offset; Offset = value }\n"); + $$ = WR_MEM_STO($2); + } + else + { + return yyerror ("Offset mismatch"); + } + } + | LD REG COMMA REG COMMA expr + { + if (IS_UIMM ($6, 11) && IS_DREG ($2) && IS_DREG ($4)) + { + notethat ("LD : Rdst, Rsrs, offset, Rdst = MEM[Rsrc + offset]\n"); + $$ = RD_MEM_ADDR(0, $2, $4, $6); + } + else + { + return yyerror ("Register mismatch"); + } + } + | LDL REG COMMA REG COMMA expr + { + if (IS_UIMM ($6, 11) && IS_DREG ($2) && IS_DREG ($4)) + { + notethat ("LDL : Rdst, Rsrs, offset, Rdst = MEM[Rsrc + offset]\n"); + $$ = RD_MEM_ADDR(0, $2, $4, $6); + } + else + { + return yyerror ("Register mismatch"); + } + } + | LDH REG COMMA REG COMMA expr + { + if (IS_UIMM ($6, 11) && IS_DREG ($2) && IS_DREG ($4)) + { + notethat ("LDH : Rdst, Rsrs, offset, Rdst = MEM[Rsrc + offset]\n"); + $$ = RD_MEM_ADDR(1, $2, $4, $6); + } + else + { + return yyerror ("Register mismatch"); + } + } + | NOP + { + notethat ("ProgCtrl: NOP\n"); + $$ = PROGCTRL (0, 0); + } + | HALT + { + notethat ("ProgCtrl: END\n"); + $$ = CMD_HALT (); + } + | WAKE + { + notethat ("ProgCtrl: CMD_WAKEUP\n"); + $$ = CMD_WAKEUP(NULL); + } + | SLEEP expr + { + notethat ("ProgCtrl: SLEEP\n"); + $$ = CMD_SLEEP($2); + } + | TSENS REG COMMA expr + { + if (IS_DREG ($2)) + { + notethat ("ProgCtrl: TSENS\n"); + $$ = CMD_TSENS($2, $4); + } + else + { + return yyerror ("Register mismatch"); + } + } + | ADC REG COMMA expr COMMA expr + { + if (IS_DREG ($2)) + { + notethat ("ProgCtrl: ADC \n"); + $$ = CMD_ADC($2, $4, $6); + } + else + { + return yyerror ("Register mismatch"); + } + } + | ADC REG COMMA expr COMMA expr COMMA expr + { + if (IS_DREG ($2)) + { + notethat ("ProgCtrl: ADC \n"); + $$ = CMD_ADC($2, $4, $6); + } + else + { + return yyerror ("Register mismatch"); + } + } + | WAIT expr + { + notethat ("ProgCtrl: WAIT count\n"); + $$ = CMD_WAIT($2); + } + | REG_RD expr COMMA expr COMMA expr + { + notethat ("ProgCtrl: REG_RD addr, high, low, \n"); + $$ = CMD_REG_RD($2, $4, $6); + } + | REG_WR expr COMMA expr COMMA expr COMMA expr + { + notethat ("ProgCtrl: REG_WR addr, high, low, value\n"); + $$ = CMD_REG_WR($2, $4, $6, $8); + } + | I2C_RD expr COMMA expr COMMA expr COMMA expr + { + notethat ("ProgCtrl: I2C_RD - i2c_addr, high, low, i2c_sel\n"); + $$ = CMD_I2C_RD($2, $4, $6, $8); + } + | I2C_WR expr COMMA expr COMMA expr COMMA expr COMMA expr + { + notethat ("ProgCtrl: I2C_WR - i2c_addr, value, high, low, i2c_sel\n"); + $$ = CMD_I2C_WR($2, $6, $8, $10, $4); + } + /* --------------------------------------------------------------------------------------------------*/ +; + +/* AUX RULES. */ +branchmod: + EQ + { + $$.r0 = 1; + } + | OV + { + $$.r0 = 2; + } + ; + +branchrel: + EQ + { + $$.r0 = 2; + } + | GT + { + $$.r0 = 1; + } + | LT + { + $$.r0 = 0; + } + ; + +branchrels: + EQ + { + $$.r0 = 4; + } + | GT + { + $$.r0 = 3; + } + | LT + { + $$.r0 = 1; + } + | LE + { + $$.r0 = 5; + } + | GE + { + $$.r0 = 7; + } + ; + +searchmod: + GE + { + $$.r0 = 1; + } + | GT + { + $$.r0 = 2; + } + | LE + { + $$.r0 = 3; + } + | LT + { + $$.r0 = 4; + } + | OV + { + $$.r0 = 5; + } + | EQ + { + $$.r0 = 6; + } + ; + + +/* Expressions and Symbols. */ + +symbol: SYMBOL + { + Expr_Node_Value val; + val.s_value = S_GET_NAME($1); + $$ = Expr_Node_Create (Expr_Node_Reloc, val, NULL, NULL); + } + ; + +any_gotrel: + GOT + { $$ = BFD_RELOC_ESP32S2ULP_GOT; } + | GOT17M4 + { $$ = BFD_RELOC_ESP32S2ULP_GOT17M4; } + | FUNCDESC_GOT17M4 + { $$ = BFD_RELOC_ESP32S2ULP_FUNCDESC_GOT17M4; } + ; + +got: symbol AT any_gotrel + { + Expr_Node_Value val; + val.i_value = $3; + $$ = Expr_Node_Create (Expr_Node_GOT_Reloc, val, $1, NULL); + } + ; + +got_or_expr: got + { + $$ = $1; + } + | expr + { + $$ = $1; + } + ; + +eterm: NUMBER + { + Expr_Node_Value val; + val.i_value = $1; + $$ = Expr_Node_Create (Expr_Node_Constant, val, NULL, NULL); + } + | symbol + { + $$ = $1; + } + | LPAREN expr_1 RPAREN + { + $$ = $2; + } + | TILDA expr_1 + { + $$ = unary (Expr_Op_Type_COMP, $2); + } + | MINUS expr_1 %prec TILDA + { + $$ = unary (Expr_Op_Type_NEG, $2); + } + ; + +expr: expr_1 + { + $$ = $1; + } + ; + +expr_1: expr_1 STAR expr_1 + { + $$ = binary (Expr_Op_Type_Mult, $1, $3); + } + | expr_1 SLASH expr_1 + { + $$ = binary (Expr_Op_Type_Div, $1, $3); + } + | expr_1 PERCENT expr_1 + { + $$ = binary (Expr_Op_Type_Mod, $1, $3); + } + | expr_1 PLUS expr_1 + { + $$ = binary (Expr_Op_Type_Add, $1, $3); + } + | expr_1 MINUS expr_1 + { + $$ = binary (Expr_Op_Type_Sub, $1, $3); + } + | expr_1 LESS_LESS expr_1 + { + $$ = binary (Expr_Op_Type_Lshift, $1, $3); + } + | expr_1 GREATER_GREATER expr_1 + { + $$ = binary (Expr_Op_Type_Rshift, $1, $3); + } + | expr_1 AMPERSAND expr_1 + { + $$ = binary (Expr_Op_Type_BAND, $1, $3); + } + | expr_1 CARET expr_1 + { + $$ = binary (Expr_Op_Type_LOR, $1, $3); + } + | expr_1 BAR expr_1 + { + $$ = binary (Expr_Op_Type_BOR, $1, $3); + } + | eterm + { + $$ = $1; + } + ; + + +%% + +EXPR_T mkexpr(int x, SYMBOL_T s) +{ + EXPR_T e = XNEW(struct expression_cell); + e->value = x; + EXPR_SYMBOL(e) = s; + return e; +} + +static int value_match(Expr_Node *exp, int sz, int sign, int mul, int issigned) +{ + int umax = (1 << sz) - 1; + int min = -(1 << (sz - 1)); + int max = (1 << (sz - 1)) - 1; + + int v = (EXPR_VALUE(exp)) & 0xffffffff; + + if ((v % mul) != 0) + { + error("%s:%d: Value Error -- Must align to %d\n", __FILE__, __LINE__, mul); + return 0; + } + + v /= mul; + + if (sign) + v = -v; + + if (issigned) + { + if (v >= min && v <= max) return 1; + +#ifdef DEBUG + fprintf(stderr, "signed value %lx out of range\n", v * mul); +#endif + return 0; + } + if (v <= umax && v >= 0) + return 1; +#ifdef DEBUG + fprintf(stderr, "unsigned value %lx out of range\n", v * mul); +#endif + return 0; +} + +/* Return the expression structure that allows symbol operations. +If the left and right children are constants, do the operation. */ +static Expr_Node* binary(Expr_Op_Type op, Expr_Node *x, Expr_Node *y) +{ + Expr_Node_Value val; + + if (x->type == Expr_Node_Constant && y->type == Expr_Node_Constant) + { + switch (op) + { + case Expr_Op_Type_Add: + x->value.i_value += y->value.i_value; + break; + case Expr_Op_Type_Sub: + x->value.i_value -= y->value.i_value; + break; + case Expr_Op_Type_Mult: + x->value.i_value *= y->value.i_value; + break; + case Expr_Op_Type_Div: + if (y->value.i_value == 0) + error("Illegal Expression: Division by zero."); + else + x->value.i_value /= y->value.i_value; + break; + case Expr_Op_Type_Mod: + x->value.i_value %= y->value.i_value; + break; + case Expr_Op_Type_Lshift: + x->value.i_value <<= y->value.i_value; + break; + case Expr_Op_Type_Rshift: + x->value.i_value >>= y->value.i_value; + break; + case Expr_Op_Type_BAND: + x->value.i_value &= y->value.i_value; + break; + case Expr_Op_Type_BOR: + x->value.i_value |= y->value.i_value; + break; + case Expr_Op_Type_BXOR: + x->value.i_value ^= y->value.i_value; + break; + case Expr_Op_Type_LAND: + x->value.i_value = x->value.i_value && y->value.i_value; + break; + case Expr_Op_Type_LOR: + x->value.i_value = x->value.i_value || y->value.i_value; + break; + + default: + error("%s:%d: Internal assembler error\n", __FILE__, __LINE__); + } + return x; + } + /* Canonicalize order to EXPR OP CONSTANT. */ + if (x->type == Expr_Node_Constant) + { + Expr_Node *t = x; + x = y; + y = t; + } + /* Canonicalize subtraction of const to addition of negated const. */ + if (op == Expr_Op_Type_Sub && y->type == Expr_Node_Constant) + { + op = Expr_Op_Type_Add; + y->value.i_value = -y->value.i_value; + } + if (y->type == Expr_Node_Constant && x->type == Expr_Node_Binop + && x->Right_Child->type == Expr_Node_Constant) + { + if (op == x->value.op_value && x->value.op_value == Expr_Op_Type_Add) + { + x->Right_Child->value.i_value += y->value.i_value; + return x; + } + } + + /* Create a new expression structure. */ + val.op_value = op; + return Expr_Node_Create(Expr_Node_Binop, val, x, y); +} + +static Expr_Node* unary(Expr_Op_Type op, Expr_Node *x) +{ + if (x->type == Expr_Node_Constant) + { + switch (op) + { + case Expr_Op_Type_NEG: + x->value.i_value = -x->value.i_value; + break; + case Expr_Op_Type_COMP: + x->value.i_value = ~x->value.i_value; + break; + default: + error("%s:%d: Internal assembler error\n", __FILE__, __LINE__); + } + return x; + } + else + { + /* Create a new expression structure. */ + Expr_Node_Value val; + val.op_value = op; + return Expr_Node_Create(Expr_Node_Unop, val, x, NULL); + } +} + +int debug_codeselection = 0; +static void +notethat(const char *format, ...) +{ + va_list ap; + va_start(ap, format); + if (debug_codeselection) + { + vfprintf(errorf, format, ap); + } + va_end(ap); +} + +#ifdef TEST +main(int argc, char **argv) +{ + yyparse(); +} +#endif + diff --git a/gas/config/tc-esp32s2ulp.c b/gas/config/tc-esp32s2ulp.c new file mode 100644 index 00000000000..8cc05673293 --- /dev/null +++ b/gas/config/tc-esp32s2ulp.c @@ -0,0 +1,1083 @@ +/* tc-esp32s2ulp.c +ESP32S2ULP GNU Assembler + +Copyright (c) 2016-2017 Espressif Systems (Shanghai) PTE LTD. + +based on Copyright (C) 2005-2017 Free Software Foundation, Inc. + +This file is part of GAS, the GNU Assembler. + +GAS is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GAS is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GAS; see the file COPYING. If not, write to the Free +Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA +02110-1301, USA. */ + +#include "as.h" +#include "struc-symbol.h" +#include "esp32s2ulp-defs.h" +#include "obstack.h" +#include "safe-ctype.h" +#ifdef OBJ_ELF +#include "dwarf2dbg.h" +#endif +#include "elf/common.h" +#include "elf/esp32s2ulp.h" +/* Global variables. */ +struct esp32s2ulp_insn *insn; +#include "tc-esp32ulp_common.c" + +#ifdef OBJ_FDPIC_ELF +# define DEFAULT_FDPIC EF_ESP32S2ULP_FDPIC +#else +# define DEFAULT_FDPIC 0 +#endif + +static flagword esp32s2ulp_flags = DEFAULT_FLAGS | DEFAULT_FDPIC; + +static void +esp32s2ulp_s_bss(int ignore ATTRIBUTE_UNUSED) +{ + int temp; + + temp = get_absolute_expression(); + subseg_set(bss_section, (subsegT)temp); + demand_empty_rest_of_line(); +} + +const pseudo_typeS md_pseudo_table[] = { + { "align", s_align_bytes, 0 }, + { "byte2", cons, 2 }, + { "byte4", cons, 4 }, + { "db", cons, 1 }, + { "dd", cons, 4 }, + { "dw", cons, 2 }, + { "p", s_ignore, 0 }, + { "pdata", s_ignore, 0 }, + { "var", s_ignore, 0 }, + { "bss", esp32s2ulp_s_bss, 0 }, + { 0, 0, 0 } +}; + +unsigned int esp32s2ulp_anomaly_checks = 0; + +/* Perform machine-specific initializations. */ +void +md_begin(void) +{ + /* Set the ELF flags if desired. */ + if (esp32s2ulp_flags) + bfd_set_private_flags(stdoutput, esp32s2ulp_flags); + + /* Set the default machine type. */ + if (!bfd_set_arch_mach(stdoutput, bfd_arch_esp32s2ulp, 0)) + as_warn(_("Could not set architecture and machine.")); + + /* Ensure that lines can begin with '(', for multiple + register stack pops. */ + lex_type['('] = LEX_BEGIN_NAME; + +#ifdef OBJ_ELF + record_alignment(text_section, 2); + record_alignment(data_section, 2); + record_alignment(bss_section, 2); +#endif + + errorf = stderr; + obstack_init(&mempool); + +#ifdef DEBUG + extern int debug_codeselection; + debug_codeselection = 1; +#endif + + last_insn_size = 0; +} + +void +md_apply_fix(fixS *fixP, valueT *valueP, segT seg ATTRIBUTE_UNUSED) +{ + char *where = fixP->fx_frag->fr_literal + fixP->fx_where; + + long value = *valueP; + //DEBUG_TRACE("dya_pass - md_apply_fix: fixP->fx_r_type=%i, value=%i, fixP->fx_where=%i\n", fixP->fx_r_type, (unsigned int)value, (int)fixP->fx_where); + switch (fixP->fx_r_type) + { + case BFD_RELOC_ESP32S2ULP_16_IMM: + if (fixP->fx_addsy != NULL)// relocation will be done not in linker + { + asymbol *sym = symbol_get_bfdsym(fixP->fx_addsy); + int force_reloc = S_FORCE_RELOC(fixP->fx_addsy, 1); + //printf("force_reloc = %i \n", force_reloc); + if (force_reloc != 0) if (sym->section->flags != 0) value = value >> 2; + } + if ((value < 0) || (value > 2047)) + as_bad_where(fixP->fx_file, fixP->fx_line, _("rel too far BFD_RELOC_16")); + if ((value%4) != 0) + as_bad_where(fixP->fx_file, fixP->fx_line, _("Esp32S2Ulp is 32-bit addressing processor. Relative jump value must be divided by 4.")); + + //value = value << 2; + md_number_to_chars(where, value, 2); + break; + + case BFD_RELOC_ESP32S2ULP_JUMPR: + if (value < -0x8000 || value > 0x7fff) + as_bad_where(fixP->fx_file, fixP->fx_line, _("rel too far BFD_RELOC_ESP32S2ULP_JUMPR")); + //value = value << 2; + if (fixP->fx_addsy != NULL)// relocation will be done not in linker + { + asymbol *sym = symbol_get_bfdsym(fixP->fx_addsy); + int force_reloc = S_FORCE_RELOC(fixP->fx_addsy, 1); + if (force_reloc != 0) if (sym->section->flags != 0) value = value >> 2; + } + unsigned int temp_val = 0; + memcpy(&temp_val, where, 4); + temp_val &= ~(0xff << 18); + temp_val |= value; + memcpy(where, &temp_val, 4); + //DEBUG_TRACE("dya_pass - md_apply_fix:BFD_RELOC_ESP32S2ULP_JUMPR temp_val=%08x where[0]=%02x, where[1]=%02x, where[2]=%02x, where[3]=%02x, \n", (unsigned int)temp_val, (unsigned int)where[0], (int)where[1], (int)where[2], (int)where[3]); + //md_number_to_chars(where, value, 0); + break; + case BFD_RELOC_ESP32S2ULP_16_LOAD: + if (value > 0xffff) + as_bad_where(fixP->fx_file, fixP->fx_line, _("rel too far BFD_LOAD_16")); + //value = value << 2; + temp_val = 0; + memcpy(&temp_val, where, 4); + temp_val &= ~(0xffff); + temp_val |= value; + memcpy(where, &temp_val, 4); + //DEBUG_TRACE("dya_pass - md_apply_fix:BFD_RELOC_ESP32S2ULP_16_LOAD temp_val=%08x where[0]=%02x, where[1]=%02x, where[2]=%02x, where[3]=%02x, \n", (unsigned int)temp_val, (unsigned int)where[0], (int)where[1], (int)where[2], (int)where[3]); + //md_number_to_chars(where, value, 0); + break; + + case BFD_RELOC_ESP32S2ULP_WR_MEM: + value = value >> 2; + if ((value > 2047) || (value < 0)) + as_bad_where(fixP->fx_file, fixP->fx_line, _("rel too far BFD_WR_MEM")); + temp_val = 0; + memcpy(&temp_val, where, 4); + temp_val &= ~((0x7ff << 10)); + temp_val |= (value << 10); + memcpy(where, &temp_val, 4); + //DEBUG_TRACE("dya_pass - md_apply_fix:BFD_RELOC_ESP32S2ULP_WR_MEM temp_val=%08x where[0]=%02x, where[1]=%02x, where[2]=%02x, where[3]=%02x, \n", (unsigned int)temp_val, (unsigned int)where[0], (int)where[1], (int)where[2], (int)where[3]); + //md_number_to_chars(where, value, 0); + break; + case BFD_RELOC_ESP32S2ULP_WR_MEM_LABEL: + if ((value > 3) || (value < 0)) + as_bad_where(fixP->fx_file, fixP->fx_line, _("rel too far BFD_WR_MEM_LABEL")); + temp_val = 0; + memcpy(&temp_val, where, 4); + temp_val &= ~((0x3 << 4)); + temp_val |= (value << 4); + memcpy(where, &temp_val, 4); + //DEBUG_TRACE("dya_pass - md_apply_fix:BFD_RELOC_ESP32S2ULP_WR_MEM_LABEL temp_val=%08x where[0]=%02x, where[1]=%02x, where[2]=%02x, where[3]=%02x, \n", (unsigned int)temp_val, (unsigned int)where[0], (int)where[1], (int)where[2], (int)where[3]); + //md_number_to_chars(where, value, 0); + break; + + case BFD_RELOC_ESP32S2ULP_ALUI: + if ((value > 0xffff) || (value < -0xffff)) + as_bad_where(fixP->fx_file, fixP->fx_line, _("rel too far BFD_ALUI")); + //value = 0x00ffff; // for tests only + if (fixP->fx_addsy != NULL)// relocation will be done not in linker + { + asymbol *sym = symbol_get_bfdsym(fixP->fx_addsy); + if (sym->section->flags != 0) value = value >> 2; + } + temp_val = 0; + memcpy(&temp_val, where, 4); + temp_val &= ~((0xffff << 4)); + temp_val |= (value << 4); + memcpy(where, &temp_val, 4); + + //if (fixP->fx_addsy != NULL) + //{ + // asymbol *sym = symbol_get_bfdsym(fixP->fx_addsy); + // DEBUG_TRACE("dya_pass - md_apply_fix:BFD_RELOC_ESP32S2ULP_ALUI temp_val=%08x value=%08x, flags=%08x, fixP=%08x, done=%08x, fixP->fx_addsy=%08x, flags=%08x, name=%s\n", + // (unsigned int)temp_val, + // (unsigned int)value, (unsigned int)seg->flags, *(unsigned int*)fixP, (unsigned int)fixP->fx_done, *(unsigned int*)fixP->fx_addsy, sym->section->flags, sym->section->name); + //} + //else + //{ + // DEBUG_TRACE("dya_pass - md_apply_fix:BFD_RELOC_ESP32S2ULP_ALUI temp_val=%08x value=%08x, flags=%08x, fixP=%08x, done=%08x, fixP->fx_addsy=%08x\n", (unsigned int)temp_val, (unsigned int)value, (unsigned int)seg->flags, *(unsigned int*)fixP, (unsigned int)fixP->fx_done, 0xdead); + //} + //md_number_to_chars(where, value, 0); + break; + + case BFD_RELOC_ESP32S2ULP_WAIT: + if ((value > 0xffff) || (value < 0)) + as_bad_where(fixP->fx_file, fixP->fx_line, _("rel too far BFD_WAIT")); + //value = value << 2; + temp_val = 0; + memcpy(&temp_val, where, 4); + temp_val &= ~((0xffff << 0)); + temp_val |= (value << 0); + memcpy(where, &temp_val, 4); + //DEBUG_TRACE("dya_pass - md_apply_fix:BFD_RELOC_ESP32S2ULP_WAIT temp_val=%08x value=%08x\n", (unsigned int)temp_val, (unsigned int)value); + //md_number_to_chars(where, value, 0); + break; + + case BFD_RELOC_ESP32S2ULP_TSENS_CYCLE: + if ((value > 0xfff) || (value < 0)) + as_bad_where(fixP->fx_file, fixP->fx_line, _("rel too far BFD_TSENS_CYLE")); + //value = value << 2; + temp_val = 0; + memcpy(&temp_val, where, 4); + temp_val &= ~((0xfff << 16)); + temp_val |= (value << 16); + memcpy(where, &temp_val, 4); + //DEBUG_TRACE("dya_pass - md_apply_fix:BFD_RELOC_ESP32S2ULP_TSENS_CYCLE temp_val=%08x value=%08x\n", (unsigned int)temp_val, (unsigned int)value); + //md_number_to_chars(where, value, 0); + break; + + case BFD_RELOC_ESP32S2ULP_TSENS_DELAY: + if ((value > 0x3fff) || (value < 0)) + as_bad_where(fixP->fx_file, fixP->fx_line, _("rel too far BFD_TSENS_DELAY")); + //value = value << 2; + temp_val = 0; + memcpy(&temp_val, where, 4); + temp_val &= ~((0x3fff << 2)); + temp_val |= (value << 2); + memcpy(where, &temp_val, 4); + //DEBUG_TRACE("dya_pass - md_apply_fix:BFD_RELOC_ESP32S2ULP_TSENS_DELAY temp_val=%08x value=%08x\n", (unsigned int)temp_val, (unsigned int)value); + //md_number_to_chars(where, value, 0); + break; + + case BFD_RELOC_ESP32S2ULP_WAKE: + if ((value > 1) || (value < 0)) + as_bad_where(fixP->fx_file, fixP->fx_line, _("rel too far BFD_WAKE")); + //value = value << 2; + temp_val = 0; + memcpy(&temp_val, where, 4); + temp_val &= ~((0x1 << 0)); + temp_val |= (value << 0); + memcpy(where, &temp_val, 4); + //DEBUG_TRACE("dya_pass - md_apply_fix:BFD_RELOC_ESP32S2ULP_WAKE temp_val=%08x value=%08x\n", (unsigned int)temp_val, (unsigned int)value); + //md_number_to_chars(where, value, 0); + break; + + case BFD_RELOC_ESP32S2ULP_SLEEP: + if ((value > 0xffff) || (value < 0)) + as_bad_where(fixP->fx_file, fixP->fx_line, _("rel too far BFD_SLEEP")); + //value = value << 2; + temp_val = 0; + memcpy(&temp_val, where, 4); + temp_val &= ~((0xffff << 0)); + temp_val |= (value << 0); + memcpy(where, &temp_val, 4); + //DEBUG_TRACE("dya_pass - md_apply_fix:BFD_RELOC_ESP32S2ULP_SLEEP temp_val=%08x value=%08x\n", (unsigned int)temp_val, (unsigned int)value); + //md_number_to_chars(where, value, 0); + break; + + case BFD_RELOC_ESP32S2ULP_ADC_CYCLE: + if ((value > 0xffff) || (value < 0)) + as_bad_where(fixP->fx_file, fixP->fx_line, _("rel too far BFD_ADC_CYCLE")); + //value = value << 2; + temp_val = 0; + memcpy(&temp_val, where, 4); + temp_val &= ~((0xffff << 8)); + temp_val |= (value << 8); + memcpy(where, &temp_val, 4); + //DEBUG_TRACE("dya_pass - md_apply_fix:BFD_RELOC_ESP32S2ULP_ADC_CYCLE temp_val=%08x value=%08x\n", (unsigned int)temp_val, (unsigned int)value); + //md_number_to_chars(where, value, 0); + break; + + case BFD_RELOC_ESP32S2ULP_ADC_SEL: + if ((value > 0x01) || (value < 0x00)) + as_bad_where(fixP->fx_file, fixP->fx_line, _("rel too far BFD_ADC_SEL")); + //value = value << 2; + temp_val = 0; + memcpy(&temp_val, where, 4); + temp_val &= ~((0x1 << 6)); + temp_val |= (value << 6); + memcpy(where, &temp_val, 4); + //DEBUG_TRACE("dya_pass - md_apply_fix:BFD_RELOC_ESP32S2ULP_ADC_SEL temp_val=%08x value=%08x\n", (unsigned int)temp_val, (unsigned int)value); + //md_number_to_chars(where, value, 0); + break; + + case BFD_RELOC_ESP32S2ULP_ADC_MUX: + if ((value > 0x0f) || (value < 0)) + as_bad_where(fixP->fx_file, fixP->fx_line, _("rel too far BFD_ADC_MUX")); + //value = value << 2; + temp_val = 0; + memcpy(&temp_val, where, 4); + temp_val &= ~((0x0f << 2)); + temp_val |= (value << 2); + memcpy(where, &temp_val, 4); + //DEBUG_TRACE("dya_pass - md_apply_fix:BFD_RELOC_ESP32S2ULP_ADC_MUX temp_val=%08x value=%08x\n", (unsigned int)temp_val, (unsigned int)value); + //md_number_to_chars(where, value, 0); + break; + + case BFD_RELOC_ESP32S2ULP_STAGE: + if (value > 0xff) + as_bad_where(fixP->fx_file, fixP->fx_line, _("rel too far BFD_STAGE")); + //value = value << 2; + temp_val = 0; + memcpy(&temp_val, where, 4); + temp_val &= ~((0xff << 4)); + temp_val |= (value << 4); + memcpy(where, &temp_val, 4); + //DEBUG_TRACE("dya_pass - md_apply_fix:BFD_RELOC_ESP32S2ULP_STAGE temp_val=%08x value=%08x\n", (unsigned int)temp_val, (unsigned int)value); + //md_number_to_chars(where, value, 0); + break; + + case BFD_RELOC_ESP32S2ULP_JUMPR_STEP: + if (value < -0x8000 || value > 0x7fff) + as_bad_where(fixP->fx_file, fixP->fx_line, _("rel too far BFD_RELOC_ESP32S2ULP_JUMPR_STEP")); + value = value >> 2; + temp_val = 0; + memcpy(&temp_val, where, 4); + if (value >= 0) + { + temp_val |= (value & 0x7f) << 18; + } + else + { + value = -value; + temp_val |= (value & 0x7f) << 18; + temp_val |= 0x80 << 18; + } + memcpy(where, &temp_val, 4); + //DEBUG_TRACE("dya_pass - md_apply_fix:BFD_RELOC_ESP32S2ULP_JUMPR temp_val=%08x where[0]=%02x, where[1]=%02x, where[2]=%02x, where[3]=%02x, \n", (unsigned int)temp_val, (unsigned int)where[0], (int)where[1], (int)where[2], (int)where[3]); + //md_number_to_chars(where, value, 0); + break; + case BFD_RELOC_ESP32S2ULP_JUMPR_THRESH: + if ((value > 0x7fff) || (value < -0x7fff)) + as_bad_where(fixP->fx_file, fixP->fx_line, _("rel too far BFD_JUMPR_THRESH")); + //value = value << 2; + temp_val = 0; + value &= 0xffff; + memcpy(&temp_val, where, 4); + temp_val &= ~((0xffff << 0)); + temp_val |= (value << 0); + memcpy(where, &temp_val, 4); + //DEBUG_TRACE("dya_pass - md_apply_fix:BFD_RELOC_ESP32S2ULP_JUMPR_THRESH temp_val=%08x value=%08x\n", (unsigned int)temp_val, (unsigned int)value); + //md_number_to_chars(where, value, 0); + break; + + case BFD_RELOC_ESP32S2ULP_JUMPS_THRESH: + if ((value > 0x7f) || (value < -0x7f)) + as_bad_where(fixP->fx_file, fixP->fx_line, _("rel too far BFD_JUMPS_THRESH")); + //value = value << 2; + temp_val = 0; + value &= 0xff; + memcpy(&temp_val, where, 4); + temp_val &= ~((0xff << 0)); + temp_val |= (value << 0); + memcpy(where, &temp_val, 4); + //DEBUG_TRACE("dya_pass - md_apply_fix:BFD_RELOC_ESP32S2ULP_JUMPS_THRESH temp_val=%08x value=%08x\n", (unsigned int)temp_val, (unsigned int)value); + //md_number_to_chars(where, value, 0); + break; + + case BFD_RELOC_ESP32S2ULP_REG_RW_HIGH: + if ((value > 0x1f) || (value < 0)) + as_bad_where(fixP->fx_file, fixP->fx_line, _("rel too far BFD_RELOC_ESP32S2ULP_REG_RW_HIGH")); + temp_val = 0; + value &= 0x1f; + memcpy(&temp_val, where, 4); + temp_val &= ~((0x1f << 23)); + temp_val |= (value << 23); + memcpy(where, &temp_val, 4); + //DEBUG_TRACE("dya_pass - md_apply_fix:BFD_RELOC_ESP32S2ULP_REG_RW_HIGH temp_val=%08x value=%08x\n", (unsigned int)temp_val, (unsigned int)value); + break; + case BFD_RELOC_ESP32S2ULP_REG_RW_LOW: + if ((value > 0x1f) || (value < 0)) + as_bad_where(fixP->fx_file, fixP->fx_line, _("rel too far BFD_RELOC_ESP32S2ULP_REG_RW_LOW")); + temp_val = 0; + value &= 0x1f; + memcpy(&temp_val, where, 4); + temp_val &= ~((0x1f << 18)); + temp_val |= (value << 18); + memcpy(where, &temp_val, 4); + //DEBUG_TRACE("dya_pass - md_apply_fix:BFD_RELOC_ESP32S2ULP_REG_RW_LOW temp_val=%08x value=%08x\n", (unsigned int)temp_val, (unsigned int)value); + break; + + case BFD_RELOC_ESP32S2ULP_REG_RW_ADDR: + value = check_reg_range(fixP, value); + + if (fixP->fx_addsy != NULL)// relocation will be done not in linker + { + asymbol *sym = symbol_get_bfdsym(fixP->fx_addsy); + if (sym->section->flags != 0) value = value >> 2; + } + temp_val = 0; + value &= 0x3ff; + memcpy(&temp_val, where, 4); + temp_val &= ~((0x3ff << 0)); + temp_val |= (value << 0); + memcpy(where, &temp_val, 4); + //DEBUG_TRACE("dya_pass - md_apply_fix:BFD_RELOC_ESP32S2ULP_REG_RW_ADDR temp_val=%08x value=%08x\n", (unsigned int)temp_val, (unsigned int)value); + break; + case BFD_RELOC_ESP32S2ULP_REG_RW_DATA: + value = check_reg_range(fixP, value); + + temp_val = 0; + value &= 0xff; + memcpy(&temp_val, where, 4); + temp_val &= ~((0xff << 10)); + temp_val |= (value << 10); + memcpy(where, &temp_val, 4); + //DEBUG_TRACE("dya_pass - md_apply_fix:BFD_RELOC_ESP32S2ULP_REG_RW_DATA temp_val=%08x value=%08x\n", (unsigned int)temp_val, (unsigned int)value); + break; + + case BFD_RELOC_ESP32S2ULP_I2C_RW_HIGH: + if ((value > 0x7) || (value < -0x7)) + as_bad_where(fixP->fx_file, fixP->fx_line, _("rel too far BFD_RELOC_ESP32S2ULP_I2C_RW_HIGH")); + temp_val = 0; + value &= 0x7; + memcpy(&temp_val, where, 4); + temp_val &= ~((0x7 << 19)); + temp_val |= (value << 19); + memcpy(where, &temp_val, 4); + //DEBUG_TRACE("dya_pass - md_apply_fix:BFD_RELOC_ESP32S2ULP_I2C_RW_HIGH temp_val=%08x value=%08x\n", (unsigned int)temp_val, (unsigned int)value); + break; + case BFD_RELOC_ESP32S2ULP_I2C_RW_LOW: + if ((value > 0x7) || (value < -0x7)) + as_bad_where(fixP->fx_file, fixP->fx_line, _("rel too far BFD_RELOC_ESP32S2ULP_I2C_RW_LOW")); + temp_val = 0; + value &= 0x7; + memcpy(&temp_val, where, 4); + temp_val &= ~((0x7 << 16)); + temp_val |= (value << 16); + memcpy(where, &temp_val, 4); + //DEBUG_TRACE("dya_pass - md_apply_fix:BFD_RELOC_ESP32S2ULP_I2C_RW_LOW temp_val=%08x value=%08x\n", (unsigned int)temp_val, (unsigned int)value); + break; + case BFD_RELOC_ESP32S2ULP_I2C_RW_SEL: + if ((value > 0xf) || (value < -0xf)) + as_bad_where(fixP->fx_file, fixP->fx_line, _("rel too far BFD_RELOC_ESP32S2ULP_I2C_RW_SEL")); + temp_val = 0; + value &= 0xf; + memcpy(&temp_val, where, 4); + temp_val &= ~((0xf << 22)); + temp_val |= (value << 22); + memcpy(where, &temp_val, 4); + //DEBUG_TRACE("dya_pass - md_apply_fix:BFD_RELOC_ESP32S2ULP_I2C_RW_SEL temp_val=%08x value=%08x\n", (unsigned int)temp_val, (unsigned int)value); + break; + case BFD_RELOC_ESP32S2ULP_I2C_RW_ADDR: + if ((value > 0xff) || (value < -0xff)) + as_bad_where(fixP->fx_file, fixP->fx_line, _("rel too far BFD_RELOC_ESP32S2ULP_I2C_RW_ADDR")); + temp_val = 0; + value &= 0xff; + memcpy(&temp_val, where, 4); + temp_val &= ~((0xff << 0)); + temp_val |= (value << 0); + memcpy(where, &temp_val, 4); + //DEBUG_TRACE("dya_pass - md_apply_fix:BFD_RELOC_ESP32S2ULP_I2C_RW_ADDR temp_val=%08x value=%08x\n", (unsigned int)temp_val, (unsigned int)value); + break; + case BFD_RELOC_ESP32S2ULP_I2C_RW_DATA: + if ((value > 0xff) || (value < -0xff)) + as_bad_where(fixP->fx_file, fixP->fx_line, _("rel too far BFD_RELOC_ESP32S2ULP_I2C_RW_DATA")); + temp_val = 0; + value &= 0xff; + memcpy(&temp_val, where, 4); + temp_val &= ~((0xff << 8)); + temp_val |= (value << 8); + memcpy(where, &temp_val, 4); + //DEBUG_TRACE("dya_pass - md_apply_fix:BFD_RELOC_ESP32S2ULP_I2C_RW_DATA temp_val=%08x value=%08x\n", (unsigned int)temp_val, (unsigned int)value); + break; + + default: + fprintf(stderr, "Relocation %d not handled in gas." " Contact support.\n", fixP->fx_r_type); + return; + //if ((BFD_ARELOC_ESP32S2ULP_PUSH > fixP->fx_r_type) || (BFD_ARELOC_ESP32S2ULP_COMP < fixP->fx_r_type)) + //{ + // fprintf(stderr, "Relocation %d not handled in gas." " Contact support.\n", fixP->fx_r_type); + // return; + //} + } + + if (!fixP->fx_addsy) + fixP->fx_done = TRUE; + +} + +/* Return true if the fix can be handled by GAS, false if it must +be passed through to the linker. */ + +bfd_boolean +esp32s2ulp_fix_adjustable(fixS *fixP) +{ + switch (fixP->fx_r_type) + { + /* Adjust_reloc_syms doesn't know about the GOT. */ + case BFD_RELOC_ESP32S2ULP_GOT: + case BFD_RELOC_ESP32S2ULP_PLTPC: + /* We need the symbol name for the VTABLE entries. */ + case BFD_RELOC_VTABLE_INHERIT: + case BFD_RELOC_VTABLE_ENTRY: + return 0; + + default: + return 1; + } +} + + + +INSTR_T +gencode(unsigned long x) +{ + INSTR_T cell = XOBNEW(&mempool, struct esp32s2ulp_insn); + memset(cell, 0, sizeof(struct esp32s2ulp_insn)); + cell->value = (x); + return cell; +} + + +INSTR_T +Expr_Node_Gen_Reloc(Expr_Node * head, int parent_reloc) +{ + /* Top level reloction expression generator VDSP style. + If the relocation is just by itself, generate one item + else generate this convoluted expression. */ + + INSTR_T note = NULL_CODE; + INSTR_T note1 = NULL_CODE; + int pcrel = 1; /* Is the parent reloc pcrelative? + This calculation here and HOWTO should match. */ + + if (parent_reloc) + { + /* If it's 32 bit quantity then 16bit code needs to be added. */ + int value = 0; + + if (head->type == Expr_Node_Constant) + { + /* If note1 is not null code, we have to generate a right + aligned value for the constant. Otherwise the reloc is + a part of the basic command and the yacc file + generates this. */ + value = head->value.i_value; + } + switch (parent_reloc) + { + /* Some relocations will need to allocate extra words. */ + case BFD_RELOC_ESP32S2ULP_16_IMM: + case BFD_RELOC_ESP32S2ULP_JUMPR: + case BFD_RELOC_ESP32S2ULP_16_LOAD: + case BFD_RELOC_ESP32S2ULP_WR_MEM: + case BFD_RELOC_ESP32S2ULP_WR_MEM_LABEL: + case BFD_RELOC_ESP32S2ULP_ALUI: + case BFD_RELOC_ESP32S2ULP_WAIT: + case BFD_RELOC_ESP32S2ULP_TSENS_DELAY: + case BFD_RELOC_ESP32S2ULP_WAKE: + case BFD_RELOC_ESP32S2ULP_SLEEP: + case BFD_RELOC_ESP32S2ULP_ADC_CYCLE: + case BFD_RELOC_ESP32S2ULP_ADC_SEL: + case BFD_RELOC_ESP32S2ULP_ADC_MUX: + case BFD_RELOC_ESP32S2ULP_STAGE: + //case BFD_RELOC_ESP32S2ULP_JUMPR_STEP: + case BFD_RELOC_ESP32S2ULP_JUMPR_THRESH: + case BFD_RELOC_ESP32S2ULP_JUMPS_THRESH: + case BFD_RELOC_ESP32S2ULP_REG_RW_HIGH: + case BFD_RELOC_ESP32S2ULP_REG_RW_LOW: + case BFD_RELOC_ESP32S2ULP_REG_RW_ADDR: + case BFD_RELOC_ESP32S2ULP_REG_RW_DATA: + case BFD_RELOC_ESP32S2ULP_I2C_RW_HIGH: + case BFD_RELOC_ESP32S2ULP_I2C_RW_LOW: + case BFD_RELOC_ESP32S2ULP_I2C_RW_ADDR: + case BFD_RELOC_ESP32S2ULP_I2C_RW_DATA: + case BFD_RELOC_ESP32S2ULP_I2C_RW_SEL: + note1 = conscode(gencode(value), NULL_CODE); + pcrel = 0; + break; + case BFD_RELOC_16: + case BFD_RELOC_24: + case BFD_RELOC_32: + note1 = conscode(gencode(value), NULL_CODE); + pcrel = 0; + break; + default: + note1 = NULL_CODE; + } + } + if (head->type == Expr_Node_Constant) + note = note1; + else if (head->type == Expr_Node_Reloc) + { + note = note_reloc1(gencode(0), head->value.s_value, parent_reloc, pcrel); + if (note1 != NULL_CODE) + note = conscode(note1, note); + } + else if (head->type == Expr_Node_Binop + && (head->value.op_value == Expr_Op_Type_Add + || head->value.op_value == Expr_Op_Type_Sub) + && head->Left_Child->type == Expr_Node_Reloc + && head->Right_Child->type == Expr_Node_Constant) + { + int val = head->Right_Child->value.i_value; + if (head->value.op_value == Expr_Op_Type_Sub) + val = -val; + note = conscode(note_reloc2(gencode(0), head->Left_Child->value.s_value, + parent_reloc, val, 0), + NULL_CODE); + if (note1 != NULL_CODE) + note = conscode(note1, note); + } + else + { + /* Call the recursive function. */ + note = note_reloc1(gencode(0), op, parent_reloc, pcrel); + if (note1 != NULL_CODE) + note = conscode(note1, note); + note = conctcode(Expr_Node_Gen_Reloc_R(head), note); + } + return note; +} + +static INSTR_T +Expr_Node_Gen_Reloc_R(Expr_Node * head) +{ + + INSTR_T note = 0; + INSTR_T note1 = 0; + + switch (head->type) + { + case Expr_Node_Constant: + note = conscode(note_reloc2(gencode(0), con, BFD_ARELOC_ESP32S2ULP_CONST, head->value.i_value, 0), NULL_CODE); + break; + case Expr_Node_Reloc: + note = conscode(note_reloc(gencode(0), head, BFD_ARELOC_ESP32S2ULP_PUSH, 0), NULL_CODE); + break; + case Expr_Node_Unop: + note1 = conscode(Expr_Node_Gen_Reloc_R(head->Left_Child), NULL_CODE); + switch (head->value.op_value) + { + case Expr_Op_Type_NEG: + note = conctcode(note1, conscode(note_reloc1(gencode(0), op, BFD_ARELOC_ESP32S2ULP_NEG, 0), NULL_CODE)); + break; + case Expr_Op_Type_COMP: + note = conctcode(note1, conscode(note_reloc1(gencode(0), op, BFD_ARELOC_ESP32S2ULP_COMP, 0), NULL_CODE)); + break; + default: + fprintf(stderr, "%s:%d:Unknown operator found for arithmetic" " relocation", __FILE__, __LINE__); + } + break; + default: + fprintf(stderr, "%s:%d:Unknown node expression found during " "arithmetic relocation generation", __FILE__, __LINE__); + } + return note; +} + +/* Blackfin opcode generation. */ + +/* These functions are called by the generated parser +(from esp32s2ulp-parse.y), the register type classification +happens in esp32s2ulp-lex.l. */ + +#include "esp32s2ulp-aux.h" +#include "opcode/esp32s2ulp.h" + + + +INSTR_T +esp32s2ulp_gen_progctrl(int prgfunc, int poprnd) +{ + (void) prgfunc; + (void) poprnd; + unsigned int local_op = OP_CMD_WAIT(0); + + return GEN_OPCODE32_DYA(local_op); +} + + +// ================= ESP32 =========================================================== + +INSTR_T esp32s2ulp_gen_alu_ADDR(int dst, int src1, int src2) +{ + //DEBUG_TRACE("dya_pass - esp32s2ulp_gen_alu_add - dst=%i, src1=%i, src2=%i\n", dst, src1, src2); + unsigned int local_op = I_ALUR(dst, src1, src2, ALU_SEL_ADD); + return GEN_OPCODE32_DYA(local_op); +} + +INSTR_T esp32s2ulp_gen_alu_r(int dst, int src1, int src2, int operation) +{ + //DEBUG_TRACE("dya_pass - esp32s2ulp_gen_alu_r - dst=%i, src1=%i, src2=%i, op = %i\n", dst, src1, src2, operation); + unsigned int local_op = I_ALUR(dst, src1, src2, operation); + return GEN_OPCODE32_DYA(local_op); +} + +INSTR_T esp32s2ulp_gen_alu_i(int dst, int src1, Expr_Node* addr, int operation) +{ + //DEBUG_TRACE("dya_pass - esp32s2ulp_gen_alu_i - dst=%i, src1=%i, operation = %i, type=%i, op_value = %i\n", dst, src1, operation, (int)addr->type, (int)addr->value.op_value); + int imm_val = EXPR_VALUE(addr); + unsigned int local_op = I_ALUI(dst, src1, imm_val, operation); + int rel = BFD_RELOC_ESP32S2ULP_ALUI; + return conscode(gencode(local_op), Expr_Node_Gen_Reloc(addr, rel)); +} + + +INSTR_T esp32s2ulp_gen_jump_r(int dst_reg, int cond) +{ + //DEBUG_TRACE("dya_pass - esp32s2ulp_gen_jump_r - dst_reg=%i, cond=%i\n", dst_reg, cond); + unsigned int local_op = I_JUMP_RI(dst_reg, 0, cond, 1); + return GEN_OPCODE32_DYA(local_op); +} +INSTR_T esp32s2ulp_gen_jump_i(Expr_Node* addr, int cond) +{ + int val; + int rel = 0; + + rel = BFD_RELOC_ESP32S2ULP_16_IMM; + + val = EXPR_VALUE(addr); + if ((val % 4) != 0) error("%s","Esp32S2Ulp is 32-bit addressing processor. Relative jump value must be divided by 4."); + unsigned int local_op = I_JUMP_RI(0, val>>2, cond, 0); + return conscode(gencode(local_op), Expr_Node_Gen_Reloc(addr, rel)); +} + +INSTR_T esp32s2ulp_cmd_jump_relr(Expr_Node* step, Expr_Node* thresh, int cond) +{ + int step_val = EXPR_VALUE(step); + int thresh_val = EXPR_VALUE(thresh); + + //DEBUG_TRACE("dya_pass - esp32s2ulp_cmd_jump_relr\n"); + unsigned int local_op = I_JUMP_RELR(thresh_val, cond, step_val>>2); + return conscode(gencode(local_op), conctcode(Expr_Node_Gen_Reloc(step, BFD_RELOC_ESP32S2ULP_JUMPR_STEP), Expr_Node_Gen_Reloc(thresh, BFD_RELOC_ESP32S2ULP_JUMPR_THRESH))); +} + + +INSTR_T esp32s2ulp_cmd_jump_rels(Expr_Node* step, Expr_Node* thresh, int cond) +{ + int step_val = EXPR_VALUE(step); + int thresh_val = EXPR_VALUE(thresh); + + { + unsigned int local_op = I_JUMP_RELS(thresh_val, cond, step_val); + + INSTR_T result = conscode(gencode(local_op), + conctcode(Expr_Node_Gen_Reloc(step, BFD_RELOC_ESP32S2ULP_JUMPR_STEP), + Expr_Node_Gen_Reloc(thresh, BFD_RELOC_ESP32S2ULP_JUMPS_THRESH) + ) + ); + + return result; + } + +} +INSTR_T esp32s2ulp_cmd_reg_rd(Expr_Node* addr, Expr_Node* high, Expr_Node* low) +{ + //DEBUG_TRACE("dya_pass - OP_CMD_REG_RD \n"); + unsigned int addr_val = EXPR_VALUE(addr); + unsigned int high_val = EXPR_VALUE(high); + unsigned int low_val = EXPR_VALUE(low); + + if (addr_val > DR_REG_MAX_DIRECT) + { + if ((addr_val >= DR_REG_RTCCNTL_BASE) && (addr_val < DR_REG_IO_MUX_BASE)) + { + addr_val = (addr_val - DR_REG_RTCCNTL_BASE)/4; + } else { + error("%s","Register address out of range. Must be 0..0x3ff, or in range of 0x3ff48000 .. 0x3ff49000."); + } + } + unsigned int local_op = I_RD_REG(addr_val, low_val, high_val); + + return conscode(gencode(local_op), + conctcode(Expr_Node_Gen_Reloc(addr, BFD_RELOC_ESP32S2ULP_REG_RW_ADDR), + conctcode(Expr_Node_Gen_Reloc(high, BFD_RELOC_ESP32S2ULP_REG_RW_HIGH), Expr_Node_Gen_Reloc(low, BFD_RELOC_ESP32S2ULP_REG_RW_LOW)))); +} +INSTR_T esp32s2ulp_cmd_reg_wr(Expr_Node* addr, Expr_Node* high, Expr_Node* low, Expr_Node* data) +{ + //DEBUG_TRACE("dya_pass - OP_CMD_REG_WR \n"); + unsigned int addr_val = EXPR_VALUE(addr); + unsigned int high_val = EXPR_VALUE(high); + unsigned int low_val = EXPR_VALUE(low); + unsigned int data_val = EXPR_VALUE(data); + + if (addr_val > DR_REG_MAX_DIRECT) + { + if ((addr_val >= DR_REG_RTCCNTL_BASE) && (addr_val < DR_REG_IO_MUX_BASE)) + { + addr_val = (addr_val - DR_REG_RTCCNTL_BASE)/4; + } else { + error("%s","Register address out of range. Must be 0..0x3ff, or in range of 0x3ff48000 .. 0x3ff49000."); + } + } + unsigned int local_op = I_WR_REG(addr_val, low_val, high_val, data_val); + + return conscode(gencode(local_op), + conctcode(Expr_Node_Gen_Reloc(addr, BFD_RELOC_ESP32S2ULP_REG_RW_ADDR), + conctcode(Expr_Node_Gen_Reloc(data, BFD_RELOC_ESP32S2ULP_REG_RW_DATA), + conctcode(Expr_Node_Gen_Reloc(high, BFD_RELOC_ESP32S2ULP_REG_RW_HIGH), Expr_Node_Gen_Reloc(low, BFD_RELOC_ESP32S2ULP_REG_RW_LOW))))); +} + +INSTR_T esp32s2ulp_cmd_i2c_rd(Expr_Node* i2c_addr, Expr_Node* high, Expr_Node* low, Expr_Node* i2c_sel) +{ + //DEBUG_TRACE("dya_pass - OP_CMD_I2C_RD \n"); + unsigned int addr_val = EXPR_VALUE(i2c_addr); + unsigned int high_val = EXPR_VALUE(high); + unsigned int low_val = EXPR_VALUE(low); + unsigned int i2c_sel_val = EXPR_VALUE(i2c_sel); + + unsigned int local_op = I_I2C_RW(addr_val, 0, low_val, high_val, i2c_sel_val, OPCODE_I2C_RD); + + return conscode(gencode(local_op), + conctcode(Expr_Node_Gen_Reloc(i2c_addr, BFD_RELOC_ESP32S2ULP_I2C_RW_ADDR), + conctcode(Expr_Node_Gen_Reloc(i2c_sel, BFD_RELOC_ESP32S2ULP_I2C_RW_SEL), + conctcode(Expr_Node_Gen_Reloc(high, BFD_RELOC_ESP32S2ULP_I2C_RW_HIGH), Expr_Node_Gen_Reloc(low, BFD_RELOC_ESP32S2ULP_I2C_RW_LOW))))); +} +INSTR_T esp32s2ulp_cmd_i2c_wr(Expr_Node* i2c_addr, Expr_Node* high, Expr_Node* low, Expr_Node* i2c_sel, Expr_Node* data) +{ + //DEBUG_TRACE("dya_pass - OP_CMD_I2C_RD \n"); + unsigned int addr_val = EXPR_VALUE(i2c_addr); + unsigned int high_val = EXPR_VALUE(high); + unsigned int low_val = EXPR_VALUE(low); + unsigned int i2c_sel_val = EXPR_VALUE(i2c_sel); + unsigned int data_val = EXPR_VALUE(data); + + unsigned int local_op = I_I2C_RW(addr_val, data_val, low_val, high_val, i2c_sel_val, OPCODE_I2C_WR); + + return conscode(gencode(local_op), + conctcode(Expr_Node_Gen_Reloc(i2c_addr, BFD_RELOC_ESP32S2ULP_I2C_RW_ADDR), + conctcode(Expr_Node_Gen_Reloc(i2c_sel, BFD_RELOC_ESP32S2ULP_I2C_RW_SEL), + conctcode(Expr_Node_Gen_Reloc(data, BFD_RELOC_ESP32S2ULP_I2C_RW_DATA), + conctcode(Expr_Node_Gen_Reloc(high, BFD_RELOC_ESP32S2ULP_I2C_RW_HIGH), Expr_Node_Gen_Reloc(low, BFD_RELOC_ESP32S2ULP_I2C_RW_LOW)))))); +} + + +INSTR_T esp32s2ulp_gen_jump_rels(Expr_Node* addr, int judge, int thresh) +{ + (void) judge; + (void) thresh; + int rel = 0; + + rel = BFD_RELOC_ESP32S2ULP_JUMPR; + unsigned int local_op = 0;// I_JUMP_RELR(0, val, cond, 1); + + return conscode(gencode(local_op), Expr_Node_Gen_Reloc(addr, rel)); +} + +//#define WR_MEM(dest, src, offs, labl, hl, way, sub) { *(unsigned int*)&(wr_mem ){ +INSTR_T esp32s2ulp_wr_mem_stlh(int low_hi, int dst_reg, int src_reg, Expr_Node *offset) +{ + int addr_val = EXPR_VALUE(offset); + unsigned int local_op = WR_MEM(dst_reg, src_reg, addr_val >> 2, 0, low_hi, 3, 0x4); + + return conscode(gencode(local_op), Expr_Node_Gen_Reloc(offset, BFD_RELOC_ESP32S2ULP_WR_MEM)); +} + +INSTR_T esp32s2ulp_wr_mem_st32(int dst_reg, int src_reg, Expr_Node *offset, Expr_Node *label) +{ + unsigned int label_val = EXPR_VALUE(label); + unsigned int offset_val = EXPR_VALUE(offset); + unsigned int local_op = WR_MEM(dst_reg, src_reg, offset_val >> 2, label_val, 0, 0, 0x4); + + return conscode(gencode(local_op), + conctcode(Expr_Node_Gen_Reloc(offset, BFD_RELOC_ESP32S2ULP_WR_MEM), Expr_Node_Gen_Reloc(label, BFD_RELOC_ESP32S2ULP_WR_MEM_LABEL))); + } + +INSTR_T esp32s2ulp_wr_mem_sti32(int dst_reg, int src_reg, Expr_Node* label) +{ + unsigned int label_val = EXPR_VALUE(label); + unsigned int local_op = WR_MEM(dst_reg, src_reg, 0, label_val, 0, 0, 0x1); + + return conscode(gencode(local_op),Expr_Node_Gen_Reloc(label, BFD_RELOC_ESP32S2ULP_WR_MEM_LABEL)); + } + +INSTR_T esp32s2ulp_wr_mem_st_l(int low_hi, int dst_reg, int src_reg, Expr_Node* offset, Expr_Node* label) +{ + unsigned int label_val = EXPR_VALUE(label); + unsigned int offset_val = EXPR_VALUE(offset); + unsigned int local_op = WR_MEM(dst_reg, src_reg, offset_val >> 2, label_val, low_hi, 1, 0x4); + + return conscode(gencode(local_op), + conctcode(Expr_Node_Gen_Reloc(label, BFD_RELOC_ESP32S2ULP_WR_MEM_LABEL), Expr_Node_Gen_Reloc(offset, BFD_RELOC_ESP32S2ULP_WR_MEM))); +} + +INSTR_T esp32s2ulp_wr_mem_sti_l(int dst_reg, int src_reg, Expr_Node* label) +{ + unsigned int label_val = EXPR_VALUE(label); + unsigned int local_op = WR_MEM(dst_reg, src_reg, 0, label_val, 0, 1, 0x1); + + return conscode(gencode(local_op),Expr_Node_Gen_Reloc(label, BFD_RELOC_ESP32S2ULP_WR_MEM_LABEL)); +} +INSTR_T esp32s2ulp_wr_mem_sti(int dst_reg, int src_reg) +{ + unsigned int local_op = WR_MEM(dst_reg, src_reg, 0, 0, 0, 3, 0x1); + return GEN_OPCODE32_DYA(local_op); +} + +INSTR_T esp32s2ulp_wr_mem_offset(Expr_Node* offset) +{ + int addr_val = EXPR_VALUE(offset); + unsigned int local_op = WR_MEM(0, 0, addr_val >> 2, 0, 0, 0, 0x2); + + return conscode(gencode(local_op), Expr_Node_Gen_Reloc(offset, BFD_RELOC_ESP32S2ULP_WR_MEM)); +} + +// INSTR_T esp32s2ulp_wr_mem_addr(int low_hi, int dst_reg, int src_reg, Expr_Node* addr) +// { +// //DEBUG_TRACE("dya_pass - esp32s2ulp_wr_mem_addr - dst_reg=%i, src_reg=%i, addr=%i\n", dst_reg, src_reg, (int)0); +// //#define WR_MEM(dest, src, offs, labl, hl, way, sub) { *(unsigned int*)&(wr_mem ){ +// if (addr != NULL) +// { +// int addr_val = EXPR_VALUE(addr); +// unsigned int local_op = WR_MEM(dst_reg, src_reg, addr_val>>2, low_hi,0,0,0);// I_JUMP_RELR(0, val, cond, 1); + +// int rel = 0; +// rel = BFD_RELOC_ESP32S2ULP_WR_MEM; +// return conscode(gencode(local_op), Expr_Node_Gen_Reloc(addr, rel)); +// } else +// { +// unsigned int local_op = WR_MEM(dst_reg, src_reg, 0, 0,0,0,0);// I_JUMP_RELR(0, val, cond, 1); +// return GEN_OPCODE32_DYA(local_op); +// } +// } + +INSTR_T esp32s2ulp_rd_mem_addr(int lh, int dst_reg, int src_reg, Expr_Node* addr) +{ + //DEBUG_TRACE("dya_pass - esp32s2ulp_rd_mem_addr - dst_reg=%i, src_reg=%i, addr=%i\n", dst_reg, src_reg, (int)0); + int addr_val = EXPR_VALUE(addr); + unsigned int local_op = RD_MEM(lh, dst_reg, src_reg, addr_val>>2);// I_JUMP_RELR(0, val, cond, 1); + + int rel = 0; + rel = BFD_RELOC_ESP32S2ULP_WR_MEM; + return conscode(gencode(local_op), Expr_Node_Gen_Reloc(addr, rel)); +} + +INSTR_T esp32s2ulp_rd_mem_offset(int dst_reg, int src_reg, int addr) +{ + //DEBUG_TRACE("dya_pass - esp32s2ulp_rd_mem_offset - dst_reg=%i, src_reg=%i, addr=%i\n", dst_reg, src_reg, addr); + unsigned int local_op = RD_MEM(0, dst_reg, src_reg, addr);// I_JUMP_RELR(0, val, cond, 1); + + return GEN_OPCODE32_DYA(local_op); +} + +INSTR_T esp32s2ulp_cmd_halt() +{ + //DEBUG_TRACE("dya_pass - OP_CMD_HALT \n"); + unsigned int local_op = OP_CMD_HALT(); + + return GEN_OPCODE32_DYA(local_op); +} + +INSTR_T esp32s2ulp_cmd_sleep(Expr_Node* cycles) +{ + //DEBUG_TRACE("dya_pass - OP_CMD_SLEEP \n"); + int cycles_val = EXPR_VALUE(cycles); + unsigned int local_op = OP_CMD_SLEEP(cycles_val); + return conscode(gencode(local_op), Expr_Node_Gen_Reloc(cycles, BFD_RELOC_ESP32S2ULP_SLEEP)); +} + +INSTR_T esp32s2ulp_cmd_wakeup(Expr_Node* wake) +{ + (void)wake; + //DEBUG_TRACE("dya_pass - OP_CMD_WAKEUP \n"); + //int wake_val = EXPR_VALUE(wake); + //unsigned int local_op = OP_CMD_WAKEUP(wake_val); + //return conscode(gencode(local_op), Expr_Node_Gen_Reloc(wake, BFD_RELOC_ESP32S2ULP_WAKE)); + unsigned int local_op = OP_CMD_WAKEUP(1); + return GEN_OPCODE32_DYA(local_op); +} + +INSTR_T esp32s2ulp_cmd_stage(int dir, Expr_Node* imm) +{ + //DEBUG_TRACE("dya_pass - OP_CMD_STAGE_INC \n"); + int imm_val = EXPR_VALUE(imm); + unsigned int local_op = I_ALUS(dir, imm_val); + + return conscode(gencode(local_op), Expr_Node_Gen_Reloc(imm, BFD_RELOC_ESP32S2ULP_STAGE)); +} + +INSTR_T esp32s2ulp_cmd_stage_rst() +{ + //DEBUG_TRACE("dya_pass - OP_CMD_STAGE_RST \n"); + unsigned int local_op = I_ALUS(ALU_SEL_SRST, 0); + + return GEN_OPCODE32_DYA(local_op); +} + +INSTR_T esp32s2ulp_cmd_wait(Expr_Node* cycles) +{ + int cycles_val = EXPR_VALUE(cycles); + unsigned int local_op = OP_CMD_WAIT(cycles_val); + int rel = BFD_RELOC_ESP32S2ULP_WAIT; + return conscode(gencode(local_op), Expr_Node_Gen_Reloc(cycles, rel)); +} + +INSTR_T esp32s2ulp_cmd_tsens(int dreg, Expr_Node* delay) +{ + //DEBUG_TRACE("dya_pass - OP_CMD_TSENS \n"); + int delay_val = EXPR_VALUE(delay); + unsigned int local_op = OP_CMD_TSENS(dreg, delay_val); + return conscode(gencode(local_op), Expr_Node_Gen_Reloc(delay, BFD_RELOC_ESP32S2ULP_TSENS_DELAY)); +} + +INSTR_T esp32s2ulp_cmd_adc(int dreg, Expr_Node* sar_sel, Expr_Node* mux) +{ + //DEBUG_TRACE("dya_pass - OP_CMD_ADC \n"); + unsigned int sar_val = EXPR_VALUE(sar_sel); + unsigned int mux_val = EXPR_VALUE(mux); + unsigned int local_op = OP_CMD_ADC(dreg, mux_val, sar_val); + + return conscode(gencode(local_op), + conctcode(Expr_Node_Gen_Reloc(mux, BFD_RELOC_ESP32S2ULP_ADC_MUX), Expr_Node_Gen_Reloc(sar_sel, BFD_RELOC_ESP32S2ULP_ADC_SEL))); +} + + +int +esp32s2ulp_force_relocation(struct fix *fixp) +{ + if (fixp->fx_r_type == BFD_RELOC_ESP32S2ULP_JUMPR) + return TRUE; + + return generic_force_reloc(fixp); +} + +//================================== ESP ========================== + + + +bfd_boolean +esp32s2ulp_eol_in_insn(char *line) +{ + /* Allow a new-line to appear in the middle of a multi-issue instruction. */ + + char *temp = line; + + if (*line != '\n') + return FALSE; + + /* A semi-colon followed by a newline is always the end of a line. */ + if (line[-1] == ';') + return FALSE; + + if (line[-1] == '|') + return TRUE; + + /* If the || is on the next line, there might be leading whitespace. */ + temp++; + while (*temp == ' ' || *temp == '\t') temp++; + + if (*temp == '|') + return TRUE; + + return FALSE; +} + +bfd_boolean +esp32s2ulp_start_label(char *s) +{ + while (*s != 0) + { + if (*s == '(' || *s == '[') + return FALSE; + s++; + } + + return TRUE; +} + + + diff --git a/gas/config/tc-esp32s2ulp.h b/gas/config/tc-esp32s2ulp.h new file mode 100644 index 00000000000..5e5b0376b07 --- /dev/null +++ b/gas/config/tc-esp32s2ulp.h @@ -0,0 +1,89 @@ +/* tc-esp32s2ulp.h + +ESP32S2ULP GNU Assembler + +Copyright (c) 2016-2017 Espressif Systems (Shanghai) PTE LTD. + +based on Copyright (C) 2005-2017 Free Software Foundation, Inc. + +This file is part of GAS, the GNU Assembler. + +GAS is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GAS is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GAS; see the file COPYING. If not, write to the Free +Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA +02110-1301, USA. */ + +#define TC_ESP32S2ULP 1 + +#define TARGET_BYTES_BIG_ENDIAN 0 +//#define OCTETS_PER_BYTE_POWER 2 + +#define TARGET_ARCH bfd_arch_esp32s2ulp + +/* +* Define the target format macro here. The value for this should be +* "elf32-esp32s2ulp", not "elf32-little-esp32s2ulp". Since the BFD source file +* elf32-esp32s2ulp.c defines TARGET_LITTLE_NAME to be "elf32-little-esp32s2ulp", +* we must use this value, until this is corrected and BFD is rebuilt. */ +#ifdef OBJ_ELF +#define TARGET_FORMAT "elf32-esp32s2ulp" +#endif + +#define LISTING_HEADER "ESP32S2ULP GAS " + +#define WORKING_DOT_WORD + +extern bfd_boolean esp32s2ulp_start_label(char *); + +#define md_number_to_chars number_to_chars_littleendian +#define md_convert_frag(b,s,f) as_fatal ("esp32s2ulp convert_frag\n"); + +/* Allow for [, ], etc. */ +#define LEX_BR 6 + +#define TC_EOL_IN_INSN(PTR) (esp32s2ulp_eol_in_insn(PTR) ? 1 : 0) +extern bfd_boolean esp32s2ulp_eol_in_insn(char *); + +#define TC_EQUAL_IN_INSN(C, NAME) 1 + +#define NOP_OPCODE 0x0000 + +#define LOCAL_LABELS_FB 1 + +#define DOUBLESLASH_LINE_COMMENTS + +#define TC_START_LABEL(STR, NUL_CHAR, NEXT_CHAR) \ + (NEXT_CHAR == ':' && esp32s2ulp_start_label (STR)) +#define tc_fix_adjustable(FIX) esp32s2ulp_fix_adjustable (FIX) +extern bfd_boolean esp32s2ulp_fix_adjustable(struct fix *); + +#define TC_FORCE_RELOCATION(FIX) esp32s2ulp_force_relocation (FIX) +extern int esp32s2ulp_force_relocation(struct fix *); + +/* Call md_pcrel_from_section(), not md_pcrel_from(). */ +#define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from_section (FIX, SEC) +extern long md_pcrel_from_section(struct fix *, segT); + +/* Values passed to md_apply_fix3 don't include symbol values. */ +#define MD_APPLY_SYM_VALUE(FIX) 0 + +/* This target is buggy, and sets fix size too large. */ +#define TC_FX_SIZE_SLACK(FIX) 2 + +extern unsigned int esp32s2ulp_anomaly_checks; + +/* Anomaly checking */ +#define AC_05000074 0x00000001 +#define ENABLE_AC_05000074 (esp32s2ulp_anomaly_checks & AC_05000074) + +/* end of tc-esp32s2ulp.h */ diff --git a/gas/config/tc-esp32ulp_common.c b/gas/config/tc-esp32ulp_common.c new file mode 100644 index 00000000000..5b114c5058b --- /dev/null +++ b/gas/config/tc-esp32ulp_common.c @@ -0,0 +1,403 @@ + + +extern int yyparse(void); +struct yy_buffer_state; +typedef struct yy_buffer_state *YY_BUFFER_STATE; +extern YY_BUFFER_STATE yy_scan_string(const char *yy_str); +extern void yy_delete_buffer(YY_BUFFER_STATE b); +static parse_state parse(char *line); +static long check_reg_range(fixS* fixP, long value); + +int last_insn_size; + +extern struct obstack mempool; +FILE *errorf; + +/* Flags to set in the elf header */ +#define DEFAULT_FLAGS 0 + +/* Characters that are used to denote comments and line separators. */ +const char comment_chars[] = "#"; +const char line_comment_chars[] = "#"; +const char line_separator_chars[] = ";"; + +/* Characters that can be used to separate the mantissa from the +exponent in floating point numbers. */ +const char EXP_CHARS[] = "eE"; + +/* Characters that mean this number is a floating point constant. +As in 0f12.456 or 0d1.2345e12. */ +const char FLT_CHARS[] = "fFdDxX"; + + + +/* Define esp32ulp-specific command-line options (there are none). */ +const char *md_shortopts = ""; + +struct option md_longopts[] = +{ + { NULL, no_argument, NULL, 0 }, +}; + +size_t md_longopts_size = sizeof(md_longopts); + + +int +md_parse_option(int c ATTRIBUTE_UNUSED, const char *arg ATTRIBUTE_UNUSED) +{ + switch (c) + { + default: + return 0; + } + + return 1; +} + +void +md_show_usage(FILE * stream) +{ + fprintf(stream, _(" ESP32 ULP processor has no specific assembler options:\n")); +} + + + +/* Perform the main parsing, and assembly of the input here. Also, +call the required routines for alignment and fixups here. +This is called for every line that contains real assembly code. */ +//#include "../../gdb/symtab.h" +void +md_assemble(char *line) +{ + char *toP ; + int insn_size; + size_t len; + static size_t buffer_len = 0; + static char *current_inputline; + parse_state state; + + len = strlen(line); + if (len + 2 > buffer_len) + { + buffer_len = len + 40; + current_inputline = XRESIZEVEC(char, current_inputline, buffer_len); + } + memcpy(current_inputline, line, len); + current_inputline[len] = ';'; + current_inputline[len + 1] = '\0'; + + // run the parser on the instruction + // it will return a list of chained "insn", + // the first contains the opcode of the instruction + // and may be followed by other "insn" like an address + state = parse(current_inputline); + if (state == NO_INSN_GENERATED || !insn) + return; + + // add 4 bytes to the fragment code buffer to put the new instruction + // and get buffer pointer (toP) on where to write the instruction + insn_size = 4; + toP = frag_more(insn_size); + +#ifdef DEBUG + printf("INS: %s\n", line); +#endif + md_number_to_chars(toP, insn->value, insn_size); // put the 4-byte instruction into the current fragment code buffer + + while (insn) + { + if (insn->reloc && insn->exp->symbol) + { + //DEBUG_TRACE("insn->reloc && insn->exp->symbol BFD_ARELOC_ESP32ULP_PUSH size =%i, insn->exp->value=%i, insn->pcrel=%i, insn->reloc=%i\n", size, (unsigned int)insn->exp->value, insn->pcrel, insn->reloc); + + // generate a relocation request for this instruction so that linker will put the right address + // toP is the pointer on this instruction in the buffer of the current code fragment + // frag_now->fr_literal is the pointer on the begining of the buffer of the current code fragment + fix_new(frag_now, toP - frag_now->fr_literal, insn_size, insn->exp->symbol, insn->exp->value, insn->pcrel, insn->reloc); + } +#ifdef DEBUG + //DEBUG_TRACE(" reloc : value = %08x, pc=%08x, reloc=%08x BFD_RELOC_ESP32ULP_PLTPC = %08x\n", (unsigned int)insn->value, (unsigned int)insn->pcrel, (unsigned int)insn->reloc, BFD_RELOC_ESP32S2ULP_PLTPC); + if (insn->exp != ((void*)(0))) + { + //DEBUG_TRACE(" exp: %08x, sy_obj=%i\n", insn->exp->value, insn->exp->symbol->sy_obj.local); + } +#endif + insn = insn->next; + if (insn) + { + int ml = insn->mult; + if (ml != 0) + { + toP = frag_more(insn_size); + md_number_to_chars(toP, insn->value, insn_size); // put the 4-byte instruction into the current fragment code buffer + } + } + } +#ifdef OBJ_ELF + dwarf2_emit_insn(insn_size); + //DEBUG_TRACE("dya_pass ============== >insn_size=%i\n", (unsigned int)insn_size); +#endif + + while (*line++ != '\0') + if (*line == '\n') + bump_line_counters(); +} + +/* Parse one line of instructions, and generate opcode for it. +To parse the line, YACC and LEX are used, because the instruction set +syntax doesn't confirm to the AT&T assembly syntax. +To call a YACC & LEX generated parser, we must provide the input via +a FILE stream, otherwise stdin is used by default. Below the input +to the function will be put into a temporary file, then the generated +parser uses the temporary file for parsing. */ + +static parse_state +parse(char *line) +{ + parse_state state; + YY_BUFFER_STATE buffstate; + + buffstate = yy_scan_string(line); + + /* our lex requires setting the start state to keyword + every line as the first word may be a keyword. + Fixes a bug where we could not have keywords as labels. */ + set_start_state(); + + /* Call yyparse here. */ + //DEBUG_TRACE("yyparse: %s\n", line); + state = yyparse(); + //DEBUG_TRACE("yyparse result!: %i\n", (int)state); + if (state == SEMANTIC_ERROR) + { + as_bad(_("Parse failed.")); + //DEBUG_TRACE("yyparse ERROR!: %s\n", line); + insn = 0; + } + + yy_delete_buffer(buffstate); + return state; +} + +/* We need to handle various expressions properly. +Such as, [SP--] = 34, concerned by md_assemble(). */ + +void +md_operand(expressionS * expressionP) +{ + if (*input_line_pointer == '[') + { + as_tsktsk("We found a '['!"); + input_line_pointer++; + expression(expressionP); + } +} + +/* Handle undefined symbols. */ +symbolS * +md_undefined_symbol(char *name ATTRIBUTE_UNUSED) +{ + return (symbolS *)0; +} + +int +md_estimate_size_before_relax(fragS * fragP ATTRIBUTE_UNUSED, +segT segment ATTRIBUTE_UNUSED) +{ + return 0; +} + +static long +check_reg_range(fixS* fixP, long value) +{ + long result = value; + if ((value > DR_REG_MAX_DIRECT) || (value < 0)){ + if ((value >= DR_REG_RTCCNTL_BASE) && (value < DR_REG_IO_MUX_BASE)){ + result = (value - DR_REG_RTCCNTL_BASE)/4; + } else { + as_bad_where(fixP->fx_file, fixP->fx_line, _("Register address out of range. Must be in range of 0..0x3ff or 0x3ff48000..0x3ff49000.")); + } + } + return result; +} + + + +/* Round up a section size to the appropriate boundary. */ +valueT +md_section_align(segT segment, valueT size) +{ + int boundary = bfd_get_section_alignment(stdoutput, segment); + return ((size + (1 << boundary) - 1) & -(1 << boundary)); +} + + +const char * +md_atof(int type, char * litP, int * sizeP) +{ + return ieee_md_atof(type, litP, sizeP, FALSE); +} + + +/* If while processing a fixup, a reloc really needs to be created +then it is done here. */ + +arelent * +tc_gen_reloc(asection *seg ATTRIBUTE_UNUSED, fixS *fixp) +{ + arelent *reloc; + + reloc = XNEW(arelent); + reloc->sym_ptr_ptr = XNEW(asymbol *); + *reloc->sym_ptr_ptr = symbol_get_bfdsym(fixp->fx_addsy); + reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; + + //reloc->address = reloc->address / 4; + + reloc->addend = fixp->fx_offset; + reloc->howto = bfd_reloc_type_lookup(stdoutput, fixp->fx_r_type); + + //DEBUG_TRACE("tc_gen_reloc - reloc->address =%08x, symvalue=%08x, seg->flags=%08x, name=%s\n", (unsigned int)reloc->address, (unsigned int)(*reloc->sym_ptr_ptr)->value, (unsigned int)seg->flags, (*reloc->sym_ptr_ptr)->name); + + if (reloc->howto == (reloc_howto_type *)NULL) + { + as_bad_where(fixp->fx_file, fixp->fx_line, + /* xgettext:c-format. */ + _("reloc %d not supported by object file format"), + (int)fixp->fx_r_type); + + xfree(reloc); + + return NULL; + } + + return reloc; +} + +/* The location from which a PC relative jump should be calculated, +given a PC relative reloc. */ + +long +md_pcrel_from_section(fixS *fixP, segT sec) +{ + if (fixP->fx_addsy != (symbolS *)NULL + && (!S_IS_DEFINED(fixP->fx_addsy) + || S_GET_SEGMENT(fixP->fx_addsy) != sec)) + { + /* The symbol is undefined (or is defined but not in this section). + Let the linker figure it out. */ + return 0; + } + return fixP->fx_frag->fr_address + fixP->fx_where; +} + +INSTR_T +note_reloc(INSTR_T code, Expr_Node * symbol, int reloc, int pcrel) +{ + /* Assert that the symbol is not an operator. */ + gas_assert(symbol->type == Expr_Node_Reloc); + + return note_reloc1(code, symbol->value.s_value, reloc, pcrel); + +} + +INSTR_T +note_reloc1(INSTR_T code, const char *symbol, int reloc, int pcrel) +{ + code->reloc = reloc; + code->exp = mkexpr(0, symbol_find_or_make(symbol)); + code->pcrel = pcrel; + return code; +} + +INSTR_T +note_reloc2(INSTR_T code, const char *symbol, int reloc, int value, int pcrel) +{ + code->reloc = reloc; + code->exp = mkexpr(value, symbol_find_or_make(symbol)); + code->pcrel = pcrel; + return code; +} + +/* Special extra functions that help esp32ulp-parse.y perform its job. */ + +struct obstack mempool; + +INSTR_T +conscode(INSTR_T head, INSTR_T tail) +{ + if (!head) + return tail; + head->next = tail; + return head; +} + +INSTR_T +conctcode(INSTR_T head, INSTR_T tail) +{ + INSTR_T temp = (head); + if (!head) + return tail; + while (temp->next) + temp = temp->next; + temp->next = tail; + + return head; +} + +int reloc; +int ninsns; +int count_insns; + +static void * +allocate(size_t n) +{ + return obstack_alloc(&mempool, n); +} + +Expr_Node * +Expr_Node_Create(Expr_Node_Type type, +Expr_Node_Value value, +Expr_Node *Left_Child, +Expr_Node *Right_Child) +{ + + + Expr_Node *node = (Expr_Node *)allocate(sizeof(Expr_Node)); + node->type = type; + node->value = value; + node->Left_Child = Left_Child; + node->Right_Child = Right_Child; + return node; +} + +static const char *con = ".__constant"; +static const char *op = ".__operator"; +static INSTR_T Expr_Node_Gen_Reloc_R(Expr_Node * head); +INSTR_T Expr_Node_Gen_Reloc(Expr_Node *head, int parent_reloc); + +#define INIT(t) t c_code = init_##t +#define ASSIGN(x) c_code.opcode |= ((x & c_code.mask_##x)< ./gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_st.lst +./gas/as-new -al ./gas/testsuite/gas/esp32s2ulp/esp32s2ulp_regrw.s > ./gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_regrw.lst +./gas/as-new -al ./gas/testsuite/gas/esp32s2ulp/esp32s2ulp_i2crw.s > ./gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_i2crw.lst +./gas/as-new -al ./gas/testsuite/gas/esp32s2ulp/esp32s2ulp_wait.s > ./gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_wait.lst +./gas/as-new -al ./gas/testsuite/gas/esp32s2ulp/esp32s2ulp_adc.s > ./gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_adc.lst +./gas/as-new -al ./gas/testsuite/gas/esp32s2ulp/esp32s2ulp_alu.s > ./gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_alu.lst +./gas/as-new -al ./gas/testsuite/gas/esp32s2ulp/esp32s2ulp_jump.s > ./gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_jump.lst +./gas/as-new -al ./gas/testsuite/gas/esp32s2ulp/esp32s2ulp_wakehalt.s > ./gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_wakehalt.lst +./gas/as-new -al ./gas/testsuite/gas/esp32s2ulp/esp32s2ulp_tsens.s > ./gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_tsens.lst +./gas/as-new -al ./gas/testsuite/gas/esp32s2ulp/esp32s2ulp_sleep.s > ./gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_sleep.lst +./gas/as-new -al ./gas/testsuite/gas/esp32s2ulp/esp32s2ulp_ld.s > ./gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_ld.lst +# This part used to check gas and linker together +#./gas/as-new -al ./gas/testsuite/gas/esp32s2ulp/esp32s2ulp_st.s -o ./gas/testsuite/gas/esp32s2ulp/esp32s2ulp_st.elf +#./ld/ld-new.exe -o ./gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_st.bin -A elf32-esp32s2ulp ./gas/testsuite/gas/esp32s2ulp/esp32s2ulp_st.elf \ No newline at end of file diff --git a/gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_adc.lst b/gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_adc.lst new file mode 100644 index 00000000000..1b19f2fe5b6 --- /dev/null +++ b/gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_adc.lst @@ -0,0 +1,30 @@ +ESP32S2ULP GAS ./gas/testsuite/gas/esp32s2ulp/esp32s2ulp_adc.s page 1 + + + 1 .data //Data section definition + 2 0000 7B00 Addr1: .word 123 // Define label Addr1 16 bit + 3 .set min_adc_sel, 0 - 0 + 4 .set max_adc_sel, 1 + 0 + 5 .set min_adc_mux, 0 - 0 + 6 .set max_adc_mux, 15 + 0 + 7 .set min_adc_cyc, 0 - 0 + 8 .set max_adc_cyc, 65535 + 0 + 9 .global min_adc_sel2 + 10 .global max_adc_sel2 + 11 .global min_adc_mux2 + 12 .global max_adc_mux2 + 13 .global min_adc_cyc2 + 14 .global max_adc_cyc2 + 15 .global __start + 16 + 17 __start: + 18 + 19 0002 0000 .text //Text section definition + 20 + 21 0000 01000050 ADC R1, 0, 0, 0 + 22 0004 01000050 ADC R1, min_adc_sel, min_adc_mux, min_adc_cyc + 23 0008 7D000050 ADC R1, 1, 15, 0xffff + 24 000c 7D000050 ADC R1, max_adc_sel, max_adc_mux, max_adc_cyc + 25 + 26 0010 01000050 ADC R1, min_adc_sel2, min_adc_mux2, min_adc_cyc2 + 27 0014 01000050 ADC R1, max_adc_sel2, max_adc_mux2, max_adc_cyc2 diff --git a/gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_alu.lst b/gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_alu.lst new file mode 100644 index 00000000000..fa4db661a16 --- /dev/null +++ b/gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_alu.lst @@ -0,0 +1,55 @@ +ESP32S2ULP GAS ./gas/testsuite/gas/esp32s2ulp/esp32s2ulp_alu.s page 1 + + + 1 .data //Data section definition + 2 0000 7B00 Addr1: .word 123 // Define label Addr1 16 bit + 3 + 4 .global __start + 5 __start: + 6 + 7 0002 0000 .text //Text section definition + 8 // Register operations - relative operations + 9 0000 39000070 Add R1, R2, R3 + 10 0004 39002070 Sub R1, R2, R3 + 11 0008 39004070 And R1, R2, R3 + 12 000c 39006070 Or R1, R2, R3 + 13 0010 3900C070 RSH R1, R2, R3 + 14 0014 3900A070 LSH R1, R2, R3 + 15 0018 29008070 MOVE R1, R2 + 16 + 17 .set im_data_d, 0xff + 18 .set im_data_r, 0xff + 19 .global im_data_r + 20 + 21 001c F90F0074 Add R1, R2, 0xff + 22 0020 F90F0074 Add R1, R2, im_data_d + 23 0024 09000074 Add R1, R2, im_data_r + 24 0028 F90F2074 Sub R1, R2, 0xff + 25 002c F90F2074 Sub R1, R2, im_data_d + 26 0030 09002074 Sub R1, R2, im_data_r + 27 0034 F90F4074 And R1, R2, 0xff + 28 0038 F90F4074 And R1, R2, im_data_d + 29 003c 09004074 And R1, R2, im_data_r + 30 0040 F90F6074 Or R1, R2, 0xff + 31 0044 F90F6074 Or R1, R2, im_data_d + 32 0048 09006074 Or R1, R2, im_data_r + 33 004c F90FC074 RSH R1, R2, 0xff + 34 0050 F90FC074 RSH R1, R2, im_data_d + 35 0054 0900C074 RSH R1, R2, im_data_r + 36 0058 F90FA074 LSH R1, R2, 0xff + 37 005c F90FA074 LSH R1, R2, im_data_d + 38 0060 0900A074 LSH R1, R2, im_data_r + 39 0064 F10F8074 MOVE R1, 0xff + 40 0068 F10F8074 MOVE R1, im_data_d + 41 006c 01008074 MOVE R1, im_data_r + 42 + 43 0070 00004078 STAGE_RST + 44 0074 F00F0078 STAGE_INC 0xff + 45 0078 F00F0078 STAGE_INC im_data_d + 46 007c 00000078 STAGE_INC im_data_r + 47 0080 F00F2078 STAGE_DEC 0xff + 48 0084 F00F2078 STAGE_DEC im_data_d + 49 0088 00002078 STAGE_DEC im_data_r + 50 + 51 + 52 diff --git a/gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_i2crw.lst b/gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_i2crw.lst new file mode 100644 index 00000000000..b8f96133b5a --- /dev/null +++ b/gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_i2crw.lst @@ -0,0 +1,35 @@ +ESP32S2ULP GAS ./gas/testsuite/gas/esp32s2ulp/esp32s2ulp_i2crw.s page 1 + + + 1 .data //Data section definition + 2 0000 7B00 Addr1: .word 123 // Define label Addr1 16 bit + 3 .set i2c_addr, 0x77 + 4 .set i2c_data1, 0x40 + 5 .set i2c_high, 0x00 + 6 .set i2c_low, 0x01 + 7 .set i2c_sel, 0x00 + 8 .set test_val, 1 + 9 + 10 .set i2c_addr2, 0x77 + 11 .set i2c_data2, 0x40 + 12 .set i2c_high2, 0x00 + 13 .set i2c_low2, 0x01 + 14 .set i2c_sel2, 0x00 + 15 .global i2c_addr2 + 16 .global i2c_data2 + 17 .global i2c_high2 + 18 .global i2c_low2 + 19 .global i2c_sel2 + 20 + 21 .global __start + 22 __start: + 23 + 24 0002 0000 .text //Text section definition + 25 + 26 0000 77400138 I2C_WR 0x77, 0x40, 0x00,0x01,0x00 + 27 0004 77400138 I2C_WR i2c_addr, i2c_data1, i2c_high,i2c_low,i2c_sel + 28 0008 00000038 I2C_WR i2c_addr2, i2c_data2, i2c_high2,i2c_low2,i2c_sel2 + 29 + 30 000c 77000130 I2C_RD 0x77, 0x00,0x01,0x00 + 31 0010 77000130 I2C_RD i2c_addr, i2c_high,i2c_low,i2c_sel + 32 0014 00000030 I2C_RD i2c_addr2, i2c_high2,i2c_low2,i2c_sel2 diff --git a/gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_jump.lst b/gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_jump.lst new file mode 100644 index 00000000000..986f62cdb31 --- /dev/null +++ b/gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_jump.lst @@ -0,0 +1,79 @@ +ESP32S2ULP GAS ./gas/testsuite/gas/esp32s2ulp/esp32s2ulp_jump.s page 1 + + + 1 .data //Data section definition + 2 0000 7B00 Addr1: .word 123 // Define label Addr1 16 bit + 3 + 4 .set check_jump1, 0x10 + 5 .set check_jump2, 0x10 + 6 .global check_jump2 + 7 + 8 .set check_thres1, 0x04 + 9 .set check_thres2, 0x04 + 10 .global check_thres2 + 11 + 12 + 13 .global __start + 14 __start: + 15 + 16 0002 0000 .text + 17 .global jmp2 + 18 0000 00000040 nop + 19 jmp1: + 20 0004 00000040 jmp2: nop + 21 0008 04000084 jump 0x04 + 22 000c 10000084 jump check_jump1 + 23 0010 00000084 jump check_jump2 + 24 0014 01002084 jump R1 + 25 0018 04004084 jump 0x04, EQ + 26 001c 10004084 jump check_jump1, EQ + 27 0020 00004084 jump check_jump2, EQ + 28 0024 01006084 jump R1, EQ + 29 0028 04008084 jump 0x04, OV + 30 002c 10008084 jump check_jump1, OV + 31 0030 00008084 jump check_jump2, OV + 32 0034 0100A084 jump R1, OV + 33 // Jump to labele + 34 0038 04004084 jump jmp1, EQ + 35 003c 00004084 jump jmp2, EQ + 36 0040 04008084 jump jmp1, OV + 37 0044 00008084 jump jmp2, OV + 38 + 39 // Relative Jump + 40 0048 04000480 JUMPR 0x04, 0x4, LT + 41 004c 04003C82 JUMPR check_jump1, 0x4, LT + 42 0050 04000480 JUMPR 0x04, check_thres1, LT + 43 0054 04004482 JUMPR check_jump1, check_thres1, LT + 44 0058 04004882 JUMPR check_jump2, check_thres1, LT + 45 005c 00004C82 JUMPR check_jump2, check_thres2, LT + 46 0060 04000580 JUMPR 0x04, 0x4, GT + 47 0064 04005582 JUMPR check_jump1, 0x4, GT + 48 0068 04000580 JUMPR 0x04, check_thres1, GT + 49 006c 04005D82 JUMPR check_jump1, check_thres1, GT + 50 0070 04006182 JUMPR check_jump2, check_thres1, GT + 51 0074 00006582 JUMPR check_jump2, check_thres2, GT + 52 0078 04000680 JUMPR 0x04, 0x4, EQ + 53 007c 04006E82 JUMPR check_jump1, 0x4, EQ + 54 0080 04000680 JUMPR 0x04, check_thres1, EQ + 55 0084 04007682 JUMPR check_jump1, check_thres1, EQ + 56 0088 04007A82 JUMPR check_jump2, check_thres1, EQ + 57 008c 00007E82 JUMPR check_jump2, check_thres2, EQ + ESP32S2ULP GAS ./gas/testsuite/gas/esp32s2ulp/esp32s2ulp_jump.s page 2 + + + 58 + 59 // Jumps commands... + 60 0090 04001288 jumps 0x4, 0x04, EQ + 61 0094 04001288 jumps 0x04, check_thres1, EQ + 62 0098 04008A8A jumps check_jump1, check_thres1, EQ + 63 009c 00008E8A jumps check_jump1, check_thres2, EQ + 64 00a0 0400928A jumps check_jump2, check_thres1, EQ + 65 00a4 0000968A jumps check_jump2, check_thres2, EQ + 66 + 67 00a8 00000288 jumps 0x0, 0x00, EQ + 68 00ac 00800088 jumps 0x0, 0x00, LT + 69 00b0 00800188 jumps 0x0, 0x00, GT + 70 00b4 00800288 jumps 0x0, 0x00, LE + 71 00b8 00800388 jumps 0x0, 0x00, GE + 72 + 73 diff --git a/gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_ld.lst b/gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_ld.lst new file mode 100644 index 00000000000..c12241d407f --- /dev/null +++ b/gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_ld.lst @@ -0,0 +1,25 @@ +ESP32S2ULP GAS ./gas/testsuite/gas/esp32s2ulp/esp32s2ulp_ld.s page 1 + + + 1 + 2 .data //Data section definition + 3 0000 7B00 Addr1: .word 123 // Define label Addr1 16 bit + 4 .set offs, 0x20 // Define constant offs + 5 + 6 .set offs2, 0x20 // Define constant offs + 7 .global offs2 + 8 + 9 + 10 .global __start + 11 __start: + 12 + 13 0002 0000 .text //Text section definition + 14 0000 092000D0 LD R1, R2, 0x20 + 15 0004 092000D0 LD R1, R2, offs + 16 0008 090000D0 LD R1, R2, offs2 + 17 000c 092000D0 LDL R1, R2, 0x20 + 18 0010 092000D0 LDL R1, R2, offs + 19 0014 090000D0 LDL R1, R2, offs2 + 20 0018 092000D8 LDH R1, R2, 0x20 + 21 001c 092000D8 LDH R1, R2, offs + 22 0020 090000D8 LDH R1, R2, offs2 diff --git a/gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_regrw.lst b/gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_regrw.lst new file mode 100644 index 00000000000..c49ba77e8b5 --- /dev/null +++ b/gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_regrw.lst @@ -0,0 +1,51 @@ +ESP32S2ULP GAS ./gas/testsuite/gas/esp32s2ulp/esp32s2ulp_regrw.s page 1 + + + 1 .data //Data section definition + 2 0000 7B00 Addr1: .word 123 // Define label Addr1 16 bit + 3 .set offs, 0x20 // Define constant offs + 4 .set lab1, 0x01 // Define constant offs + 5 + 6 .set offs2, 0x20 // Define constant offs + 7 .set lab2, 0x1 // Define constant offs + 8 .global lab2 + 9 .global offs2 + 10 + 11 + 12 .global __start + 13 __start: + 14 + 15 0002 0000 .text //Text section definition + 16 + 17 .set min_reg_Addr, 0 - 0 + 18 .set max_reg_Addr, 0x3ff + 0 + 19 .set min_reg_High, 0 - 0 + 20 .set max_reg_High, 31 + 0 + 21 .set min_reg_Low, 0 - 0 + 22 .set max_reg_Low, 31 + 0 + 23 .set min_reg_data, 0 - 0 + 24 .set max_reg_data, 255 + 0 + 25 + 26 0000 00000020 REG_RD 0, 0, 0 + 27 0004 FF03FC2F REG_RD 0x3ff, 31, 31 + 28 0008 00000010 REG_WR 0, 0, 0, 0 + 29 000c FFFFFF1F REG_WR 0x3ff, 31, 31, 255 + 30 + 31 0010 00000020 REG_RD min_reg_Addr, min_reg_High, min_reg_Low + 32 0014 FF03FC2F REG_RD max_reg_Addr, max_reg_High, max_reg_Low + 33 0018 00000010 REG_WR min_reg_Addr, min_reg_High, min_reg_Low, min_reg_data + 34 001c FFFFFF1F REG_WR max_reg_Addr, max_reg_High, max_reg_Low, max_reg_data + 35 + 36 .global min_reg_Addr2 + 37 .global max_reg_Addr2 + 38 .global min_reg_High2 + 39 .global max_reg_High2 + 40 .global min_reg_Low2 + 41 .global max_reg_Low2 + 42 .global min_reg_data2 + 43 .global max_reg_data2 + 44 + 45 0020 00000020 REG_RD min_reg_Addr2, min_reg_High2, min_reg_Low2 + 46 0024 00000020 REG_RD max_reg_Addr2, max_reg_High2, max_reg_Low2 + 47 0028 00000010 REG_WR min_reg_Addr2, min_reg_High2, min_reg_Low2, min_reg_data2 + 48 002c 00000010 REG_WR max_reg_Addr2, max_reg_High2, max_reg_Low2, max_reg_data2 diff --git a/gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_sleep.lst b/gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_sleep.lst new file mode 100644 index 00000000000..b1dfa2143ae --- /dev/null +++ b/gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_sleep.lst @@ -0,0 +1,19 @@ +ESP32S2ULP GAS ./gas/testsuite/gas/esp32s2ulp/esp32s2ulp_sleep.s page 1 + + + 1 .data //Data section definition + 2 0000 7B00 Addr1: .word 123 // Define label Addr1 16 bit + 3 + 4 .set wait_delay1, 0x04 + 5 .set wait_delay2, 0x04 + 6 .global wait_delay2 + 7 + 8 .global __start + 9 __start: + 10 + 11 0002 0000 .text + 12 .global jmp2 + 13 0000 00000040 nop + 14 0004 04000040 SLEEP 0x04 + 15 0008 04000040 SLEEP wait_delay1 + 16 000c 00000040 SLEEP wait_delay2 diff --git a/gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_st.lst b/gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_st.lst new file mode 100644 index 00000000000..393e4802c77 --- /dev/null +++ b/gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_st.lst @@ -0,0 +1,63 @@ +ESP32S2ULP GAS ./gas/testsuite/gas/esp32s2ulp/esp32s2ulp_st.s page 1 + + + 1 + 2 .data //Data section definition + 3 0000 7B00 Addr1: .word 123 // Define label Addr1 16 bit + 4 .set offs, 0x20 // Define constant offs + 5 .set lab1, 0x01 // Define constant offs + 6 + 7 .set offs2, 0x20 // Define constant offs + 8 .set lab2, 0x1 // Define constant offs + 9 .global lab2 + 10 .global offs2 + 11 + 12 + 13 .global __start + 14 __start: + 15 + 16 0002 0000 .text //Text section definition + 17 0000 89210068 STL R1, R2, 0x20 // 89210068 + 18 0004 89210068 STL R1, R2, offs // 89210068 + 19 0008 99200068 STL R1, R2, offs, 1 // 99200068 + 20 000c 99200068 STL R1, R2, offs, lab1 // 99200068 + 21 0010 99000068 STL R1, R2, offs2, lab1 // + 22 0014 89200068 STL R1, R2, offs, lab2 // + 23 0018 89000068 STL R1, R2, offs2, lab2 // + 24 + 25 001c C9210068 STH R1, R2, 0x20 // C9210068 + 26 0020 C9210068 STH R1, R2, offs // C9210068 + 27 0024 D9200068 STH R1, R2, offs, 1 // D9200068 + 28 0028 D9200068 STH R1, R2, offs, lab1 // D9200068 + 29 002c D9000068 STH R1, R2, offs2, lab1 // + 30 0030 C9200068 STH R1, R2, offs, lab2 // + 31 0034 C9000068 STH R1, R2, offs2, lab2 // + 32 0038 00000040 NOP + 33 003c 00000040 NOP + 34 + 35 // ST32 Rdst, Rsrc, offset, label + 36 0040 19100068 ST32 R1, R2, 0x10, 1 // 19100068 + 37 0044 19200068 ST32 R1, R2, offs, lab1 // 19200068 + 38 0048 09200068 ST32 R1, R2, offs, lab2 // 09200068 + 39 004c 09000068 ST32 R1, R2, offs2,lab2 // 09000068 + 40 // STI Rdst, Rsrc, label + 41 0050 19000062 STI32 R1, R2, 1 // 19000062 + 42 0054 19000062 STI32 R1, R2, lab1 // 19000062 + 43 0058 00000040 NOP + 44 005c 89010062 STI R1, R2 // 89010062 + 45 0060 99000062 STI R1, R2, 1 // 99000062 + 46 0064 99000062 STI R1, R2, lab1 // 99000062 + 47 0068 89000062 STI R1, R2, lab2 + 48 006c 00000040 NOP + 49 0070 00200064 STO 0x20 + 50 0074 00200064 STO offs + 51 0078 00000064 STO offs2 + 52 007c 00000040 NOP + 53 0080 00000040 NOP + 54 0084 00000040 NOP + 55 0088 00000040 NOP + 56 + 57 // After operation value at Addr1 will be = 1... + ESP32S2ULP GAS ./gas/testsuite/gas/esp32s2ulp/esp32s2ulp_st.s page 2 + + diff --git a/gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_tsens.lst b/gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_tsens.lst new file mode 100644 index 00000000000..86bf4222f84 --- /dev/null +++ b/gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_tsens.lst @@ -0,0 +1,19 @@ +ESP32S2ULP GAS ./gas/testsuite/gas/esp32s2ulp/esp32s2ulp_tsens.s page 1 + + + 1 .data //Data section definition + 2 0000 7B00 Addr1: .word 123 // Define label Addr1 16 bit + 3 + 4 .set wait_delay1, 0x04 + 5 .set wait_delay2, 0x04 + 6 .global wait_delay2 + 7 + 8 .global __start + 9 __start: + 10 + 11 0002 0000 .text + 12 .global jmp2 + 13 0000 00000040 nop + 14 0004 110000A0 TSENS R1, 0x04 + 15 0008 110000A0 TSENS R1, wait_delay1 + 16 000c 010000A0 TSENS R1, wait_delay2 diff --git a/gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_wait.lst b/gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_wait.lst new file mode 100644 index 00000000000..00296dce4e6 --- /dev/null +++ b/gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_wait.lst @@ -0,0 +1,24 @@ +ESP32S2ULP GAS ./gas/testsuite/gas/esp32s2ulp/esp32s2ulp_wait.s page 1 + + + 1 .data //Data section definition + 2 0000 7B00 Addr1: .word 123 // Define label Addr1 16 bit + 3 .set min_wait1, 0 + 4 .set max_wait1, 0xffff + 5 + 6 .set min_wait2, 0x00 + 7 .set max_wait2, 0xffff + 8 .global min_wait2 + 9 .global max_wait2 + 10 + 11 .global __start + 12 __start: + 13 + 14 0002 0000 .text //Text section definition + 15 + 16 0000 00000040 WAIT 0 + 17 0004 FFFF0040 WAIT 0xffff + 18 0008 00000040 WAIT min_wait1 + 19 000c FFFF0040 WAIT max_wait1 + 20 0010 00000040 WAIT min_wait2 + 21 0014 00000040 WAIT max_wait2 diff --git a/gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_wakehalt.lst b/gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_wakehalt.lst new file mode 100644 index 00000000000..335a61488aa --- /dev/null +++ b/gas/testsuite/gas/esp32s2ulp/compare/esp32s2ulp_wakehalt.lst @@ -0,0 +1,15 @@ +ESP32S2ULP GAS ./gas/testsuite/gas/esp32s2ulp/esp32s2ulp_wakehalt.s page 1 + + + 1 .data //Data section definition + 2 0000 7B00 Addr1: .word 123 // Define label Addr1 16 bit + 3 + 4 + 5 .global __start + 6 __start: + 7 + 8 0002 0000 .text + 9 .global jmp2 + 10 0000 00000040 nop + 11 0004 01000090 wake + 12 0008 000000B0 halt diff --git a/gas/testsuite/gas/esp32s2ulp/esp32s2ulp_adc.s b/gas/testsuite/gas/esp32s2ulp/esp32s2ulp_adc.s new file mode 100644 index 00000000000..3429bd935d8 --- /dev/null +++ b/gas/testsuite/gas/esp32s2ulp/esp32s2ulp_adc.s @@ -0,0 +1,27 @@ + .data //Data section definition +Addr1: .word 123 // Define label Addr1 16 bit + .set min_adc_sel, 0 - 0 + .set max_adc_sel, 1 + 0 + .set min_adc_mux, 0 - 0 + .set max_adc_mux, 15 + 0 + .set min_adc_cyc, 0 - 0 + .set max_adc_cyc, 65535 + 0 + .global min_adc_sel2 + .global max_adc_sel2 + .global min_adc_mux2 + .global max_adc_mux2 + .global min_adc_cyc2 + .global max_adc_cyc2 + .global __start + +__start: + + .text //Text section definition + + ADC R1, 0, 0, 0 + ADC R1, min_adc_sel, min_adc_mux, min_adc_cyc + ADC R1, 1, 15, 0xffff + ADC R1, max_adc_sel, max_adc_mux, max_adc_cyc + + ADC R1, min_adc_sel2, min_adc_mux2, min_adc_cyc2 + ADC R1, max_adc_sel2, max_adc_mux2, max_adc_cyc2 diff --git a/gas/testsuite/gas/esp32s2ulp/esp32s2ulp_alu.s b/gas/testsuite/gas/esp32s2ulp/esp32s2ulp_alu.s new file mode 100644 index 00000000000..d65251ba351 --- /dev/null +++ b/gas/testsuite/gas/esp32s2ulp/esp32s2ulp_alu.s @@ -0,0 +1,52 @@ + .data //Data section definition +Addr1: .word 123 // Define label Addr1 16 bit + + .global __start +__start: + + .text //Text section definition +// Register operations - relative operations + Add R1, R2, R3 + Sub R1, R2, R3 + And R1, R2, R3 + Or R1, R2, R3 + RSH R1, R2, R3 + LSH R1, R2, R3 + MOVE R1, R2 + + .set im_data_d, 0xff + .set im_data_r, 0xff + .global im_data_r + + Add R1, R2, 0xff + Add R1, R2, im_data_d + Add R1, R2, im_data_r + Sub R1, R2, 0xff + Sub R1, R2, im_data_d + Sub R1, R2, im_data_r + And R1, R2, 0xff + And R1, R2, im_data_d + And R1, R2, im_data_r + Or R1, R2, 0xff + Or R1, R2, im_data_d + Or R1, R2, im_data_r + RSH R1, R2, 0xff + RSH R1, R2, im_data_d + RSH R1, R2, im_data_r + LSH R1, R2, 0xff + LSH R1, R2, im_data_d + LSH R1, R2, im_data_r + MOVE R1, 0xff + MOVE R1, im_data_d + MOVE R1, im_data_r + + STAGE_RST + STAGE_INC 0xff + STAGE_INC im_data_d + STAGE_INC im_data_r + STAGE_DEC 0xff + STAGE_DEC im_data_d + STAGE_DEC im_data_r + + + diff --git a/gas/testsuite/gas/esp32s2ulp/esp32s2ulp_i2crw.s b/gas/testsuite/gas/esp32s2ulp/esp32s2ulp_i2crw.s new file mode 100644 index 00000000000..38691987a85 --- /dev/null +++ b/gas/testsuite/gas/esp32s2ulp/esp32s2ulp_i2crw.s @@ -0,0 +1,32 @@ + .data //Data section definition +Addr1: .word 123 // Define label Addr1 16 bit + .set i2c_addr, 0x77 + .set i2c_data1, 0x40 + .set i2c_high, 0x00 + .set i2c_low, 0x01 + .set i2c_sel, 0x00 + .set test_val, 1 + + .set i2c_addr2, 0x77 + .set i2c_data2, 0x40 + .set i2c_high2, 0x00 + .set i2c_low2, 0x01 + .set i2c_sel2, 0x00 + .global i2c_addr2 + .global i2c_data2 + .global i2c_high2 + .global i2c_low2 + .global i2c_sel2 + + .global __start +__start: + + .text //Text section definition + + I2C_WR 0x77, 0x40, 0x00,0x01,0x00 + I2C_WR i2c_addr, i2c_data1, i2c_high,i2c_low,i2c_sel + I2C_WR i2c_addr2, i2c_data2, i2c_high2,i2c_low2,i2c_sel2 + + I2C_RD 0x77, 0x00,0x01,0x00 + I2C_RD i2c_addr, i2c_high,i2c_low,i2c_sel + I2C_RD i2c_addr2, i2c_high2,i2c_low2,i2c_sel2 diff --git a/gas/testsuite/gas/esp32s2ulp/esp32s2ulp_jump.s b/gas/testsuite/gas/esp32s2ulp/esp32s2ulp_jump.s new file mode 100644 index 00000000000..ff1c6ed14c8 --- /dev/null +++ b/gas/testsuite/gas/esp32s2ulp/esp32s2ulp_jump.s @@ -0,0 +1,73 @@ + .data //Data section definition +Addr1: .word 123 // Define label Addr1 16 bit + + .set check_jump1, 0x10 + .set check_jump2, 0x10 + .global check_jump2 + + .set check_thres1, 0x04 + .set check_thres2, 0x04 + .global check_thres2 + + + .global __start +__start: + + .text + .global jmp2 + nop +jmp1: +jmp2: nop + jump 0x04 + jump check_jump1 + jump check_jump2 + jump R1 + jump 0x04, EQ + jump check_jump1, EQ + jump check_jump2, EQ + jump R1, EQ + jump 0x04, OV + jump check_jump1, OV + jump check_jump2, OV + jump R1, OV +// Jump to labele + jump jmp1, EQ + jump jmp2, EQ + jump jmp1, OV + jump jmp2, OV + +// Relative Jump + JUMPR 0x04, 0x4, LT + JUMPR check_jump1, 0x4, LT + JUMPR 0x04, check_thres1, LT + JUMPR check_jump1, check_thres1, LT + JUMPR check_jump2, check_thres1, LT + JUMPR check_jump2, check_thres2, LT + JUMPR 0x04, 0x4, GT + JUMPR check_jump1, 0x4, GT + JUMPR 0x04, check_thres1, GT + JUMPR check_jump1, check_thres1, GT + JUMPR check_jump2, check_thres1, GT + JUMPR check_jump2, check_thres2, GT + JUMPR 0x04, 0x4, EQ + JUMPR check_jump1, 0x4, EQ + JUMPR 0x04, check_thres1, EQ + JUMPR check_jump1, check_thres1, EQ + JUMPR check_jump2, check_thres1, EQ + JUMPR check_jump2, check_thres2, EQ + +// Jumps commands... + jumps 0x4, 0x04, EQ + jumps 0x04, check_thres1, EQ + jumps check_jump1, check_thres1, EQ + jumps check_jump1, check_thres2, EQ + jumps check_jump2, check_thres1, EQ + jumps check_jump2, check_thres2, EQ + + jumps 0x0, 0x00, EQ + jumps 0x0, 0x00, LT + jumps 0x0, 0x00, GT + jumps 0x0, 0x00, LE + jumps 0x0, 0x00, GE + + diff --git a/gas/testsuite/gas/esp32s2ulp/esp32s2ulp_ld.s b/gas/testsuite/gas/esp32s2ulp/esp32s2ulp_ld.s new file mode 100644 index 00000000000..a48ada8eeba --- /dev/null +++ b/gas/testsuite/gas/esp32s2ulp/esp32s2ulp_ld.s @@ -0,0 +1,22 @@ + + .data //Data section definition +Addr1: .word 123 // Define label Addr1 16 bit + .set offs, 0x20 // Define constant offs + + .set offs2, 0x20 // Define constant offs + .global offs2 + + + .global __start +__start: + + .text //Text section definition + LD R1, R2, 0x20 + LD R1, R2, offs + LD R1, R2, offs2 + LDL R1, R2, 0x20 + LDL R1, R2, offs + LDL R1, R2, offs2 + LDH R1, R2, 0x20 + LDH R1, R2, offs + LDH R1, R2, offs2 diff --git a/gas/testsuite/gas/esp32s2ulp/esp32s2ulp_regrw.s b/gas/testsuite/gas/esp32s2ulp/esp32s2ulp_regrw.s new file mode 100644 index 00000000000..ca2dd63e7b8 --- /dev/null +++ b/gas/testsuite/gas/esp32s2ulp/esp32s2ulp_regrw.s @@ -0,0 +1,48 @@ + .data //Data section definition +Addr1: .word 123 // Define label Addr1 16 bit + .set offs, 0x20 // Define constant offs + .set lab1, 0x01 // Define constant offs + + .set offs2, 0x20 // Define constant offs + .set lab2, 0x1 // Define constant offs + .global lab2 + .global offs2 + + + .global __start +__start: + + .text //Text section definition + + .set min_reg_Addr, 0 - 0 + .set max_reg_Addr, 0x3ff + 0 + .set min_reg_High, 0 - 0 + .set max_reg_High, 31 + 0 + .set min_reg_Low, 0 - 0 + .set max_reg_Low, 31 + 0 + .set min_reg_data, 0 - 0 + .set max_reg_data, 255 + 0 + + REG_RD 0, 0, 0 + REG_RD 0x3ff, 31, 31 + REG_WR 0, 0, 0, 0 + REG_WR 0x3ff, 31, 31, 255 + + REG_RD min_reg_Addr, min_reg_High, min_reg_Low + REG_RD max_reg_Addr, max_reg_High, max_reg_Low + REG_WR min_reg_Addr, min_reg_High, min_reg_Low, min_reg_data + REG_WR max_reg_Addr, max_reg_High, max_reg_Low, max_reg_data + + .global min_reg_Addr2 + .global max_reg_Addr2 + .global min_reg_High2 + .global max_reg_High2 + .global min_reg_Low2 + .global max_reg_Low2 + .global min_reg_data2 + .global max_reg_data2 + + REG_RD min_reg_Addr2, min_reg_High2, min_reg_Low2 + REG_RD max_reg_Addr2, max_reg_High2, max_reg_Low2 + REG_WR min_reg_Addr2, min_reg_High2, min_reg_Low2, min_reg_data2 + REG_WR max_reg_Addr2, max_reg_High2, max_reg_Low2, max_reg_data2 diff --git a/gas/testsuite/gas/esp32s2ulp/esp32s2ulp_sleep.s b/gas/testsuite/gas/esp32s2ulp/esp32s2ulp_sleep.s new file mode 100644 index 00000000000..10a9499b799 --- /dev/null +++ b/gas/testsuite/gas/esp32s2ulp/esp32s2ulp_sleep.s @@ -0,0 +1,16 @@ + .data //Data section definition +Addr1: .word 123 // Define label Addr1 16 bit + + .set wait_delay1, 0x04 + .set wait_delay2, 0x04 + .global wait_delay2 + + .global __start +__start: + + .text + .global jmp2 + nop + SLEEP 0x04 + SLEEP wait_delay1 + SLEEP wait_delay2 diff --git a/gas/testsuite/gas/esp32s2ulp/esp32s2ulp_st.s b/gas/testsuite/gas/esp32s2ulp/esp32s2ulp_st.s new file mode 100644 index 00000000000..fc7452e755e --- /dev/null +++ b/gas/testsuite/gas/esp32s2ulp/esp32s2ulp_st.s @@ -0,0 +1,57 @@ + + .data //Data section definition +Addr1: .word 123 // Define label Addr1 16 bit + .set offs, 0x20 // Define constant offs + .set lab1, 0x01 // Define constant offs + + .set offs2, 0x20 // Define constant offs + .set lab2, 0x1 // Define constant offs + .global lab2 + .global offs2 + + + .global __start +__start: + + .text //Text section definition + STL R1, R2, 0x20 // 89210068 + STL R1, R2, offs // 89210068 + STL R1, R2, offs, 1 // 99200068 + STL R1, R2, offs, lab1 // 99200068 + STL R1, R2, offs2, lab1 // + STL R1, R2, offs, lab2 // + STL R1, R2, offs2, lab2 // + + STH R1, R2, 0x20 // C9210068 + STH R1, R2, offs // C9210068 + STH R1, R2, offs, 1 // D9200068 + STH R1, R2, offs, lab1 // D9200068 + STH R1, R2, offs2, lab1 // + STH R1, R2, offs, lab2 // + STH R1, R2, offs2, lab2 // + NOP + NOP + +// ST32 Rdst, Rsrc, offset, label + ST32 R1, R2, 0x10, 1 // 19100068 + ST32 R1, R2, offs, lab1 // 19200068 + ST32 R1, R2, offs, lab2 // 09200068 + ST32 R1, R2, offs2,lab2 // 09000068 +// STI Rdst, Rsrc, label + STI32 R1, R2, 1 // 19000062 + STI32 R1, R2, lab1 // 19000062 + NOP + STI R1, R2 // 89010062 + STI R1, R2, 1 // 99000062 + STI R1, R2, lab1 // 99000062 + STI R1, R2, lab2 + NOP + STO 0x20 + STO offs + STO offs2 + NOP + NOP + NOP + NOP + +// After operation value at Addr1 will be = 1 \ No newline at end of file diff --git a/gas/testsuite/gas/esp32s2ulp/esp32s2ulp_tsens.s b/gas/testsuite/gas/esp32s2ulp/esp32s2ulp_tsens.s new file mode 100644 index 00000000000..be4125ca7ad --- /dev/null +++ b/gas/testsuite/gas/esp32s2ulp/esp32s2ulp_tsens.s @@ -0,0 +1,16 @@ + .data //Data section definition +Addr1: .word 123 // Define label Addr1 16 bit + + .set wait_delay1, 0x04 + .set wait_delay2, 0x04 + .global wait_delay2 + + .global __start +__start: + + .text + .global jmp2 + nop + TSENS R1, 0x04 + TSENS R1, wait_delay1 + TSENS R1, wait_delay2 diff --git a/gas/testsuite/gas/esp32s2ulp/esp32s2ulp_wait.s b/gas/testsuite/gas/esp32s2ulp/esp32s2ulp_wait.s new file mode 100644 index 00000000000..b5ad51f2900 --- /dev/null +++ b/gas/testsuite/gas/esp32s2ulp/esp32s2ulp_wait.s @@ -0,0 +1,21 @@ + .data //Data section definition +Addr1: .word 123 // Define label Addr1 16 bit + .set min_wait1, 0 + .set max_wait1, 0xffff + + .set min_wait2, 0x00 + .set max_wait2, 0xffff + .global min_wait2 + .global max_wait2 + + .global __start +__start: + + .text //Text section definition + + WAIT 0 + WAIT 0xffff + WAIT min_wait1 + WAIT max_wait1 + WAIT min_wait2 + WAIT max_wait2 diff --git a/gas/testsuite/gas/esp32s2ulp/esp32s2ulp_wakehalt.s b/gas/testsuite/gas/esp32s2ulp/esp32s2ulp_wakehalt.s new file mode 100644 index 00000000000..e809b593928 --- /dev/null +++ b/gas/testsuite/gas/esp32s2ulp/esp32s2ulp_wakehalt.s @@ -0,0 +1,13 @@ + .data //Data section definition +Addr1: .word 123 // Define label Addr1 16 bit + + + .global __start +__start: + + .text + .global jmp2 + nop + wake + halt + \ No newline at end of file diff --git a/gas/testsuite/gas/esp32s2ulp/esp32ulp_globals.s b/gas/testsuite/gas/esp32s2ulp/esp32ulp_globals.s new file mode 100644 index 00000000000..59e3aa92d66 --- /dev/null +++ b/gas/testsuite/gas/esp32s2ulp/esp32ulp_globals.s @@ -0,0 +1,96 @@ + .text + .global min_add1 + .global max_add2 + + .set min_add1, -32768 + .set max_add2, 32767 + + .set min_wait2, 0 + .set max_wait2, 65535 +0 + .global min_wait2 + .global max_wait2 + + .set min_jump2, 0 + .set max_jump2, 2047+0 + .global min_jump2 + .global max_jump2 + + .set min_jumpr2, -40- 0 + .set max_jumpr2, 80 + 0 + .set min_thresh2, -32768 + .set max_thresh2, 32767 + .global min_jumpr2 + .global max_jumpr2 + .global min_thresh2 + .global max_thresh2 + + .set min_threshs3, -128-0 + .set max_threshs3, 127+0 + .global min_threshs3 + .global max_threshs3 + + + .set min_wr_mem2, 0 - 0 + .set max_wr_mem2, 2047 + 0 + .global min_wr_mem2 + .global max_wr_mem2 + + .set min_sleep2, 0 - 0 + .set max_sleep2, 15 + 0 + .global min_sleep2 + .global max_sleep2 + + .set min_wake2, 0 - 0 + .set max_wake2, 1 + 0 + .global min_wake2 + .global max_wake2 + + + .set min_tsens_meas2, 0 - 0 + .set max_tsens_meas2, 4095 + 0 + .set min_tsens_wait2, 0 - 0 + .set max_tsens_wait2, 16383 + 0 + .global min_tsens_meas2 + .global max_tsens_meas2 + .global min_tsens_wait2 + .global max_tsens_wait2 + + .set min_adc_sel2, 0 - 0 + .set max_adc_sel2, 1 + 0 + .set min_adc_mux2, 0 - 0 + .set max_adc_mux2, 15 + 0 + .set min_adc_cyc2, 0 - 0 + .set max_adc_cyc2, 65535 + 0 + + .global min_adc_sel2 + .global max_adc_sel2 + .global min_adc_mux2 + .global max_adc_mux2 + .global min_adc_cyc2 + .global max_adc_cyc2 + + .set min_reg_Addr2, 0 - 0 + .set max_reg_Addr2, 1023 + 0 + .set min_reg_High2, 0 - 0 + .set max_reg_High2, 31 + 0 + .set min_reg_Low2, 0 - 0 + .set max_reg_Low2, 31 + 0 + .set min_reg_data2, 0 - 0 + .set max_reg_data2, 255 + 0 + .global min_reg_Addr2 + .global max_reg_Addr2 + .global min_reg_High2 + .global max_reg_High2 + .global min_reg_Low2 + .global max_reg_Low2 + .global min_reg_data2 + .global max_reg_data2 + + + + .global _temp_dataw + _temp_dataw: .int 1111 + .global _temp_dataw331 + _temp_dataw331: .int 1234567 + .global _temp_dataw2 + _temp_dataw2: .int 1234567 diff --git a/gdb/Makefile.in b/gdb/Makefile.in index f13709c57cf..3fbd86574bc 100644 --- a/gdb/Makefile.in +++ b/gdb/Makefile.in @@ -718,6 +718,7 @@ ALL_TARGET_OBS = \ bfin-linux-tdep.o \ bfin-tdep.o \ esp32ulp-tdep.o \ + esp32s2ulp-tdep.o \ bsd-uthread.o \ cris-linux-tdep.o \ cris-tdep.o \ @@ -1223,6 +1224,7 @@ HFILES_NO_SRCDIR = \ bfd-target.h \ bfin-tdep.h \ esp32ulp-tdep.h \ + esp32s2ulp-tdep.h \ block.h \ breakpoint.h \ bsd-kvm.h \ diff --git a/gdb/configure.tgt b/gdb/configure.tgt index 8133051c124..b53fd0d2631 100644 --- a/gdb/configure.tgt +++ b/gdb/configure.tgt @@ -210,6 +210,11 @@ esp32ulp-*-*) gdb_target_obs="esp32ulp-tdep.o" ;; +esp32s2ulp-*-*) + # Target: Esp32-s2ulp processor + gdb_target_obs="esp32s2ulp-tdep.o" + ;; + cris*) # Target: CRIS gdb_target_obs="cris-tdep.o cris-linux-tdep.o linux-tdep.o solib-svr4.o" diff --git a/gdb/esp32s2ulp-tdep.c b/gdb/esp32s2ulp-tdep.c new file mode 100644 index 00000000000..c47a497b179 --- /dev/null +++ b/gdb/esp32s2ulp-tdep.c @@ -0,0 +1,2 @@ +// Just for future +// esp32s2ulp \ No newline at end of file diff --git a/gdb/esp32s2ulp-tdep.h b/gdb/esp32s2ulp-tdep.h new file mode 100644 index 00000000000..bdd5ae946a2 --- /dev/null +++ b/gdb/esp32s2ulp-tdep.h @@ -0,0 +1 @@ +// Just for future \ No newline at end of file diff --git a/gdb/esp32ulp-tdep.c b/gdb/esp32ulp-tdep.c old mode 100755 new mode 100644 index bdd5ae946a2..1d5abb6024b --- a/gdb/esp32ulp-tdep.c +++ b/gdb/esp32ulp-tdep.c @@ -1 +1,2 @@ -// Just for future \ No newline at end of file +// Just for future +// esp32ulp \ No newline at end of file diff --git a/gdb/syscalls/esp32ulp-linux.xml.in b/gdb/syscalls/esp32ulp-linux.xml.in old mode 100755 new mode 100644 index a499ec4c1cb..42863453983 --- a/gdb/syscalls/esp32ulp-linux.xml.in +++ b/gdb/syscalls/esp32ulp-linux.xml.in @@ -323,4 +323,5 @@ + diff --git a/include/dis-asm.h b/include/dis-asm.h index 0532cefa951..cac106c7e92 100644 --- a/include/dis-asm.h +++ b/include/dis-asm.h @@ -280,6 +280,8 @@ typedef int (*disassembler_ftype) (bfd_vma, disassemble_info *); /* Disassemblers used out side of opcodes library. */ extern int print_insn_m32c (bfd_vma, disassemble_info *); +extern int print_insn_esp32ulp (bfd_vma, disassemble_info *); +extern int print_insn_esp32s2ulp (bfd_vma, disassemble_info *); extern int print_insn_mep (bfd_vma, disassemble_info *); extern int print_insn_s12z (bfd_vma, disassemble_info *); extern int print_insn_sh (bfd_vma, disassemble_info *); diff --git a/include/elf/common.h b/include/elf/common.h index 9e49d8060a2..b5f54c6e9d8 100644 --- a/include/elf/common.h +++ b/include/elf/common.h @@ -217,6 +217,7 @@ #define EM_MSP430 105 /* TI msp430 micro controller */ #define EM_BLACKFIN 106 /* ADI Blackfin */ #define EM_ESP32ULP 245 /* ESP32ULP */ +#define EM_ESP32S2ULP 246 /* ESP32S2ULP */ #define EM_SE_C33 107 /* S1C33 Family of Seiko Epson processors */ #define EM_SEP 108 /* Sharp embedded microprocessor */ #define EM_ARCA 109 /* Arca RISC Microprocessor */ diff --git a/include/elf/esp32s2ulp.h b/include/elf/esp32s2ulp.h new file mode 100644 index 00000000000..c13ff98486d --- /dev/null +++ b/include/elf/esp32s2ulp.h @@ -0,0 +1,86 @@ +/* ESP32-S2ULP ELF support for BFD. + Copyright (c) 2016-2017 Espressif Systems (Shanghai) PTE LTD. + + based on Copyright (C) 2005-2017 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_ESP32S2ULP_H +#define _ELF_ESP32S2ULP_H + +#include "elf/reloc-macros.h" + +//#ifndef DEBUG_TRACE +//#define DEBUG_TRACE //printf +//#endif //DEBUG_TRACE + +START_RELOC_NUMBERS (elf_esp32s2ulp_reloc_type) + RELOC_NUMBER (R_ESP32S2ULP_UNUSED0, 0x00) + RELOC_NUMBER(R_ESP32S2ULP_RIMM16, 0x01) + RELOC_NUMBER(R_ESP32S2ULP_JUMPR, 0x02) + RELOC_NUMBER(R_ESP32S2ULP_LOAD16, 0x03) + RELOC_NUMBER(R_ESP32S2ULP_WR_MEM, 0x04) + RELOC_NUMBER(R_ESP32S2ULP_ALUI, 0x05) + RELOC_NUMBER(R_ESP32S2ULP_WAIT, 0x06) + RELOC_NUMBER(R_ESP32S2ULP_TSENS_CYCLE, 0x07) + RELOC_NUMBER(R_ESP32S2ULP_TSENS_DELAY, 0x08) + + RELOC_NUMBER(R_ESP32S2ULP_ADC_CYCLE, 0x09) + RELOC_NUMBER(R_ESP32S2ULP_ADC_SEL, 0x0A) + RELOC_NUMBER(R_ESP32S2ULP_ADC_MUX, 0x0B) + RELOC_NUMBER(R_ESP32S2ULP_WAKE, 0x0C) + RELOC_NUMBER(R_ESP32S2ULP_SLEEP, 0x0D) + RELOC_NUMBER(R_ESP32S2ULP_STAGE, 0x0E) + + RELOC_NUMBER(R_ESP32S2ULP_JUMPR_STEP, 0x0F) + RELOC_NUMBER(R_ESP32S2ULP_JUMPR_THRESH, 0x10) + RELOC_NUMBER(R_ESP32S2ULP_JUMPS_THRESH, 0x11) + + RELOC_NUMBER(R_ESP32S2ULP_REG_RW_HIGH, 0x12) + RELOC_NUMBER(R_ESP32S2ULP_REG_RW_LOW, 0x13) + RELOC_NUMBER(R_ESP32S2ULP_REG_RW_ADDR, 0x14) + RELOC_NUMBER(R_ESP32S2ULP_REG_RW_DATA, 0x15) + + RELOC_NUMBER(R_ESP32S2ULP_I2C_RW_HIGH, 0x16) + RELOC_NUMBER(R_ESP32S2ULP_I2C_RW_LOW, 0x17) + RELOC_NUMBER(R_ESP32S2ULP_I2C_RW_ADDR, 0x18) + RELOC_NUMBER(R_ESP32S2ULP_I2C_RW_DATA, 0x19) + RELOC_NUMBER(R_ESP32S2ULP_I2C_RW_SEL, 0x1A) + + RELOC_NUMBER(R_ESP32S2ULP_WR_MEM_LABEL, 0x1B) + + RELOC_NUMBER(R_ESP32S2ULP_RESERVE, 0x1C) + RELOC_NUMBER(R_ESP32S2ULP_PLTPC, 0x40) /* PLT gnu only relocation */ + RELOC_NUMBER(R_ESP32S2ULP_GOT, 0x41) /* GOT gnu only relocation */ + RELOC_NUMBER(R_ESP32S2ULP_GNU_VTINHERIT, 0x42) /* C++, gnu only */ + RELOC_NUMBER(R_ESP32S2ULP_GNU_VTENTRY, 0x43) /* C++, gnu only */ + END_RELOC_NUMBERS(R_ESP32S2ULP_max) + +/* Processor specific flags for the ELF header e_flags field. */ +#define EF_ESP32S2ULP_PIC 0x00000001 /* -fpic */ +#define EF_ESP32S2ULP_FDPIC 0x00000002 /* -mfdpic */ + +#define EF_ESP32S2ULP_CODE_IN_L1 0x00000010 /* --code-in-l1 */ +#define EF_ESP32S2ULP_DATA_IN_L1 0x00000020 /* --data-in-l1 */ + +#define EF_ESP32S2ULP_PIC_FLAGS (EF_ESP32S2ULP_PIC | EF_ESP32S2ULP_FDPIC) + +#define DR_REG_MAX_DIRECT 0x3ff +#define DR_REG_RTCCNTL_BASE 0x3ff48000 +#define DR_REG_IO_MUX_BASE 0x3ff49000 + +#endif /* _ELF_ESP32S2ULP_H */ diff --git a/include/opcode/esp32s2ulp.h b/include/opcode/esp32s2ulp.h new file mode 100644 index 00000000000..b8d9a39b7e4 --- /dev/null +++ b/include/opcode/esp32s2ulp.h @@ -0,0 +1,409 @@ +/* esp32s2ulp.h -- Header file for ESP32S2ULP opcode table + + Copyright (c) 2016-2017 Espressif Systems (Shanghai) PTE LTD. + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version 3, + or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING3. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef OPCODE_ESP32S2ULP_H +#define OPCODE_ESP32S2ULP_H + +// ==================== I_ALUR ============================ + +#define OPCODE_ALU 7 /*!< Arithmetic instructions */ +#define SUB_OPCODE_ALU_REG 0 /*!< Arithmetic instruction, both source values are in register */ +#define SUB_OPCODE_ALU_IMM 1 /*!< Arithmetic instruction, one source value is an immediate */ +#define SUB_OPCODE_ALU_CNT 2 /*!< Arithmetic instruction between counter register and an immediate (not implemented yet)*/ +#define ALU_SEL_ADD 0 /*!< Addition */ +#define ALU_SEL_SUB 1 /*!< Subtraction */ +#define ALU_SEL_AND 2 /*!< Logical AND */ +#define ALU_SEL_OR 3 /*!< Logical OR */ +#define ALU_SEL_MOV 4 /*!< Copy value (immediate to destination register or source register to destination register */ +#define ALU_SEL_LSH 5 /*!< Shift left by given number of bits */ +#define ALU_SEL_RSH 6 /*!< Shift right by given number of bits */ +#define ALU_SEL_SINC 0 +#define ALU_SEL_SDEC 1 +#define ALU_SEL_SRST 2 + +typedef struct { + unsigned int dreg : 2; /*!< Destination register */ + unsigned int sreg : 2; /*!< Register with operand A */ + unsigned int treg : 2; /*!< Register with operand B */ + unsigned int unused : 15; /*!< Unused */ + unsigned int sel : 4; /*!< Operation to perform, one of ALU_SEL_xxx */ + unsigned int unused2 : 1; /*!< Unused */ + unsigned int sub_opcode : 2; /*!< Sub opcode (SUB_OPCODE_ALU_REG) */ + unsigned int opcode : 4; /*!< Opcode (OPCODE_ALU) */ +} alu_reg; /*!< Format of ALU instruction (both sources are registers) */ + + +#define I_ALUR(reg_dest, reg_src1, reg_src2, op_sel) { *(unsigned int*)&(alu_reg ){ \ + .dreg = reg_dest, \ + .sreg = reg_src1, \ + .treg = reg_src2, \ + .unused = 0, \ + .sel = op_sel, \ + .sub_opcode = SUB_OPCODE_ALU_REG, \ + .opcode = OPCODE_ALU } } + + +// ==================== I_ALUI ============================ + +typedef struct { + unsigned int dreg : 2; /*!< Destination register */ + unsigned int sreg : 2; /*!< Register with operand A */ + unsigned int imm : 16; /*!< imm value */ + unsigned int unused : 1; /*!< Unused */ + unsigned int sel : 4; /*!< Operation to perform, one of ALU_SEL_xxx */ + unsigned int unused2 : 1; /*!< Unused */ + unsigned int sub_opcode : 2; /*!< Sub opcode (SUB_OPCODE_ALU_REG) */ + unsigned int opcode : 4; /*!< Opcode (OPCODE_ALU) */ +} alu_reg_i; /*!< Format of ALU instruction (both sources are registers) */ + + + +#define I_ALUI(reg_dest, reg_src1, imme, op_sel) { *(unsigned int*)&(alu_reg_i ){ \ + .dreg = reg_dest, \ + .sreg = reg_src1, \ + .imm = imme, \ + .unused = 0, \ + .sel = op_sel, \ + .sub_opcode = SUB_OPCODE_ALU_IMM, \ + .opcode = OPCODE_ALU } } + +// ==================== I_ALUS ============================ + +typedef struct { + unsigned int unused1 : 4; /*!< Destination register */ + unsigned int imm : 8; /*!< imm value */ + unsigned int unused2 : 9; /*!< Unused */ + unsigned int sel : 4; /*!< Operation to perform, one of ALU_SEL_xxx */ + unsigned int unused3 : 1; /*!< Unused */ + unsigned int sub_opcode : 2; /*!< Sub opcode (SUB_OPCODE_ALU_REG) */ + unsigned int opcode : 4; /*!< Opcode (OPCODE_ALU) */ +} alu_reg_s; /*!< Format of ALU instruction (both sources are registers) */ + + + +#define I_ALUS(op_sel, imme) { *(unsigned int*)&(alu_reg_s ){ \ + .unused1 = 0, \ + .imm = imme, \ + .unused2 = 0, \ + .sel = op_sel, \ + .unused3 = 0, \ + .sub_opcode = SUB_OPCODE_ALU_CNT, \ + .opcode = OPCODE_ALU } } + +// ------------------ Jump ------------------------ + +typedef struct { + unsigned int dreg : 2; /*!< Register which contains target PC, expressed in words (used if .reg == 1) */ + unsigned int addr : 11; /*!< Target PC, expressed in words (used if .reg == 0) */ + unsigned int unused : 8; /*!< Unused */ + unsigned int reg : 1; /*!< Target PC in register (1) or immediate (0) */ + unsigned int type : 3; /*!< Jump condition (BX_JUMP_TYPE_xxx) */ + unsigned int unused2 : 1; /*!< Target PC in register (1) or immediate (0) */ + unsigned int sub_opcode : 2; /*!< Sub opcode (SUB_OPCODE_BX) */ + unsigned int opcode : 4; /*!< Opcode (OPCODE_BRANCH) */ +} jump_alu_ri; /*!< Format of ALU instruction (both sources are registers) */ + +#define OPCODE_BRANCH 8 /*!< Branch instructions */ +#define SUB_OPCODE_BX 1 /*!< Branch to absolute PC (immediate or in register) */ +#define SUB_OPCODE_BR 0 /*!< Branch to relative PC */ +#define SUB_OPCODE_BS 2 /*!< Branch to relative PC */ + +#define I_JUMP_RI(reg_pc, imm_pc, cond, mode) { *(unsigned int*)&(jump_alu_ri ){ \ + .dreg = reg_pc, \ + .addr = imm_pc, \ + .unused = 0, \ + .reg = mode,\ + .unused2 = 0,\ + .type = cond,\ + .sub_opcode = SUB_OPCODE_BX, \ + .opcode = OPCODE_BRANCH } } + + +// ------------------ Jump relr ------------------------ + +typedef struct { + unsigned int threshold : 16; + unsigned int judge : 2; + unsigned int step: 8; + unsigned int sub_opcode : 2; /*!< Sub opcode (SUB_OPCODE_BX) */ + unsigned int opcode : 4; /*!< Opcode (OPCODE_BRANCH) */ +} jump_alu_relr; /*!< Format of ALU instruction */ + + +#define I_JUMP_RELR(thresh, jud, stp) { *(unsigned int*)&(jump_alu_relr ){ \ + .threshold = thresh, \ + .judge = jud, \ + .step = stp, \ + .sub_opcode = SUB_OPCODE_BR, \ + .opcode = OPCODE_BRANCH } } + +// ------------------ Jump rels ------------------------ + +typedef struct { + unsigned int threshold : 8; + unsigned int unused : 7; + unsigned int judge : 3; + unsigned int step : 8; + unsigned int sub_opcode : 2; /*!< Sub opcode (SUB_OPCODE_BX) */ + unsigned int opcode : 4; /*!< Opcode (OPCODE_BRANCH) */ +} jump_alu_rels; /*!< Format of ALU instruction */ + + +#define I_JUMP_RELS(thresh, jud, stp) { *(unsigned int*)&(jump_alu_rels ){ \ + .threshold = thresh, \ + .unused = 0, \ + .judge = jud, \ + .step = stp, \ + .sub_opcode = SUB_OPCODE_BS, \ + .opcode = OPCODE_BRANCH } } + +// ------------------ wr_mem ------------------------ +#define OPCODE_ST 6 /*!< Instruction: store indirect to RTC memory */ +#define SUB_OPCODE_ST 4 /*!< Store 32 bits, 16 MSBs contain PC, 16 LSBs contain value from source register */ + +typedef struct { + unsigned int dreg : 2; + unsigned int sreg : 2; + unsigned int label : 2; + unsigned int high_low : 1; + unsigned int write_way : 2; + unsigned int unused1: 1; + unsigned int offset : 11; + unsigned int unused2 : 4; + unsigned int sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_BX) */ + unsigned int opcode : 4; /*!< Opcode (OPCODE_BRANCH) */ +} wr_mem; /*!< Format of ALU instruction */ + + +#define WR_MEM(dest, src, offs, labl, hl, way, sub) { *(unsigned int*)&(wr_mem ){ \ + .dreg = dest, \ + .sreg = src, \ + .label = labl, \ + .high_low = hl, \ + .write_way = way, \ + .unused1 = 0, \ + .offset = offs, \ + .unused2 = 0, \ + .sub_opcode = sub, \ + .opcode = OPCODE_ST } } + +// ------------------ rd_mem ------------------------ +#define OPCODE_LD 13 /*!< Instruction: store indirect to RTC memory */ +#define SUB_OPCODE_LD 0 /*!< Store 32 bits, 16 MSBs contain PC, 16 LSBs contain value from source register */ + +typedef struct { + unsigned int dreg : 2; + unsigned int sreg : 2; + unsigned int unused1 : 6; + unsigned int offset : 11; + unsigned int unused2 : 6; + unsigned int sub_opcode : 1; /*!< Sub opcode (SUB_OPCODE_BX) */ + unsigned int opcode : 4; /*!< Opcode (OPCODE_BRANCH) */ +} rd_mem; /*!< Format of ALU instruction */ + + +#define RD_MEM(lh,dest, src, offs) { *(unsigned int*)&(rd_mem ){ \ + .dreg = dest, \ + .sreg = src, \ + .unused1 = 0, \ + .offset = offs, \ + .unused2 = 0, \ + .sub_opcode = lh, \ + .opcode = OPCODE_LD } } + + +// ------------------ halt ------------------------ +#define OPCODE_HALT 11 /*!< Instruction: store indirect to RTC memory */ + +typedef struct { + unsigned int unused : 28; + unsigned int opcode : 4; /*!< Opcode (OPCODE_BRANCH) */ +} cmd_halt; /*!< Format of ALU instruction */ + + +#define OP_CMD_HALT() { *(unsigned int*)&(cmd_halt ){ \ + .unused = 0, \ + .opcode = OPCODE_HALT } } + +// ------------------ WAKEUP ------------------------ +#define OPCODE_EXIT 9 /*!< Stop executing the program (not implemented yet) */ +#define SUB_OPCODE_WAKEUP 0 /*!< Stop executing the program and optionally wake up the chip */ + +typedef struct { + unsigned int wakeup : 1; /*!< Set to 1 to wake up chip */ + unsigned int unused : 24; /*!< Unused */ + unsigned int sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_WAKEUP) */ + unsigned int opcode : 4; /*!< Opcode (OPCODE_END) */ +} cmd_wakeup; /*!< Format of END instruction with wakeup */ + + +#define OP_CMD_WAKEUP(wake) { *(unsigned int*)&(cmd_wakeup ){ \ + .wakeup = wake, \ + .unused = 0,\ + .sub_opcode = SUB_OPCODE_WAKEUP,\ + .opcode = OPCODE_EXIT } } + + +// ------------------ SLEEP ------------------------ + +typedef struct { + unsigned int cycle_sel : 16; /*!< Select which one of SARADC_ULP_CP_SLEEP_CYCx_REG to get the sleep duration from */ + unsigned int unused : 12; /*!< Unused */ + unsigned int opcode : 4; /*!< Opcode (OPCODE_END) */ +} cmd_sleep; /*!< Format of END instruction with wakeup */ + +#define OPCODE_SLEEP 4 + +#define OP_CMD_SLEEP(sleep) { *(unsigned int*)&(cmd_sleep ){ \ + .cycle_sel = sleep, \ + .unused = 0,\ + .opcode = OPCODE_SLEEP } } + +// ------------------ TSENS ------------------------ +#define OPCODE_TSENS 10 /*!< Instruction: temperature sensor measurement (not implemented yet) */ + +typedef struct { + unsigned int dreg : 2; /*!< Register where to store temperature measurement result */ + unsigned int wait_delay : 14; /*!< Cycles to wait after measurement is done */ + unsigned int cycles : 12; /*!< Cycles used to perform measurement */ + unsigned int opcode : 4; /*!< Opcode (OPCODE_TSENS) */ +} cmd_tsens; /*!< Format of TSENS instruction */ + + +#define OP_CMD_TSENS(dreg, delay) { *(unsigned int*)&(cmd_tsens ){ \ + .dreg = dreg, \ + .wait_delay = delay,\ + .cycles = 0,\ + .opcode = OPCODE_TSENS } } + + +// ------------------ WAIT ------------------------ +#define OPCODE_WAIT 4 /*!< Instruction: delay (nop) for a given number of cycles */ + +typedef struct { + unsigned int wait : 16; /*!< Set to 1 to wake up chip */ + unsigned int unused : 12; /*!< Unused */ + unsigned int opcode : 4; /*!< Opcode (OPCODE_WAIT) */ +} cmd_wait; /*!< Format of END instruction with wakeup */ + + +#define OP_CMD_WAIT(cyc) { *(unsigned int*)&(cmd_wait ){ \ + .wait = cyc, \ + .unused = 0,\ + .opcode = OPCODE_WAIT } } + +// ------------------ MEAS ------------------------ +#define OPCODE_ADC 5 /*!< Instruction: SAR ADC measurement (not implemented yet) */ + +typedef struct{ + unsigned int dreg : 2; /*!< Register where to store ADC result */ + unsigned int sar_mux : 4; /*!< Select SARADC pad (mux + 1) */ + unsigned int sar_sel : 1; /*!< Select SARADC0 (0) or SARADC1 (1) */ + unsigned int unused1 : 1; /*!< Unused */ + unsigned int cycles : 16; /*!< TBD, cycles used for measurement */ + unsigned int unused2 : 4; /*!< Unused */ + unsigned int opcode : 4; /*!< Opcode (OPCODE_ADC) */ +} cmd_adc; + +#define OP_CMD_ADC(d_reg, mux, sel) { *(unsigned int*)&(cmd_adc ){ \ + .dreg = d_reg, \ + .sar_mux = mux, \ + .sar_sel = sel, \ + .unused1 = 0, \ + .cycles = 0, \ + .unused2 = 0, \ + .opcode = OPCODE_ADC } } + +// ------------------ RD/WR reg ------------------------ +#define OPCODE_WR_REG 1 /*!< Instruction: write peripheral register (RTC_CNTL/RTC_IO/SARADC) (not implemented yet) */ + +#define OPCODE_RD_REG 2 /*!< Instruction: read peripheral register (RTC_CNTL/RTC_IO/SARADC) (not implemented yet) */ + +typedef struct{ + unsigned int addr : 10; /*!< Address within either RTC_CNTL, RTC_IO, or SARADC */ + unsigned int data : 8; /*!< 8 bits of data to write */ + unsigned int low : 5; /*!< Low bit */ + unsigned int high : 5; /*!< High bit */ + unsigned int opcode : 4; /*!< Opcode (OPCODE_WR_REG) */ +} cmd_wr_reg; /*!< Format of WR_REG instruction */ + +typedef struct { + unsigned int addr : 10; /*!< Address within either RTC_CNTL, RTC_IO, or SARADC */ + unsigned int unused : 8; /*!< Unused */ + unsigned int low : 5; /*!< Low bit */ + unsigned int high : 5; /*!< High bit */ + unsigned int opcode : 4; /*!< Opcode (OPCODE_WR_REG) */ +} cmd_rd_reg; /*!< Format of RD_REG instruction */ + +/** +* Write literal value to a peripheral register +* +* reg[high_bit : low_bit] = val +* This instruction can access RTC_CNTL_, RTC_IO_, and SENS_ peripheral registers. +*/ +#define I_WR_REG(reg_addr, low_bit, high_bit, val) { *(unsigned int*)&(cmd_wr_reg ){ \ + .addr = reg_addr, \ + .data = val, \ + .low = low_bit, \ + .high = high_bit, \ + .opcode = OPCODE_WR_REG } } + +/** +* Read from peripheral register into R0 +* +* R0 = reg[high_bit : low_bit] +* This instruction can access RTC_CNTL_, RTC_IO_, and SENS_ peripheral registers. +*/ +#define I_RD_REG(reg_addr, low_bit, high_bit) { *(unsigned int*)&(cmd_rd_reg ){ \ + .addr = reg_addr, \ + .unused = 0, \ + .low = low_bit, \ + .high = high_bit, \ + .opcode = OPCODE_RD_REG } } + +// ------------------ RD/WR reg ------------------------ +#define OPCODE_I2C 3 /*!< Instruction: read/write I2C (not implemented yet) */ +#define OPCODE_I2C_RD 0 +#define OPCODE_I2C_WR 1 + +typedef struct { + unsigned int i2c_addr : 8; /*!< I2C slave address */ + unsigned int data : 8; /*!< Data to read or write */ + unsigned int low_bits : 3; /*!< TBD */ + unsigned int high_bits : 3; /*!< TBD */ + unsigned int i2c_sel : 4; /*!< TBD, select reg_i2c_slave_address[7:0] */ + unsigned int unused : 1; /*!< Unused */ + unsigned int rw_bit : 1; /*!< Write (1) or read (0) */ + unsigned int opcode : 4; /*!< Opcode (OPCODE_I2C) */ +} cmd_i2c; /*!< Format of I2C instruction */ + +#define I_I2C_RW(addr, val, low, high, sel, rw) { *(unsigned int*)&(cmd_i2c ){ \ + .i2c_addr = addr, \ + .data = val, \ + .low_bits = low, \ + .high_bits = high, \ + .i2c_sel = sel, \ + .unused = 0, \ + .rw_bit = rw, \ + .opcode = OPCODE_I2C } } + +// -------------------------------------------------------------------------- +#endif diff --git a/ld/Makefile.am b/ld/Makefile.am index 923550ed4e9..dd77ffab130 100644 --- a/ld/Makefile.am +++ b/ld/Makefile.am @@ -227,6 +227,7 @@ ALL_EMULATION_SOURCES = \ eelf32bfin.c \ eelf32bfinfd.c \ eelf32esp32ulp.c \ + eelf32esp32s2ulp.c \ eelf32cr16.c \ eelf32crx.c \ eelf32epiphany.c \ @@ -714,6 +715,7 @@ $(ALL_EMULATION_SOURCES) $(ALL_64_EMULATION_SOURCES): $(GEN_DEPENDS) @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32bfin.Pc@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32bfinfd.Pc@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32esp32ulp.Pc@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32esp32s2ulp.Pc@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32cr16.Pc@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32crx.Pc@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32epiphany.Pc@am__quote@ diff --git a/ld/Makefile.in b/ld/Makefile.in index 3ec60680398..12f81caf44a 100644 --- a/ld/Makefile.in +++ b/ld/Makefile.in @@ -710,6 +710,7 @@ ALL_EMULATION_SOURCES = \ eelf32bfin.c \ eelf32bfinfd.c \ eelf32esp32ulp.c \ + eelf32esp32s2ulp.c \ eelf32cr16.c \ eelf32crx.c \ eelf32epiphany.c \ @@ -1266,6 +1267,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32bfin.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32bfinfd.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32esp32ulp.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32esp32s2ulp.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32bmip.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32bmipn32.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32bsmip.Po@am__quote@ @@ -1273,7 +1275,6 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32btsmip_fbsd.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32btsmipn32.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32btsmipn32_fbsd.Po@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32esp32ulp.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32cr16.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32crx.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32ebmip.Po@am__quote@ diff --git a/ld/configure.tgt b/ld/configure.tgt index 825ec7e092e..840d8bbdfe6 100644 --- a/ld/configure.tgt +++ b/ld/configure.tgt @@ -218,6 +218,9 @@ bfin-*-linux-uclibc*) targ_emul=elf32bfinfd; ;; esp32ulp-*-elf) targ_emul=elf32esp32ulp; + ;; +esp32s2ulp-*-elf) targ_emul=elf32esp32s2ulp; + ;; bpf-*-*) targ_emul=elf64bpf ;; diff --git a/ld/emulparams/elf32esp32s2ulp.sh b/ld/emulparams/elf32esp32s2ulp.sh new file mode 100644 index 00000000000..30ac2cb1267 --- /dev/null +++ b/ld/emulparams/elf32esp32s2ulp.sh @@ -0,0 +1,12 @@ +SCRIPT_NAME=elf +OUTPUT_FORMAT="elf32-esp32s2ulp" +TEXT_START_ADDR=0x0 +MAXPAGESIZE="CONSTANT (MAXPAGESIZE)" +TARGET_PAGE_SIZE=0x1000 +ARCH=esp32s2ulp +MACHINE= +TEMPLATE_NAME=elf32 +GENERATE_SHLIB_SCRIPT=yes +EMBEDDED=yes +USER_LABEL_PREFIX=_ +EXTRA_EM_FILE=esp32s2ulp diff --git a/ld/emultempl/esp32s2ulp.em b/ld/emultempl/esp32s2ulp.em new file mode 100644 index 00000000000..e69de29bb2d diff --git a/opcodes/configure b/opcodes/configure old mode 100755 new mode 100644 index bb552814ea5..9cb113b5eaa --- a/opcodes/configure +++ b/opcodes/configure @@ -12871,6 +12871,7 @@ if test x${all_targets} = xfalse ; then bfd_avr_arch) ta="$ta avr-dis.lo" ;; bfd_bfin_arch) ta="$ta bfin-dis.lo" ;; bfd_esp32ulp_arch) ta="$ta esp32ulp-dis.lo" ;; + bfd_esp32s2ulp_arch)ta="$ta esp32s2ulp-dis.lo" ;; bfd_cr16_arch) ta="$ta cr16-dis.lo cr16-opc.lo" ;; bfd_cris_arch) ta="$ta cris-dis.lo cris-opc.lo cgen-bitset.lo" ;; bfd_crx_arch) ta="$ta crx-dis.lo crx-opc.lo" ;; diff --git a/opcodes/configure.ac b/opcodes/configure.ac index 553917e6618..24acd95703d 100644 --- a/opcodes/configure.ac +++ b/opcodes/configure.ac @@ -262,6 +262,7 @@ if test x${all_targets} = xfalse ; then bfd_avr_arch) ta="$ta avr-dis.lo" ;; bfd_bfin_arch) ta="$ta bfin-dis.lo" ;; bfd_esp32ulp_arch) ta="$ta esp32ulp-dis.lo" ;; + bfd_esp32s2ulp_arch)ta="$ta esp32s2ulp-dis.lo" ;; bfd_cr16_arch) ta="$ta cr16-dis.lo cr16-opc.lo" ;; bfd_cris_arch) ta="$ta cris-dis.lo cris-opc.lo cgen-bitset.lo" ;; bfd_crx_arch) ta="$ta crx-dis.lo crx-opc.lo" ;; diff --git a/opcodes/esp32s2ulp-dis.c b/opcodes/esp32s2ulp-dis.c new file mode 100644 index 00000000000..6ea386c3d97 --- /dev/null +++ b/opcodes/esp32s2ulp-dis.c @@ -0,0 +1,18 @@ +/* ESP32S2ULP ELF support for BFD. +Copyright (c) 2016-2017 Espressif Systems (Shanghai) PTE LTD. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, +Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ diff --git a/opcodes/esp32ulp-dis.c b/opcodes/esp32ulp-dis.c old mode 100755 new mode 100644 index b174cda9c55..656a8d46ddc --- a/opcodes/esp32ulp-dis.c +++ b/opcodes/esp32ulp-dis.c @@ -1,4 +1,4 @@ -/* ESPULP ELF support for BFD. +/* ESP32ULP ELF support for BFD. Copyright (c) 2016-2017 Espressif Systems (Shanghai) PTE LTD. This file is part of BFD, the Binary File Descriptor library.